[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciDxe / XhciReg.c

/** @file\r
\r
  The XHCI register operation routines.\r
\r
Copyright (c) 2011 - 2017, Intel Corporation. All rights reserved.<BR>\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include "Xhci.h"\r
\r
/**\r
  Read 1-byte width XHCI capability register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the 1-byte width capability register.\r
\r
  @return The register content read.\r
  @retval If err, return 0xFF.\r
\r
**/\r
UINT8\r
XhcReadCapReg8 (\r
  IN  USB_XHCI_INSTANCE  *Xhc,\r
  IN  UINT32             Offset\r
  )\r
{\r
  UINT8       Data;\r
  EFI_STATUS  Status;\r
\r
  Status = Xhc->PciIo->Mem.Read (\r
                             Xhc->PciIo,\r
                             EfiPciIoWidthUint8,\r
                             XHC_BAR_INDEX,\r
                             (UINT64)Offset,\r
                             1,\r
                             &Data\r
                             );\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((DEBUG_ERROR, "XhcReadCapReg: Pci Io read error - %r at %d\n", Status, Offset));\r
    Data = 0xFF;\r
  }\r
\r
  return Data;\r
}\r
\r
/**\r
  Read 4-bytes width XHCI capability register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the 4-bytes width capability register.\r
\r
  @return The register content read.\r
  @retval If err, return 0xFFFFFFFF.\r
\r
**/\r
UINT32\r
XhcReadCapReg (\r
  IN  USB_XHCI_INSTANCE  *Xhc,\r
  IN  UINT32             Offset\r
  )\r
{\r
  UINT32      Data;\r
  EFI_STATUS  Status;\r
\r
  Status = Xhc->PciIo->Mem.Read (\r
                             Xhc->PciIo,\r
                             EfiPciIoWidthUint32,\r
                             XHC_BAR_INDEX,\r
                             (UINT64)Offset,\r
                             1,\r
                             &Data\r
                             );\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((DEBUG_ERROR, "XhcReadCapReg: Pci Io read error - %r at %d\n", Status, Offset));\r
    Data = 0xFFFFFFFF;\r
  }\r
\r
  return Data;\r
}\r
\r
/**\r
  Read 4-bytes width XHCI Operational register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the 4-bytes width operational register.\r
\r
  @return The register content read.\r
  @retval If err, return 0xFFFFFFFF.\r
\r
**/\r
UINT32\r
XhcReadOpReg (\r
  IN  USB_XHCI_INSTANCE  *Xhc,\r
  IN  UINT32             Offset\r
  )\r
{\r
  UINT32      Data;\r
  EFI_STATUS  Status;\r
\r
  ASSERT (Xhc->CapLength != 0);\r
\r
  Status = Xhc->PciIo->Mem.Read (\r
                             Xhc->PciIo,\r
                             EfiPciIoWidthUint32,\r
                             XHC_BAR_INDEX,\r
                             Xhc->CapLength + Offset,\r
                             1,\r
                             &Data\r
                             );\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((DEBUG_ERROR, "XhcReadOpReg: Pci Io Read error - %r at %d\n", Status, Offset));\r
    Data = 0xFFFFFFFF;\r
  }\r
\r
  return Data;\r
}\r
\r
/**\r
  Write the data to the 4-bytes width XHCI operational register.\r
\r
  @param  Xhc      The XHCI Instance.\r
  @param  Offset   The offset of the 4-bytes width operational register.\r
  @param  Data     The data to write.\r
\r
**/\r
VOID\r
XhcWriteOpReg (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Data\r
  )\r
{\r
  EFI_STATUS  Status;\r
\r
  ASSERT (Xhc->CapLength != 0);\r
\r
  Status = Xhc->PciIo->Mem.Write (\r
                             Xhc->PciIo,\r
                             EfiPciIoWidthUint32,\r
                             XHC_BAR_INDEX,\r
                             Xhc->CapLength + Offset,\r
                             1,\r
                             &Data\r
                             );\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((DEBUG_ERROR, "XhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));\r
  }\r
}\r
\r
/**\r
  Write the data to the XHCI door bell register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the door bell register.\r
  @param  Data         The data to write.\r
\r
**/\r
VOID\r
XhcWriteDoorBellReg (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Data\r
  )\r
{\r
  EFI_STATUS  Status;\r
\r
  ASSERT (Xhc->DBOff != 0);\r
\r
  Status = Xhc->PciIo->Mem.Write (\r
                             Xhc->PciIo,\r
                             EfiPciIoWidthUint32,\r
                             XHC_BAR_INDEX,\r
                             Xhc->DBOff + Offset,\r
                             1,\r
                             &Data\r
                             );\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((DEBUG_ERROR, "XhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));\r
  }\r
}\r
\r
/**\r
  Read XHCI runtime register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcReadRuntimeReg (\r
  IN  USB_XHCI_INSTANCE  *Xhc,\r
  IN  UINT32             Offset\r
  )\r
{\r
  UINT32      Data;\r
  EFI_STATUS  Status;\r
\r
  ASSERT (Xhc->RTSOff != 0);\r
\r
  Status = Xhc->PciIo->Mem.Read (\r
                             Xhc->PciIo,\r
                             EfiPciIoWidthUint32,\r
                             XHC_BAR_INDEX,\r
                             Xhc->RTSOff + Offset,\r
                             1,\r
                             &Data\r
                             );\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((DEBUG_ERROR, "XhcReadRuntimeReg: Pci Io Read error - %r at %d\n", Status, Offset));\r
    Data = 0xFFFFFFFF;\r
  }\r
\r
  return Data;\r
}\r
\r
/**\r
  Write the data to the XHCI runtime register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
  @param  Data         The data to write.\r
\r
**/\r
VOID\r
XhcWriteRuntimeReg (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Data\r
  )\r
{\r
  EFI_STATUS  Status;\r
\r
  ASSERT (Xhc->RTSOff != 0);\r
\r
  Status = Xhc->PciIo->Mem.Write (\r
                             Xhc->PciIo,\r
                             EfiPciIoWidthUint32,\r
                             XHC_BAR_INDEX,\r
                             Xhc->RTSOff + Offset,\r
                             1,\r
                             &Data\r
                             );\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((DEBUG_ERROR, "XhcWriteRuntimeReg: Pci Io Write error: %r at %d\n", Status, Offset));\r
  }\r
}\r
\r
/**\r
  Read XHCI extended capability register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the extended capability register.\r
\r
  @return The register content read\r
\r
**/\r
UINT32\r
XhcReadExtCapReg (\r
  IN  USB_XHCI_INSTANCE  *Xhc,\r
  IN  UINT32             Offset\r
  )\r
{\r
  UINT32      Data;\r
  EFI_STATUS  Status;\r
\r
  ASSERT (Xhc->ExtCapRegBase != 0);\r
\r
  Status = Xhc->PciIo->Mem.Read (\r
                             Xhc->PciIo,\r
                             EfiPciIoWidthUint32,\r
                             XHC_BAR_INDEX,\r
                             Xhc->ExtCapRegBase + Offset,\r
                             1,\r
                             &Data\r
                             );\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((DEBUG_ERROR, "XhcReadExtCapReg: Pci Io Read error - %r at %d\n", Status, Offset));\r
    Data = 0xFFFFFFFF;\r
  }\r
\r
  return Data;\r
}\r
\r
/**\r
  Write the data to the XHCI extended capability register.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the extended capability register.\r
  @param  Data         The data to write.\r
\r
**/\r
VOID\r
XhcWriteExtCapReg (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Data\r
  )\r
{\r
  EFI_STATUS  Status;\r
\r
  ASSERT (Xhc->ExtCapRegBase != 0);\r
\r
  Status = Xhc->PciIo->Mem.Write (\r
                             Xhc->PciIo,\r
                             EfiPciIoWidthUint32,\r
                             XHC_BAR_INDEX,\r
                             Xhc->ExtCapRegBase + Offset,\r
                             1,\r
                             &Data\r
                             );\r
\r
  if (EFI_ERROR (Status)) {\r
    DEBUG ((DEBUG_ERROR, "XhcWriteExtCapReg: Pci Io Write error: %r at %d\n", Status, Offset));\r
  }\r
}\r
\r
/**\r
  Set one bit of the runtime register while keeping other bits.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcSetRuntimeRegBit (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Bit\r
  )\r
{\r
  UINT32  Data;\r
\r
  Data  = XhcReadRuntimeReg (Xhc, Offset);\r
  Data |= Bit;\r
  XhcWriteRuntimeReg (Xhc, Offset, Data);\r
}\r
\r
/**\r
  Clear one bit of the runtime register while keeping other bits.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the runtime register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcClearRuntimeRegBit (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Bit\r
  )\r
{\r
  UINT32  Data;\r
\r
  Data  = XhcReadRuntimeReg (Xhc, Offset);\r
  Data &= ~Bit;\r
  XhcWriteRuntimeReg (Xhc, Offset, Data);\r
}\r
\r
/**\r
  Set one bit of the operational register while keeping other bits.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit mask of the register to set.\r
\r
**/\r
VOID\r
XhcSetOpRegBit (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Bit\r
  )\r
{\r
  UINT32  Data;\r
\r
  Data  = XhcReadOpReg (Xhc, Offset);\r
  Data |= Bit;\r
  XhcWriteOpReg (Xhc, Offset, Data);\r
}\r
\r
/**\r
  Clear one bit of the operational register while keeping other bits.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Offset       The offset of the operational register.\r
  @param  Bit          The bit mask of the register to clear.\r
\r
**/\r
VOID\r
XhcClearOpRegBit (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Bit\r
  )\r
{\r
  UINT32  Data;\r
\r
  Data  = XhcReadOpReg (Xhc, Offset);\r
  Data &= ~Bit;\r
  XhcWriteOpReg (Xhc, Offset, Data);\r
}\r
\r
/**\r
  Wait the operation register's bit as specified by Bit\r
  to become set (or clear).\r
\r
  @param  Xhc                    The XHCI Instance.\r
  @param  Offset                 The offset of the operation register.\r
  @param  Bit                    The bit of the register to wait for.\r
  @param  WaitToSet              Wait the bit to set or clear.\r
  @param  Timeout                The time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS            The bit successfully changed by host controller.\r
  @retval EFI_TIMEOUT            The time out occurred.\r
  @retval EFI_OUT_OF_RESOURCES   Memory for the timer event could not be allocated.\r
\r
**/\r
EFI_STATUS\r
XhcWaitOpRegBit (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT32             Offset,\r
  IN UINT32             Bit,\r
  IN BOOLEAN            WaitToSet,\r
  IN UINT32             Timeout\r
  )\r
{\r
  EFI_STATUS  Status;\r
  EFI_EVENT   TimeoutEvent;\r
\r
  TimeoutEvent = NULL;\r
\r
  if (Timeout == 0) {\r
    return EFI_TIMEOUT;\r
  }\r
\r
  Status = gBS->CreateEvent (\r
                  EVT_TIMER,\r
                  TPL_CALLBACK,\r
                  NULL,\r
                  NULL,\r
                  &TimeoutEvent\r
                  );\r
\r
  if (EFI_ERROR (Status)) {\r
    goto DONE;\r
  }\r
\r
  Status = gBS->SetTimer (\r
                  TimeoutEvent,\r
                  TimerRelative,\r
                  EFI_TIMER_PERIOD_MILLISECONDS (Timeout)\r
                  );\r
\r
  if (EFI_ERROR (Status)) {\r
    goto DONE;\r
  }\r
\r
  do {\r
    if (XHC_REG_BIT_IS_SET (Xhc, Offset, Bit) == WaitToSet) {\r
      Status = EFI_SUCCESS;\r
      goto DONE;\r
    }\r
\r
    gBS->Stall (XHC_1_MICROSECOND);\r
  } while (EFI_ERROR (gBS->CheckEvent (TimeoutEvent)));\r
\r
  Status = EFI_TIMEOUT;\r
\r
DONE:\r
  if (TimeoutEvent != NULL) {\r
    gBS->CloseEvent (TimeoutEvent);\r
  }\r
\r
  return Status;\r
}\r
\r
/**\r
  Set Bios Ownership\r
\r
  @param  Xhc          The XHCI Instance.\r
\r
**/\r
VOID\r
XhcSetBiosOwnership (\r
  IN USB_XHCI_INSTANCE  *Xhc\r
  )\r
{\r
  UINT32  Buffer;\r
\r
  if (Xhc->UsbLegSupOffset == 0xFFFFFFFF) {\r
    return;\r
  }\r
\r
  DEBUG ((DEBUG_INFO, "XhcSetBiosOwnership: called to set BIOS ownership\n"));\r
\r
  Buffer = XhcReadExtCapReg (Xhc, Xhc->UsbLegSupOffset);\r
  Buffer = ((Buffer & (~USBLEGSP_OS_SEMAPHORE)) | USBLEGSP_BIOS_SEMAPHORE);\r
  XhcWriteExtCapReg (Xhc, Xhc->UsbLegSupOffset, Buffer);\r
}\r
\r
/**\r
  Clear Bios Ownership\r
\r
  @param  Xhc       The XHCI Instance.\r
\r
**/\r
VOID\r
XhcClearBiosOwnership (\r
  IN USB_XHCI_INSTANCE  *Xhc\r
  )\r
{\r
  UINT32  Buffer;\r
\r
  if (Xhc->UsbLegSupOffset == 0xFFFFFFFF) {\r
    return;\r
  }\r
\r
  DEBUG ((DEBUG_INFO, "XhcClearBiosOwnership: called to clear BIOS ownership\n"));\r
\r
  Buffer = XhcReadExtCapReg (Xhc, Xhc->UsbLegSupOffset);\r
  Buffer = ((Buffer & (~USBLEGSP_BIOS_SEMAPHORE)) | USBLEGSP_OS_SEMAPHORE);\r
  XhcWriteExtCapReg (Xhc, Xhc->UsbLegSupOffset, Buffer);\r
}\r
\r
/**\r
  Calculate the offset of the XHCI capability.\r
\r
  @param  Xhc     The XHCI Instance.\r
  @param  CapId   The XHCI Capability ID.\r
\r
  @return The offset of XHCI legacy support capability register.\r
\r
**/\r
UINT32\r
XhcGetCapabilityAddr (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT8              CapId\r
  )\r
{\r
  UINT32  ExtCapOffset;\r
  UINT8   NextExtCapReg;\r
  UINT32  Data;\r
\r
  ExtCapOffset = 0;\r
\r
  do {\r
    //\r
    // Check if the extended capability register's capability id is USB Legacy Support.\r
    //\r
    Data = XhcReadExtCapReg (Xhc, ExtCapOffset);\r
    if ((Data & 0xFF) == CapId) {\r
      return ExtCapOffset;\r
    }\r
\r
    //\r
    // If not, then traverse all of the ext capability registers till finding out it.\r
    //\r
    NextExtCapReg = (UINT8)((Data >> 8) & 0xFF);\r
    ExtCapOffset += (NextExtCapReg << 2);\r
  } while (NextExtCapReg != 0);\r
\r
  return 0xFFFFFFFF;\r
}\r
\r
/**\r
  Calculate the offset of the xHCI Supported Protocol Capability.\r
\r
  @param  Xhc           The XHCI Instance.\r
  @param  MajorVersion  The USB Major Version in xHCI Support Protocol Capability Field\r
\r
  @return The offset of xHCI Supported Protocol capability register.\r
\r
**/\r
UINT32\r
XhcGetSupportedProtocolCapabilityAddr (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT8              MajorVersion\r
  )\r
{\r
  UINT32                      ExtCapOffset;\r
  UINT8                       NextExtCapReg;\r
  UINT32                      Data;\r
  UINT32                      NameString;\r
  XHC_SUPPORTED_PROTOCOL_DW0  UsbSupportDw0;\r
\r
  if (Xhc == NULL) {\r
    return 0;\r
  }\r
\r
  ExtCapOffset = 0;\r
\r
  do {\r
    //\r
    // Check if the extended capability register's capability id is USB Legacy Support.\r
    //\r
    Data                = XhcReadExtCapReg (Xhc, ExtCapOffset);\r
    UsbSupportDw0.Dword = Data;\r
    if ((Data & 0xFF) == XHC_CAP_USB_SUPPORTED_PROTOCOL) {\r
      if (UsbSupportDw0.Data.RevMajor == MajorVersion) {\r
        NameString = XhcReadExtCapReg (Xhc, ExtCapOffset + XHC_SUPPORTED_PROTOCOL_NAME_STRING_OFFSET);\r
        if (NameString == XHC_SUPPORTED_PROTOCOL_NAME_STRING_VALUE) {\r
          //\r
          // Ensure Name String field is xHCI supported protocols in xHCI Supported Protocol Capability Offset 04h\r
          //\r
          return ExtCapOffset;\r
        }\r
      }\r
    }\r
\r
    //\r
    // If not, then traverse all of the ext capability registers till finding out it.\r
    //\r
    NextExtCapReg = (UINT8)((Data >> 8) & 0xFF);\r
    ExtCapOffset += (NextExtCapReg << 2);\r
  } while (NextExtCapReg != 0);\r
\r
  return 0xFFFFFFFF;\r
}\r
\r
/**\r
  Find PortSpeed value match Protocol Speed ID Value (PSIV).\r
\r
  @param  Xhc            The XHCI Instance.\r
  @param  ExtCapOffset   The USB Major Version in xHCI Support Protocol Capability Field\r
  @param  PortSpeed      The Port Speed Field in USB PortSc register\r
  @param  PortNumber     The Port Number (0-indexed)\r
\r
  @return The Protocol Speed ID (PSI) from xHCI Supported Protocol capability register.\r
\r
**/\r
UINT32\r
XhciPsivGetPsid (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT32             ExtCapOffset,\r
  IN UINT8              PortSpeed,\r
  IN UINT8              PortNumber\r
  )\r
{\r
  XHC_SUPPORTED_PROTOCOL_DW2                PortId;\r
  XHC_SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID  Reg;\r
  UINT32                                    Count;\r
  UINT32                                    MinPortIndex;\r
  UINT32                                    MaxPortIndex;\r
\r
  if ((Xhc == NULL) || (ExtCapOffset == 0xFFFFFFFF)) {\r
    return 0;\r
  }\r
\r
  //\r
  // According to XHCI 1.1 spec November 2017,\r
  // Section 7.2 xHCI Supported Protocol Capability\r
  // 1. Get the PSIC(Protocol Speed ID Count) value.\r
  // 2. The PSID register boundary should be Base address + PSIC * 0x04\r
  //\r
  PortId.Dword = XhcReadExtCapReg (Xhc, ExtCapOffset + XHC_SUPPORTED_PROTOCOL_DW2_OFFSET);\r
\r
  //\r
  // According to XHCI 1.1 spec November 2017, valid values\r
  // for CompPortOffset are 1 to CompPortCount - 1.\r
  //\r
  // PortNumber is zero-indexed, so subtract 1.\r
  //\r
  if ((PortId.Data.CompPortOffset == 0) || (PortId.Data.CompPortCount == 0)) {\r
    return 0;\r
  }\r
\r
  MinPortIndex = PortId.Data.CompPortOffset - 1;\r
  MaxPortIndex = MinPortIndex + PortId.Data.CompPortCount - 1;\r
\r
  if ((PortNumber < MinPortIndex) || (PortNumber > MaxPortIndex)) {\r
    return 0;\r
  }\r
\r
  for (Count = 0; Count < PortId.Data.Psic; Count++) {\r
    Reg.Dword = XhcReadExtCapReg (Xhc, ExtCapOffset + XHC_SUPPORTED_PROTOCOL_PSI_OFFSET + (Count << 2));\r
    if (Reg.Data.Psiv == PortSpeed) {\r
      return Reg.Dword;\r
    }\r
  }\r
\r
  return 0;\r
}\r
\r
/**\r
  Find PortSpeed value match case in XHCI Supported Protocol Capability\r
\r
  @param  Xhc         The XHCI Instance.\r
  @param  PortSpeed   The Port Speed Field in USB PortSc register\r
  @param  PortNumber  The Port Number (0-indexed)\r
\r
  @return The USB Port Speed.\r
\r
**/\r
UINT16\r
XhcCheckUsbPortSpeedUsedPsic (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT8              PortSpeed,\r
  IN UINT8              PortNumber\r
  )\r
{\r
  XHC_SUPPORTED_PROTOCOL_PROTOCOL_SPEED_ID  SpField;\r
  UINT16                                    UsbSpeedIdMap;\r
\r
  if (Xhc == NULL) {\r
    return 0;\r
  }\r
\r
  SpField.Dword = 0;\r
  UsbSpeedIdMap = 0;\r
\r
  //\r
  // Check xHCI Supported Protocol Capability, find the PSIV field to match\r
  // PortSpeed definition when the Major Revision is 03h.\r
  //\r
  if (Xhc->Usb3SupOffset != 0xFFFFFFFF) {\r
    SpField.Dword = XhciPsivGetPsid (Xhc, Xhc->Usb3SupOffset, PortSpeed, PortNumber);\r
    if (SpField.Dword != 0) {\r
      //\r
      // Found the corresponding PORTSC value in PSIV field of USB3 offset.\r
      //\r
      UsbSpeedIdMap = USB_PORT_STAT_SUPER_SPEED;\r
    }\r
  }\r
\r
  //\r
  // Check xHCI Supported Protocol Capability, find the PSIV field to match\r
  // PortSpeed definition when the Major Revision is 02h.\r
  //\r
  if ((UsbSpeedIdMap == 0) && (Xhc->Usb2SupOffset != 0xFFFFFFFF)) {\r
    SpField.Dword = XhciPsivGetPsid (Xhc, Xhc->Usb2SupOffset, PortSpeed, PortNumber);\r
    if (SpField.Dword != 0) {\r
      //\r
      // Found the corresponding PORTSC value in PSIV field of USB2 offset.\r
      //\r
      if (SpField.Data.Psie == 2) {\r
        //\r
        // According to XHCI 1.1 spec November 2017,\r
        // Section 7.2.1 the Protocol Speed ID Exponent (PSIE) field definition,\r
        // PSIE value shall be applied to Protocol Speed ID Mantissa when calculating, value 2 shall represent bit rate in Mb/s\r
        //\r
        if (SpField.Data.Psim == XHC_SUPPORTED_PROTOCOL_USB2_HIGH_SPEED_PSIM) {\r
          //\r
          // PSIM shows as default High-speed protocol, apply to High-speed mapping\r
          //\r
          UsbSpeedIdMap = USB_PORT_STAT_HIGH_SPEED;\r
        }\r
      } else if (SpField.Data.Psie == 1) {\r
        //\r
        // According to XHCI 1.1 spec November 2017,\r
        // Section 7.2.1 the Protocol Speed ID Exponent (PSIE) field definition,\r
        // PSIE value shall be applied to Protocol Speed ID Mantissa when calculating, value 1 shall represent bit rate in Kb/s\r
        //\r
        if (SpField.Data.Psim == XHC_SUPPORTED_PROTOCOL_USB2_LOW_SPEED_PSIM) {\r
          //\r
          // PSIM shows as default Low-speed protocol, apply to Low-speed mapping\r
          //\r
          UsbSpeedIdMap = USB_PORT_STAT_LOW_SPEED;\r
        }\r
      }\r
    }\r
  }\r
\r
  return UsbSpeedIdMap;\r
}\r
\r
/**\r
  Whether the XHCI host controller is halted.\r
\r
  @param  Xhc     The XHCI Instance.\r
\r
  @retval TRUE    The controller is halted.\r
  @retval FALSE   It isn't halted.\r
\r
**/\r
BOOLEAN\r
XhcIsHalt (\r
  IN USB_XHCI_INSTANCE  *Xhc\r
  )\r
{\r
  return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT);\r
}\r
\r
/**\r
  Whether system error occurred.\r
\r
  @param  Xhc      The XHCI Instance.\r
\r
  @retval TRUE     System error happened.\r
  @retval FALSE    No system error.\r
\r
**/\r
BOOLEAN\r
XhcIsSysError (\r
  IN USB_XHCI_INSTANCE  *Xhc\r
  )\r
{\r
  return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HSE);\r
}\r
\r
/**\r
  Set USBCMD Host System Error Enable(HSEE) Bit if PCICMD SERR# Enable Bit is set.\r
\r
  The USBCMD HSEE Bit will be reset to default 0 by USBCMD Host Controller Reset(HCRST).\r
  This function is to set USBCMD HSEE Bit if PCICMD SERR# Enable Bit is set.\r
\r
  @param Xhc            The XHCI Instance.\r
\r
**/\r
VOID\r
XhcSetHsee (\r
  IN USB_XHCI_INSTANCE  *Xhc\r
  )\r
{\r
  EFI_STATUS           Status;\r
  EFI_PCI_IO_PROTOCOL  *PciIo;\r
  UINT16               XhciCmd;\r
\r
  PciIo  = Xhc->PciIo;\r
  Status = PciIo->Pci.Read (\r
                        PciIo,\r
                        EfiPciIoWidthUint16,\r
                        PCI_COMMAND_OFFSET,\r
                        sizeof (XhciCmd) / sizeof (UINT16),\r
                        &XhciCmd\r
                        );\r
  if (!EFI_ERROR (Status)) {\r
    if ((XhciCmd & EFI_PCI_COMMAND_SERR) != 0) {\r
      XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_HSEE);\r
    }\r
  }\r
}\r
\r
/**\r
  Reset the XHCI host controller.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @retval EFI_SUCCESS  The XHCI host controller is reset.\r
  @return Others       Failed to reset the XHCI before Timeout.\r
\r
**/\r
EFI_STATUS\r
XhcResetHC (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT32             Timeout\r
  )\r
{\r
  EFI_STATUS  Status;\r
\r
  Status = EFI_SUCCESS;\r
\r
  DEBUG ((DEBUG_INFO, "XhcResetHC!\n"));\r
  //\r
  // Host can only be reset when it is halt. If not so, halt it\r
  //\r
  if (!XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT)) {\r
    Status = XhcHaltHC (Xhc, Timeout);\r
\r
    if (EFI_ERROR (Status)) {\r
      return Status;\r
    }\r
  }\r
\r
  if ((Xhc->DebugCapSupOffset == 0xFFFFFFFF) || ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) != XHC_CAP_USB_DEBUG) ||\r
      ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) == 0))\r
  {\r
    XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);\r
    //\r
    // Some XHCI host controllers require to have extra 1ms delay before accessing any MMIO register during reset.\r
    // Otherwise there may have the timeout case happened.\r
    // The below is a workaround to solve such problem.\r
    //\r
    gBS->Stall (XHC_1_MILLISECOND);\r
    Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);\r
\r
    if (!EFI_ERROR (Status)) {\r
      //\r
      // The USBCMD HSEE Bit will be reset to default 0 by USBCMD HCRST.\r
      // Set USBCMD HSEE Bit if PCICMD SERR# Enable Bit is set.\r
      //\r
      XhcSetHsee (Xhc);\r
    }\r
  }\r
\r
  return Status;\r
}\r
\r
/**\r
  Halt the XHCI host controller.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @return EFI_SUCCESS  The XHCI host controller is halt.\r
  @return EFI_TIMEOUT  Failed to halt the XHCI before Timeout.\r
\r
**/\r
EFI_STATUS\r
XhcHaltHC (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT32             Timeout\r
  )\r
{\r
  EFI_STATUS  Status;\r
\r
  XhcClearOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);\r
  Status = XhcWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, TRUE, Timeout);\r
  return Status;\r
}\r
\r
/**\r
  Set the XHCI host controller to run.\r
\r
  @param  Xhc          The XHCI Instance.\r
  @param  Timeout      Time to wait before abort (in millisecond, ms).\r
\r
  @return EFI_SUCCESS  The XHCI host controller is running.\r
  @return EFI_TIMEOUT  Failed to set the XHCI to run before Timeout.\r
\r
**/\r
EFI_STATUS\r
XhcRunHC (\r
  IN USB_XHCI_INSTANCE  *Xhc,\r
  IN UINT32             Timeout\r
  )\r
{\r
  EFI_STATUS  Status;\r
\r
  XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);\r
  Status = XhcWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, FALSE, Timeout);\r
  return Status;\r
}\r