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MdeModulePkg: add generic SataController driver.
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1/** @file\r
2Private Header file for Usb Host Controller PEIM\r
3\r
26cd2d6d 4Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
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5\r
6This program and the accompanying materials\r
7are licensed and made available under the terms and conditions\r
8of the BSD License which accompanies this distribution. The\r
9full text of the license may be found at\r
10http://opensource.org/licenses/bsd-license.php\r
11\r
12THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
13WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
14\r
15**/\r
16\r
17#ifndef _RECOVERY_XHC_H_\r
18#define _RECOVERY_XHC_H_\r
19\r
20#include <PiPei.h>\r
21\r
22#include <Ppi/UsbController.h>\r
23#include <Ppi/Usb2HostController.h>\r
24\r
25#include <Library/DebugLib.h>\r
26#include <Library/PeimEntryPoint.h>\r
27#include <Library/PeiServicesLib.h>\r
28#include <Library/BaseMemoryLib.h>\r
29#include <Library/TimerLib.h>\r
30#include <Library/IoLib.h>\r
31#include <Library/MemoryAllocationLib.h>\r
32\r
33typedef struct _PEI_XHC_DEV PEI_XHC_DEV;\r
34typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;\r
35\r
36#include "UsbHcMem.h"\r
37#include "XhciReg.h"\r
38#include "XhciSched.h"\r
39\r
40#define CMD_RING_TRB_NUMBER 0x100\r
41#define TR_RING_TRB_NUMBER 0x100\r
42#define ERST_NUMBER 0x01\r
43#define EVENT_RING_TRB_NUMBER 0x200\r
44\r
45#define XHC_1_MICROSECOND 1\r
46#define XHC_1_MILLISECOND (1000 * XHC_1_MICROSECOND)\r
47#define XHC_1_SECOND (1000 * XHC_1_MILLISECOND)\r
48\r
49//\r
50// XHC reset timeout experience values.\r
26cd2d6d 51// The unit is millisecond, setting it as 1s.\r
d987459f 52//\r
26cd2d6d 53#define XHC_RESET_TIMEOUT (1000)\r
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54\r
55//\r
56// Wait for root port state stable.\r
57//\r
58#define XHC_ROOT_PORT_STATE_STABLE (200 * XHC_1_MILLISECOND)\r
59\r
26cd2d6d
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60//\r
61// XHC generic timeout experience values.\r
62// The unit is millisecond, setting it as 10s.\r
63//\r
64#define XHC_GENERIC_TIMEOUT (10 * 1000)\r
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65\r
66#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))\r
67#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))\r
68#define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))\r
69\r
70#define XHC_REG_BIT_IS_SET(XHC, Offset, Bit) \\r
71 (XHC_BIT_IS_SET(XhcPeiReadOpReg ((XHC), (Offset)), (Bit)))\r
72\r
73#define USB_DESC_TYPE_HUB 0x29\r
74#define USB_DESC_TYPE_HUB_SUPER_SPEED 0x2a\r
75\r
76//\r
77// The RequestType in EFI_USB_DEVICE_REQUEST is composed of\r
78// three fields: One bit direction, 2 bit type, and 5 bit\r
79// target.\r
80//\r
81#define USB_REQUEST_TYPE(Dir, Type, Target) \\r
82 ((UINT8)((((Dir) == EfiUsbDataIn ? 0x01 : 0) << 7) | (Type) | (Target)))\r
83\r
84struct _USB_DEV_CONTEXT {\r
85 //\r
86 // Whether this entry in UsbDevContext array is used or not.\r
87 //\r
88 BOOLEAN Enabled;\r
89 //\r
90 // The slot id assigned to the new device through XHCI's Enable_Slot cmd.\r
91 //\r
92 UINT8 SlotId;\r
93 //\r
94 // The route string presented an attached usb device.\r
95 //\r
96 USB_DEV_ROUTE RouteString;\r
97 //\r
98 // The route string of parent device if it exists. Otherwise it's zero.\r
99 //\r
100 USB_DEV_ROUTE ParentRouteString;\r
101 //\r
102 // The actual device address assigned by XHCI through Address_Device command.\r
103 //\r
104 UINT8 XhciDevAddr;\r
105 //\r
106 // The requested device address from UsbBus driver through Set_Address standard usb request.\r
107 // As XHCI spec replaces this request with Address_Device command, we have to record the\r
108 // requested device address and establish a mapping relationship with the actual device address.\r
109 // Then UsbBus driver just need to be aware of the requested device address to access usb device\r
110 // through EFI_USB2_HC_PROTOCOL. Xhci driver would be responsible for translating it to actual\r
111 // device address and access the actual device.\r
112 //\r
113 UINT8 BusDevAddr;\r
114 //\r
115 // The pointer to the input device context.\r
116 //\r
117 VOID *InputContext;\r
118 //\r
119 // The pointer to the output device context.\r
120 //\r
121 VOID *OutputContext;\r
122 //\r
123 // The transfer queue for every endpoint.\r
124 //\r
125 VOID *EndpointTransferRing[31];\r
126 //\r
127 // The device descriptor which is stored to support XHCI's Evaluate_Context cmd.\r
128 //\r
129 EFI_USB_DEVICE_DESCRIPTOR DevDesc;\r
130 //\r
131 // As a usb device may include multiple configuration descriptors, we dynamically allocate an array\r
132 // to store them.\r
133 // Note that every configuration descriptor stored here includes those lower level descriptors,\r
134 // such as Interface descriptor, Endpoint descriptor, and so on.\r
135 // These information is used to support XHCI's Config_Endpoint cmd.\r
136 //\r
137 EFI_USB_CONFIG_DESCRIPTOR **ConfDesc;\r
138};\r
139\r
140#define USB_XHC_DEV_SIGNATURE SIGNATURE_32 ('x', 'h', 'c', 'i')\r
141\r
142struct _PEI_XHC_DEV {\r
143 UINTN Signature;\r
144 PEI_USB2_HOST_CONTROLLER_PPI Usb2HostControllerPpi;\r
145 EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;\r
146 UINT32 UsbHostControllerBaseAddress;\r
147 USBHC_MEM_POOL *MemPool;\r
148\r
149 //\r
150 // XHCI configuration data\r
151 //\r
152 UINT8 CapLength; ///< Capability Register Length\r
153 XHC_HCSPARAMS1 HcSParams1; ///< Structural Parameters 1\r
154 XHC_HCSPARAMS2 HcSParams2; ///< Structural Parameters 2\r
155 XHC_HCCPARAMS HcCParams; ///< Capability Parameters\r
156 UINT32 DBOff; ///< Doorbell Offset\r
157 UINT32 RTSOff; ///< Runtime Register Space Offset\r
158 UINT32 PageSize;\r
159 UINT32 MaxScratchpadBufs;\r
160 UINT64 *ScratchBuf;\r
161 UINT64 *ScratchEntry;\r
162 UINT64 *DCBAA;\r
163 UINT32 MaxSlotsEn;\r
164 //\r
165 // Cmd Transfer Ring\r
166 //\r
167 TRANSFER_RING CmdRing;\r
168 //\r
169 // EventRing\r
170 //\r
171 EVENT_RING EventRing;\r
172\r
173 //\r
174 // Store device contexts managed by XHCI device\r
175 // The array supports up to 255 devices, entry 0 is reserved and should not be used.\r
176 //\r
177 USB_DEV_CONTEXT UsbDevContext[256];\r
178};\r
179\r
180#define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS(a) CR (a, PEI_XHC_DEV, Usb2HostControllerPpi, USB_XHC_DEV_SIGNATURE)\r
181\r
182/**\r
183 Initialize the memory management pool for the host controller.\r
184\r
185 @return Pointer to the allocated memory pool or NULL if failed.\r
186\r
187**/\r
188USBHC_MEM_POOL *\r
189UsbHcInitMemPool (\r
190 VOID\r
191 )\r
192;\r
193\r
194/**\r
195 Release the memory management pool.\r
196\r
197 @param Pool The USB memory pool to free.\r
198\r
199**/\r
200VOID\r
201UsbHcFreeMemPool (\r
202 IN USBHC_MEM_POOL *Pool\r
203 )\r
204;\r
205\r
206/**\r
207 Allocate some memory from the host controller's memory pool\r
208 which can be used to communicate with host controller.\r
209\r
210 @param Pool The host controller's memory pool.\r
211 @param Size Size of the memory to allocate.\r
212\r
213 @return The allocated memory or NULL.\r
214\r
215**/\r
216VOID *\r
217UsbHcAllocateMem (\r
218 IN USBHC_MEM_POOL *Pool,\r
219 IN UINTN Size\r
220 )\r
221;\r
222\r
223/**\r
224 Free the allocated memory back to the memory pool.\r
225\r
226 @param Pool The memory pool of the host controller.\r
227 @param Mem The memory to free.\r
228 @param Size The size of the memory to free.\r
229\r
230**/\r
231VOID\r
232UsbHcFreeMem (\r
233 IN USBHC_MEM_POOL *Pool,\r
234 IN VOID *Mem,\r
235 IN UINTN Size\r
236 )\r
237;\r
238\r
239#endif\r