MdeModulePkg/Xhci: Remove TDs from transfer ring when timeout happens

[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciPei / XhciSched.h

/** @file\r
Private Header file for Usb Host Controller PEIM\r
\r
Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions\r
of the BSD License which accompanies this distribution.  The\r
full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _EFI_PEI_XHCI_SCHED_H_\r
#define _EFI_PEI_XHCI_SCHED_H_\r
\r
//\r
// Transfer types, used in URB to identify the transfer type\r
//\r
#define XHC_CTRL_TRANSFER                       0x01\r
#define XHC_BULK_TRANSFER                       0x02\r
\r
//\r
// 6.4.6 TRB Types\r
//\r
#define TRB_TYPE_NORMAL                         1\r
#define TRB_TYPE_SETUP_STAGE                    2\r
#define TRB_TYPE_DATA_STAGE                     3\r
#define TRB_TYPE_STATUS_STAGE                   4\r
#define TRB_TYPE_ISOCH                          5\r
#define TRB_TYPE_LINK                           6\r
#define TRB_TYPE_EVENT_DATA                     7\r
#define TRB_TYPE_NO_OP                          8\r
#define TRB_TYPE_EN_SLOT                        9\r
#define TRB_TYPE_DIS_SLOT                       10\r
#define TRB_TYPE_ADDRESS_DEV                    11\r
#define TRB_TYPE_CON_ENDPOINT                   12\r
#define TRB_TYPE_EVALU_CONTXT                   13\r
#define TRB_TYPE_RESET_ENDPOINT                 14\r
#define TRB_TYPE_STOP_ENDPOINT                  15\r
#define TRB_TYPE_SET_TR_DEQUE                   16\r
#define TRB_TYPE_RESET_DEV                      17\r
#define TRB_TYPE_GET_PORT_BANW                  21\r
#define TRB_TYPE_FORCE_HEADER                   22\r
#define TRB_TYPE_NO_OP_COMMAND                  23\r
#define TRB_TYPE_TRANS_EVENT                    32\r
#define TRB_TYPE_COMMAND_COMPLT_EVENT           33\r
#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT       34\r
#define TRB_TYPE_HOST_CONTROLLER_EVENT          37\r
#define TRB_TYPE_DEVICE_NOTIFI_EVENT            38\r
#define TRB_TYPE_MFINDEX_WRAP_EVENT             39\r
\r
//\r
// Endpoint Type (EP Type).\r
//\r
#define ED_NOT_VALID                            0\r
#define ED_ISOCH_OUT                            1\r
#define ED_BULK_OUT                             2\r
#define ED_INTERRUPT_OUT                        3\r
#define ED_CONTROL_BIDIR                        4\r
#define ED_ISOCH_IN                             5\r
#define ED_BULK_IN                              6\r
#define ED_INTERRUPT_IN                         7\r
\r
//\r
// 6.4.5 TRB Completion Codes\r
//\r
#define TRB_COMPLETION_INVALID                  0\r
#define TRB_COMPLETION_SUCCESS                  1\r
#define TRB_COMPLETION_DATA_BUFFER_ERROR        2\r
#define TRB_COMPLETION_BABBLE_ERROR             3\r
#define TRB_COMPLETION_USB_TRANSACTION_ERROR    4\r
#define TRB_COMPLETION_TRB_ERROR                5\r
#define TRB_COMPLETION_STALL_ERROR              6\r
#define TRB_COMPLETION_SHORT_PACKET             13\r
\r
//\r
// The topology string used to present usb device location\r
//\r
typedef struct _USB_DEV_TOPOLOGY {\r
  //\r
  // The tier concatenation of down stream port.\r
  //\r
  UINT32 RouteString:20;\r
  //\r
  // The root port number of the chain.\r
  //\r
  UINT32 RootPortNum:8;\r
  //\r
  // The Tier the device reside.\r
  //\r
  UINT32 TierNum:4;\r
} USB_DEV_TOPOLOGY;\r
\r
//\r
// USB Device's RouteChart\r
//\r
typedef union _USB_DEV_ROUTE {\r
  UINT32                    Dword;\r
  USB_DEV_TOPOLOGY          Route;\r
} USB_DEV_ROUTE;\r
\r
//\r
// Endpoint address and its capabilities\r
//\r
typedef struct _USB_ENDPOINT {\r
  //\r
  // Store logical device address assigned by UsbBus\r
  // It's because some XHCI host controllers may assign the same physcial device\r
  // address for those devices inserted at different root port.\r
  //\r
  UINT8                     BusAddr;\r
  UINT8                     DevAddr;\r
  UINT8                     EpAddr;\r
  EFI_USB_DATA_DIRECTION    Direction;\r
  UINT8                     DevSpeed;\r
  UINTN                     MaxPacket;\r
  UINTN                     Type;\r
} USB_ENDPOINT;\r
\r
//\r
// TRB Template\r
//\r
typedef struct _TRB_TEMPLATE {\r
  UINT32                    Parameter1;\r
\r
  UINT32                    Parameter2;\r
\r
  UINT32                    Status;\r
\r
  UINT32                    CycleBit:1;\r
  UINT32                    RsvdZ1:9;\r
  UINT32                    Type:6;\r
  UINT32                    Control:16;\r
} TRB_TEMPLATE;\r
\r
typedef struct _TRANSFER_RING {\r
  VOID                      *RingSeg0;\r
  UINTN                     TrbNumber;\r
  TRB_TEMPLATE              *RingEnqueue;\r
  TRB_TEMPLATE              *RingDequeue;\r
  UINT32                    RingPCS;\r
} TRANSFER_RING;\r
\r
typedef struct _EVENT_RING {\r
  VOID                      *ERSTBase;\r
  VOID                      *EventRingSeg0;\r
  UINTN                     TrbNumber;\r
  TRB_TEMPLATE              *EventRingEnqueue;\r
  TRB_TEMPLATE              *EventRingDequeue;\r
  UINT32                    EventRingCCS;\r
} EVENT_RING;\r
\r
#define XHC_URB_SIG                 SIGNATURE_32 ('U', 'S', 'B', 'R')\r
\r
//\r
// URB (Usb Request Block) contains information for all kinds of\r
// usb requests.\r
//\r
typedef struct _URB {\r
  UINT32                            Signature;\r
  //\r
  // Usb Device URB related information\r
  //\r
  USB_ENDPOINT                      Ep;\r
  EFI_USB_DEVICE_REQUEST            *Request;\r
  VOID                              *Data;\r
  UINTN                             DataLen;\r
  VOID                              *DataPhy;\r
  EFI_ASYNC_USB_TRANSFER_CALLBACK   Callback;\r
  VOID                              *Context;\r
  //\r
  // Execute result\r
  //\r
  UINT32                            Result;\r
  //\r
  // completed data length\r
  //\r
  UINTN                             Completed;\r
  //\r
  // Command/Tranfer Ring info\r
  //\r
  TRANSFER_RING                     *Ring;\r
  TRB_TEMPLATE                      *TrbStart;\r
  TRB_TEMPLATE                      *TrbEnd;\r
  UINTN                             TrbNum;\r
  BOOLEAN                           StartDone;\r
  BOOLEAN                           EndDone;\r
  BOOLEAN                           Finished;\r
\r
  TRB_TEMPLATE                      *EvtTrb;\r
} URB;\r
\r
//\r
// 6.5 Event Ring Segment Table\r
// The Event Ring Segment Table is used to define multi-segment Event Rings and to enable runtime\r
// expansion and shrinking of the Event Ring. The location of the Event Ring Segment Table is defined by the\r
// Event Ring Segment Table Base Address Register (5.5.2.3.2). The size of the Event Ring Segment Table\r
// is defined by the Event Ring Segment Table Base Size Register (5.5.2.3.1).\r
//\r
typedef struct _EVENT_RING_SEG_TABLE_ENTRY {\r
  UINT32                    PtrLo;\r
  UINT32                    PtrHi;\r
  UINT32                    RingTrbSize:16;\r
  UINT32                    RsvdZ1:16;\r
  UINT32                    RsvdZ2;\r
} EVENT_RING_SEG_TABLE_ENTRY;\r
\r
//\r
// 6.4.1.1 Normal TRB\r
// A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and\r
// Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer\r
// Rings, and to define the Data stage information for Control Transfer Rings.\r
//\r
typedef struct _TRANSFER_TRB_NORMAL {\r
  UINT32                    TRBPtrLo;\r
\r
  UINT32                    TRBPtrHi;\r
\r
  UINT32                    Length:17;\r
  UINT32                    TDSize:5;\r
  UINT32                    IntTarget:10;\r
\r
  UINT32                    CycleBit:1;\r
  UINT32                    ENT:1;\r
  UINT32                    ISP:1;\r
  UINT32                    NS:1;\r
  UINT32                    CH:1;\r
  UINT32                    IOC:1;\r
  UINT32                    IDT:1;\r
  UINT32                    RsvdZ1:2;\r
  UINT32                    BEI:1;\r
  UINT32                    Type:6;\r
  UINT32                    RsvdZ2:16;\r
} TRANSFER_TRB_NORMAL;\r
\r
//\r
// 6.4.1.2.1 Setup Stage TRB\r
// A Setup Stage TRB is created by system software to initiate a USB Setup packet on a control endpoint.\r
//\r
typedef struct _TRANSFER_TRB_CONTROL_SETUP {\r
  UINT32                    bmRequestType:8;\r
  UINT32                    bRequest:8;\r
  UINT32                    wValue:16;\r
\r
  UINT32                    wIndex:16;\r
  UINT32                    wLength:16;\r
\r
  UINT32                    Length:17;\r
  UINT32                    RsvdZ1:5;\r
  UINT32                    IntTarget:10;\r
\r
  UINT32                    CycleBit:1;\r
  UINT32                    RsvdZ2:4;\r
  UINT32                    IOC:1;\r
  UINT32                    IDT:1;\r
  UINT32                    RsvdZ3:3;\r
  UINT32                    Type:6;\r
  UINT32                    TRT:2;\r
  UINT32                    RsvdZ4:14;\r
} TRANSFER_TRB_CONTROL_SETUP;\r
\r
//\r
// 6.4.1.2.2 Data Stage TRB\r
// A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.\r
//\r
typedef struct _TRANSFER_TRB_CONTROL_DATA {\r
  UINT32                    TRBPtrLo;\r
\r
  UINT32                    TRBPtrHi;\r
\r
  UINT32                    Length:17;\r
  UINT32                    TDSize:5;\r
  UINT32                    IntTarget:10;\r
\r
  UINT32                    CycleBit:1;\r
  UINT32                    ENT:1;\r
  UINT32                    ISP:1;\r
  UINT32                    NS:1;\r
  UINT32                    CH:1;\r
  UINT32                    IOC:1;\r
  UINT32                    IDT:1;\r
  UINT32                    RsvdZ1:3;\r
  UINT32                    Type:6;\r
  UINT32                    DIR:1;\r
  UINT32                    RsvdZ2:15;\r
} TRANSFER_TRB_CONTROL_DATA;\r
\r
//\r
// 6.4.1.2.2 Data Stage TRB\r
// A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.\r
//\r
typedef struct _TRANSFER_TRB_CONTROL_STATUS {\r
  UINT32                    RsvdZ1;\r
  UINT32                    RsvdZ2;\r
\r
  UINT32                    RsvdZ3:22;\r
  UINT32                    IntTarget:10;\r
\r
  UINT32                    CycleBit:1;\r
  UINT32                    ENT:1;\r
  UINT32                    RsvdZ4:2;\r
  UINT32                    CH:1;\r
  UINT32                    IOC:1;\r
  UINT32                    RsvdZ5:4;\r
  UINT32                    Type:6;\r
  UINT32                    DIR:1;\r
  UINT32                    RsvdZ6:15;\r
} TRANSFER_TRB_CONTROL_STATUS;\r
\r
//\r
// 6.4.2.1 Transfer Event TRB\r
// A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1\r
// for more information on the use and operation of Transfer Events.\r
//\r
typedef struct _EVT_TRB_TRANSFER {\r
  UINT32                    TRBPtrLo;\r
\r
  UINT32                    TRBPtrHi;\r
\r
  UINT32                    Length:24;\r
  UINT32                    Completecode:8;\r
\r
  UINT32                    CycleBit:1;\r
  UINT32                    RsvdZ1:1;\r
  UINT32                    ED:1;\r
  UINT32                    RsvdZ2:7;\r
  UINT32                    Type:6;\r
  UINT32                    EndpointId:5;\r
  UINT32                    RsvdZ3:3;\r
  UINT32                    SlotId:8;\r
} EVT_TRB_TRANSFER;\r
\r
//\r
// 6.4.2.2 Command Completion Event TRB\r
// A Command Completion Event TRB shall be generated by the xHC when a command completes on the\r
// Command Ring. Refer to section 4.11.4 for more information on the use of Command Completion Events.\r
//\r
typedef struct _EVT_TRB_COMMAND_COMPLETION {\r
  UINT32                    TRBPtrLo;\r
\r
  UINT32                    TRBPtrHi;\r
\r
  UINT32                    RsvdZ2:24;\r
  UINT32                    Completecode:8;\r
\r
  UINT32                    CycleBit:1;\r
  UINT32                    RsvdZ3:9;\r
  UINT32                    Type:6;\r
  UINT32                    VFID:8;\r
  UINT32                    SlotId:8;\r
} EVT_TRB_COMMAND_COMPLETION;\r
\r
typedef union _TRB {\r
  TRB_TEMPLATE                  TrbTemplate;\r
  TRANSFER_TRB_NORMAL           TrbNormal;\r
  TRANSFER_TRB_CONTROL_SETUP    TrbCtrSetup;\r
  TRANSFER_TRB_CONTROL_DATA     TrbCtrData;\r
  TRANSFER_TRB_CONTROL_STATUS   TrbCtrStatus;\r
} TRB;\r
\r
//\r
// 6.4.3.1 No Op Command TRB\r
// The No Op Command TRB provides a simple means for verifying the operation of the Command Ring\r
// mechanisms offered by the xHCI.\r
//\r
typedef struct _CMD_TRB_NO_OP {\r
  UINT32                    RsvdZ0;\r
  UINT32                    RsvdZ1;\r
  UINT32                    RsvdZ2;\r
\r
  UINT32                    CycleBit:1;\r
  UINT32                    RsvdZ3:9;\r
  UINT32                    Type:6;\r
  UINT32                    RsvdZ4:16;\r
} CMD_TRB_NO_OP;\r
\r
//\r
// 6.4.3.2 Enable Slot Command TRB\r
// The Enable Slot Command TRB causes the xHC to select an available Device Slot and return the ID of the\r
// selected slot to the host in a Command Completion Event.\r
//\r
typedef struct _CMD_TRB_ENABLE_SLOT {\r
  UINT32                    RsvdZ0;\r
  UINT32                    RsvdZ1;\r
  UINT32                    RsvdZ2;\r
\r
  UINT32                    CycleBit:1;\r
  UINT32                    RsvdZ3:9;\r
  UINT32                    Type:6;\r
  UINT32                    RsvdZ4:16;\r
} CMD_TRB_ENABLE_SLOT;\r
\r
//\r
// 6.4.3.3 Disable Slot Command TRB\r
// The Disable Slot Command TRB releases any bandwidth assigned to the disabled slot and frees any\r
// internal xHC resources assigned to the slot.\r
//\r
typedef struct _CMD_TRB_DISABLE_SLOT {\r
  UINT32                    RsvdZ0;\r
  UINT32                    RsvdZ1;\r
  UINT32                    RsvdZ2;\r
\r
  UINT32                    CycleBit:1;\r
  UINT32                    RsvdZ3:9;\r
  UINT32                    Type:6;\r
  UINT32                    RsvdZ4:8;\r
  UINT32                    SlotId:8;\r
} CMD_TRB_DISABLE_SLOT;\r
\r
//\r
// 6.4.3.4 Address Device Command TRB\r
// The Address Device Command TRB transitions the selected Device Context from the Default to the\r
// Addressed state and causes the xHC to select an address for the USB device in the Default State and\r
// issue a SET_ADDRESS request to the USB device.\r
//\r
typedef struct _CMD_TRB_ADDRESS_DEVICE {\r
  UINT32                    PtrLo;\r
\r
  UINT32                    PtrHi;\r
\r
  UINT32                    RsvdZ1;\r
\r
  UINT32                    CycleBit:1;\r
  UINT32                    RsvdZ2:8;\r
  UINT32                    BSR:1;\r
  UINT32                    Type:6;\r
  UINT32                    RsvdZ3:8;\r
  UINT32                    SlotId:8;\r
} CMD_TRB_ADDRESS_DEVICE;\r
\r
//\r
// 6.4.3.5 Configure Endpoint Command TRB\r
// The Configure Endpoint Command TRB evaluates the bandwidth and resource requirements of the\r
// endpoints selected by the command.\r
//\r
typedef struct _CMD_TRB_CONFIG_ENDPOINT {\r
  UINT32                    PtrLo;\r
\r
  UINT32                    PtrHi;\r
\r
  UINT32                    RsvdZ1;\r
\r
  UINT32                    CycleBit:1;\r
  UINT32                    RsvdZ2:8;\r
  UINT32                    DC:1;\r
  UINT32                    Type:6;\r
  UINT32                    RsvdZ3:8;\r
  UINT32                    SlotId:8;\r
} CMD_TRB_CONFIG_ENDPOINT;\r
\r
//\r
// 6.4.3.6 Evaluate Context Command TRB\r
// The Evaluate Context Command TRB is used by system software to inform the xHC that the selected\r
// Context data structures in the Device Context have been modified by system software and that the xHC\r
// shall evaluate any changes\r
//\r
typedef struct _CMD_TRB_EVALUATE_CONTEXT {\r
  UINT32                    PtrLo;\r
\r
  UINT32                    PtrHi;\r
\r
  UINT32                    RsvdZ1;\r
\r
  UINT32                    CycleBit:1;\r
  UINT32                    RsvdZ2:9;\r
  UINT32                    Type:6;\r
  UINT32                    RsvdZ3:8;\r
  UINT32                    SlotId:8;\r
} CMD_TRB_EVALUATE_CONTEXT;\r
\r
//\r
// 6.4.3.7 Reset Endpoint Command TRB\r
// The Reset Endpoint Command TRB is used by system software to reset a specified Transfer Ring\r
//\r
typedef struct _CMD_TRB_RESET_ENDPOINT {\r
  UINT32                    RsvdZ0;\r
  UINT32                    RsvdZ1;\r
  UINT32                    RsvdZ2;\r
\r
  UINT32                    CycleBit:1;\r
  UINT32                    RsvdZ3:8;\r
  UINT32                    TSP:1;\r
  UINT32                    Type:6;\r
  UINT32                    EDID:5;\r
  UINT32                    RsvdZ4:3;\r
  UINT32                    SlotId:8;\r
} CMD_TRB_RESET_ENDPOINT;\r
\r
//\r
// 6.4.3.8 Stop Endpoint Command TRB\r
// The Stop Endpoint Command TRB command allows software to stop the xHC execution of the TDs on a\r
// Transfer Ring and temporarily take ownership of TDs that had previously been passed to the xHC.\r
//\r
typedef struct _CMD_TRB_STOP_ENDPOINT {\r
  UINT32                    RsvdZ0;\r
  UINT32                    RsvdZ1;\r
  UINT32                    RsvdZ2;\r
\r
  UINT32                    CycleBit:1;\r
  UINT32                    RsvdZ3:9;\r
  UINT32                    Type:6;\r
  UINT32                    EDID:5;\r
  UINT32                    RsvdZ4:2;\r
  UINT32                    SP:1;\r
  UINT32                    SlotId:8;\r
} CMD_TRB_STOP_ENDPOINT;\r
\r
//\r
// 6.4.3.9 Set TR Dequeue Pointer Command TRB\r
// The Set TR Dequeue Pointer Command TRB is used by system software to modify the TR Dequeue\r
// Pointer and DCS fields of an Endpoint or Stream Context.\r
//\r
typedef struct _CMD_SET_TR_DEQ_POINTER {\r
  UINT32                    PtrLo;\r
\r
  UINT32                    PtrHi;\r
\r
  UINT32                    RsvdZ1:16;\r
  UINT32                    StreamID:16;\r
\r
  UINT32                    CycleBit:1;\r
  UINT32                    RsvdZ2:9;\r
  UINT32                    Type:6;\r
  UINT32                    Endpoint:5;\r
  UINT32                    RsvdZ3:3;\r
  UINT32                    SlotId:8;\r
} CMD_SET_TR_DEQ_POINTER;\r
\r
//\r
// 6.4.4.1 Link TRB\r
// A Link TRB provides support for non-contiguous TRB Rings.\r
//\r
typedef struct _LINK_TRB {\r
  UINT32                    PtrLo;\r
\r
  UINT32                    PtrHi;\r
\r
  UINT32                    RsvdZ1:22;\r
  UINT32                    InterTarget:10;\r
\r
  UINT32                    CycleBit:1;\r
  UINT32                    TC:1;\r
  UINT32                    RsvdZ2:2;\r
  UINT32                    CH:1;\r
  UINT32                    IOC:1;\r
  UINT32                    RsvdZ3:4;\r
  UINT32                    Type:6;\r
  UINT32                    RsvdZ4:16;\r
} LINK_TRB;\r
\r
//\r
// 6.2.2 Slot Context\r
//\r
typedef struct _SLOT_CONTEXT {\r
  UINT32                    RouteString:20;\r
  UINT32                    Speed:4;\r
  UINT32                    RsvdZ1:1;\r
  UINT32                    MTT:1;\r
  UINT32                    Hub:1;\r
  UINT32                    ContextEntries:5;\r
\r
  UINT32                    MaxExitLatency:16;\r
  UINT32                    RootHubPortNum:8;\r
  UINT32                    PortNum:8;\r
\r
  UINT32                    TTHubSlotId:8;\r
  UINT32                    TTPortNum:8;\r
  UINT32                    TTT:2;\r
  UINT32                    RsvdZ2:4;\r
  UINT32                    InterTarget:10;\r
\r
  UINT32                    DeviceAddress:8;\r
  UINT32                    RsvdZ3:19;\r
  UINT32                    SlotState:5;\r
\r
  UINT32                    RsvdZ4;\r
  UINT32                    RsvdZ5;\r
  UINT32                    RsvdZ6;\r
  UINT32                    RsvdZ7;\r
} SLOT_CONTEXT;\r
\r
typedef struct _SLOT_CONTEXT_64 {\r
  UINT32                    RouteString:20;\r
  UINT32                    Speed:4;\r
  UINT32                    RsvdZ1:1;\r
  UINT32                    MTT:1;\r
  UINT32                    Hub:1;\r
  UINT32                    ContextEntries:5;\r
\r
  UINT32                    MaxExitLatency:16;\r
  UINT32                    RootHubPortNum:8;\r
  UINT32                    PortNum:8;\r
\r
  UINT32                    TTHubSlotId:8;\r
  UINT32                    TTPortNum:8;\r
  UINT32                    TTT:2;\r
  UINT32                    RsvdZ2:4;\r
  UINT32                    InterTarget:10;\r
\r
  UINT32                    DeviceAddress:8;\r
  UINT32                    RsvdZ3:19;\r
  UINT32                    SlotState:5;\r
\r
  UINT32                    RsvdZ4;\r
  UINT32                    RsvdZ5;\r
  UINT32                    RsvdZ6;\r
  UINT32                    RsvdZ7;\r
\r
  UINT32                    RsvdZ8;\r
  UINT32                    RsvdZ9;\r
  UINT32                    RsvdZ10;\r
  UINT32                    RsvdZ11;\r
\r
  UINT32                    RsvdZ12;\r
  UINT32                    RsvdZ13;\r
  UINT32                    RsvdZ14;\r
  UINT32                    RsvdZ15;\r
\r
} SLOT_CONTEXT_64;\r
\r
\r
//\r
// 6.2.3 Endpoint Context\r
//\r
typedef struct _ENDPOINT_CONTEXT {\r
  UINT32                    EPState:3;\r
  UINT32                    RsvdZ1:5;\r
  UINT32                    Mult:2;\r
  UINT32                    MaxPStreams:5;\r
  UINT32                    LSA:1;\r
  UINT32                    Interval:8;\r
  UINT32                    RsvdZ2:8;\r
\r
  UINT32                    RsvdZ3:1;\r
  UINT32                    CErr:2;\r
  UINT32                    EPType:3;\r
  UINT32                    RsvdZ4:1;\r
  UINT32                    HID:1;\r
  UINT32                    MaxBurstSize:8;\r
  UINT32                    MaxPacketSize:16;\r
\r
  UINT32                    PtrLo;\r
\r
  UINT32                    PtrHi;\r
\r
  UINT32                    AverageTRBLength:16;\r
  UINT32                    MaxESITPayload:16;\r
\r
  UINT32                    RsvdZ5;\r
  UINT32                    RsvdZ6;\r
  UINT32                    RsvdZ7;\r
} ENDPOINT_CONTEXT;\r
\r
typedef struct _ENDPOINT_CONTEXT_64 {\r
  UINT32                    EPState:3;\r
  UINT32                    RsvdZ1:5;\r
  UINT32                    Mult:2;\r
  UINT32                    MaxPStreams:5;\r
  UINT32                    LSA:1;\r
  UINT32                    Interval:8;\r
  UINT32                    RsvdZ2:8;\r
\r
  UINT32                    RsvdZ3:1;\r
  UINT32                    CErr:2;\r
  UINT32                    EPType:3;\r
  UINT32                    RsvdZ4:1;\r
  UINT32                    HID:1;\r
  UINT32                    MaxBurstSize:8;\r
  UINT32                    MaxPacketSize:16;\r
\r
  UINT32                    PtrLo;\r
\r
  UINT32                    PtrHi;\r
\r
  UINT32                    AverageTRBLength:16;\r
  UINT32                    MaxESITPayload:16;\r
\r
  UINT32                    RsvdZ5;\r
  UINT32                    RsvdZ6;\r
  UINT32                    RsvdZ7;\r
\r
  UINT32                    RsvdZ8;\r
  UINT32                    RsvdZ9;\r
  UINT32                    RsvdZ10;\r
  UINT32                    RsvdZ11;\r
\r
  UINT32                    RsvdZ12;\r
  UINT32                    RsvdZ13;\r
  UINT32                    RsvdZ14;\r
  UINT32                    RsvdZ15;\r
\r
} ENDPOINT_CONTEXT_64;\r
\r
\r
//\r
// 6.2.5.1 Input Control Context\r
//\r
typedef struct _INPUT_CONTRL_CONTEXT {\r
  UINT32                    Dword1;\r
  UINT32                    Dword2;\r
  UINT32                    RsvdZ1;\r
  UINT32                    RsvdZ2;\r
  UINT32                    RsvdZ3;\r
  UINT32                    RsvdZ4;\r
  UINT32                    RsvdZ5;\r
  UINT32                    RsvdZ6;\r
} INPUT_CONTRL_CONTEXT;\r
\r
typedef struct _INPUT_CONTRL_CONTEXT_64 {\r
  UINT32                    Dword1;\r
  UINT32                    Dword2;\r
  UINT32                    RsvdZ1;\r
  UINT32                    RsvdZ2;\r
  UINT32                    RsvdZ3;\r
  UINT32                    RsvdZ4;\r
  UINT32                    RsvdZ5;\r
  UINT32                    RsvdZ6;\r
  UINT32                    RsvdZ7;\r
  UINT32                    RsvdZ8;\r
  UINT32                    RsvdZ9;\r
  UINT32                    RsvdZ10;\r
  UINT32                    RsvdZ11;\r
  UINT32                    RsvdZ12;\r
  UINT32                    RsvdZ13;\r
  UINT32                    RsvdZ14;\r
} INPUT_CONTRL_CONTEXT_64;\r
\r
//\r
// 6.2.1 Device Context\r
//\r
typedef struct _DEVICE_CONTEXT {\r
  SLOT_CONTEXT              Slot;\r
  ENDPOINT_CONTEXT          EP[31];\r
} DEVICE_CONTEXT;\r
\r
typedef struct _DEVICE_CONTEXT_64 {\r
  SLOT_CONTEXT_64           Slot;\r
  ENDPOINT_CONTEXT_64       EP[31];\r
} DEVICE_CONTEXT_64;\r
\r
//\r
// 6.2.5 Input Context\r
//\r
typedef struct _INPUT_CONTEXT {\r
  INPUT_CONTRL_CONTEXT      InputControlContext;\r
  SLOT_CONTEXT              Slot;\r
  ENDPOINT_CONTEXT          EP[31];\r
} INPUT_CONTEXT;\r
\r
typedef struct _INPUT_CONTEXT_64 {\r
  INPUT_CONTRL_CONTEXT_64   InputControlContext;\r
  SLOT_CONTEXT_64           Slot;\r
  ENDPOINT_CONTEXT_64       EP[31];\r
} INPUT_CONTEXT_64;\r
\r
/**\r
  Execute the transfer by polling the URB. This is a synchronous operation.\r
\r
  @param  Xhc               The XHCI device.\r
  @param  CmdTransfer       The executed URB is for cmd transfer or not.\r
  @param  Urb               The URB to execute.\r
  @param  Timeout           The time to wait before abort, in millisecond.\r
\r
  @return EFI_DEVICE_ERROR  The transfer failed due to transfer error.\r
  @return EFI_TIMEOUT       The transfer failed due to time out.\r
  @return EFI_SUCCESS       The transfer finished OK.\r
\r
**/\r
EFI_STATUS\r
XhcPeiExecTransfer (\r
  IN PEI_XHC_DEV            *Xhc,\r
  IN BOOLEAN                CmdTransfer,\r
  IN URB                    *Urb,\r
  IN UINTN                  Timeout\r
  );\r
\r
/**\r
  Find out the actual device address according to the requested device address from UsbBus.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  BusDevAddr    The requested device address by UsbBus upper driver.\r
\r
  @return The actual device address assigned to the device.\r
\r
**/\r
UINT8\r
XhcPeiBusDevAddrToSlotId (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT8              BusDevAddr\r
  );\r
\r
/**\r
  Find out the slot id according to the device's route string.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  RouteString   The route string described the device location.\r
\r
  @return The slot id used by the device.\r
\r
**/\r
UINT8\r
XhcPeiRouteStringToSlotId (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN USB_DEV_ROUTE      RouteString\r
  );\r
\r
/**\r
  Calculate the device context index by endpoint address and direction.\r
\r
  @param  EpAddr        The target endpoint number.\r
  @param  Direction     The direction of the target endpoint.\r
\r
  @return The device context index of endpoint.\r
\r
**/\r
UINT8\r
XhcPeiEndpointToDci (\r
  IN UINT8                      EpAddr,\r
  IN EFI_USB_DATA_DIRECTION     Direction\r
  );\r
\r
/**\r
  Ring the door bell to notify XHCI there is a transaction to be executed.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  SlotId        The slot id of the target device.\r
  @param  Dci           The device context index of the target slot or endpoint.\r
\r
**/\r
VOID\r
XhcPeiRingDoorBell (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT8              SlotId,\r
  IN UINT8              Dci\r
  );\r
\r
/**\r
  Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.\r
\r
  @param  Xhc               The XHCI device.\r
  @param  ParentRouteChart  The route string pointed to the parent device if it exists.\r
  @param  Port              The port to be polled.\r
  @param  PortState         The port state.\r
\r
  @retval EFI_SUCCESS       Successfully enable/disable device slot according to port state.\r
  @retval Others            Should not appear.\r
\r
**/\r
EFI_STATUS\r
XhcPeiPollPortStatusChange (\r
  IN PEI_XHC_DEV            *Xhc,\r
  IN USB_DEV_ROUTE          ParentRouteChart,\r
  IN UINT8                  Port,\r
  IN EFI_USB_PORT_STATUS    *PortState\r
  );\r
\r
/**\r
  Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  SlotId        The slot id to be configured.\r
  @param  PortNum       The total number of downstream port supported by the hub.\r
  @param  TTT           The TT think time of the hub device.\r
  @param  MTT           The multi-TT of the hub device.\r
\r
  @retval EFI_SUCCESS   Successfully configure the hub device's slot context.\r
\r
**/\r
EFI_STATUS\r
XhcPeiConfigHubContext (\r
  IN PEI_XHC_DEV                *Xhc,\r
  IN UINT8                      SlotId,\r
  IN UINT8                      PortNum,\r
  IN UINT8                      TTT,\r
  IN UINT8                      MTT\r
  );\r
\r
/**\r
  Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  SlotId        The slot id to be configured.\r
  @param  PortNum       The total number of downstream port supported by the hub.\r
  @param  TTT           The TT think time of the hub device.\r
  @param  MTT           The multi-TT of the hub device.\r
\r
  @retval EFI_SUCCESS   Successfully configure the hub device's slot context.\r
\r
**/\r
EFI_STATUS\r
XhcPeiConfigHubContext64 (\r
  IN PEI_XHC_DEV                *Xhc,\r
  IN UINT8                      SlotId,\r
  IN UINT8                      PortNum,\r
  IN UINT8                      TTT,\r
  IN UINT8                      MTT\r
  );\r
\r
/**\r
  Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  SlotId        The slot id to be configured.\r
  @param  DeviceSpeed   The device's speed.\r
  @param  ConfigDesc    The pointer to the usb device configuration descriptor.\r
\r
  @retval EFI_SUCCESS   Successfully configure all the device endpoints.\r
\r
**/\r
EFI_STATUS\r
XhcPeiSetConfigCmd (\r
  IN PEI_XHC_DEV                *Xhc,\r
  IN UINT8                      SlotId,\r
  IN UINT8                      DeviceSpeed,\r
  IN USB_CONFIG_DESCRIPTOR      *ConfigDesc\r
  );\r
\r
/**\r
  Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  SlotId        The slot id to be configured.\r
  @param  DeviceSpeed   The device's speed.\r
  @param  ConfigDesc    The pointer to the usb device configuration descriptor.\r
\r
  @retval EFI_SUCCESS   Successfully configure all the device endpoints.\r
\r
**/\r
EFI_STATUS\r
XhcPeiSetConfigCmd64 (\r
  IN PEI_XHC_DEV                *Xhc,\r
  IN UINT8                      SlotId,\r
  IN UINT8                      DeviceSpeed,\r
  IN USB_CONFIG_DESCRIPTOR      *ConfigDesc\r
  );\r
\r
/**\r
  Stop endpoint through XHCI's Stop_Endpoint cmd.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  SlotId        The slot id of the target device.\r
  @param  Dci           The device context index of the target slot or endpoint.\r
\r
  @retval EFI_SUCCESS   Stop endpoint successfully.\r
  @retval Others        Failed to stop endpoint.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
XhcPeiStopEndpoint (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT8              SlotId,\r
  IN UINT8              Dci\r
  );\r
\r
/**\r
  Reset endpoint through XHCI's Reset_Endpoint cmd.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  SlotId        The slot id of the target device.\r
  @param  Dci           The device context index of the target slot or endpoint.\r
\r
  @retval EFI_SUCCESS   Reset endpoint successfully.\r
  @retval Others        Failed to reset endpoint.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
XhcPeiResetEndpoint (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT8              SlotId,\r
  IN UINT8              Dci\r
  );\r
\r
/**\r
  Set transfer ring dequeue pointer through XHCI's Set_Tr_Dequeue_Pointer cmd.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  SlotId        The slot id of the target device.\r
  @param  Dci           The device context index of the target slot or endpoint.\r
  @param  Urb           The dequeue pointer of the transfer ring specified\r
                        by the urb to be updated.\r
\r
  @retval EFI_SUCCESS   Set transfer ring dequeue pointer succeeds.\r
  @retval Others        Failed to set transfer ring dequeue pointer.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
XhcPeiSetTrDequeuePointer (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN UINT8              SlotId,\r
  IN UINT8              Dci,\r
  IN URB                *Urb\r
  );\r
\r
/**\r
  Assign and initialize the device slot for a new device.\r
\r
  @param  Xhc                   The XHCI device.\r
  @param  ParentRouteChart      The route string pointed to the parent device.\r
  @param  ParentPort            The port at which the device is located.\r
  @param  RouteChart            The route string pointed to the device.\r
  @param  DeviceSpeed           The device speed.\r
\r
  @retval EFI_SUCCESS           Successfully assign a slot to the device and assign an address to it.\r
  @retval Others                Fail to initialize device slot.\r
\r
**/\r
EFI_STATUS\r
XhcPeiInitializeDeviceSlot (\r
  IN PEI_XHC_DEV                *Xhc,\r
  IN USB_DEV_ROUTE              ParentRouteChart,\r
  IN UINT16                     ParentPort,\r
  IN USB_DEV_ROUTE              RouteChart,\r
  IN UINT8                      DeviceSpeed\r
  );\r
\r
/**\r
  Assign and initialize the device slot for a new device.\r
\r
  @param  Xhc                   The XHCI device.\r
  @param  ParentRouteChart      The route string pointed to the parent device.\r
  @param  ParentPort            The port at which the device is located.\r
  @param  RouteChart            The route string pointed to the device.\r
  @param  DeviceSpeed           The device speed.\r
\r
  @retval EFI_SUCCESS           Successfully assign a slot to the device and assign an address to it.\r
  @retval Others                Fail to initialize device slot.\r
\r
**/\r
EFI_STATUS\r
XhcPeiInitializeDeviceSlot64 (\r
  IN PEI_XHC_DEV                *Xhc,\r
  IN USB_DEV_ROUTE              ParentRouteChart,\r
  IN UINT16                     ParentPort,\r
  IN USB_DEV_ROUTE              RouteChart,\r
  IN UINT8                      DeviceSpeed\r
  );\r
\r
/**\r
  Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  SlotId        The slot id to be evaluated.\r
  @param  MaxPacketSize The max packet size supported by the device control transfer.\r
\r
  @retval EFI_SUCCESS   Successfully evaluate the device endpoint 0.\r
\r
**/\r
EFI_STATUS\r
XhcPeiEvaluateContext (\r
  IN PEI_XHC_DEV                *Xhc,\r
  IN UINT8                      SlotId,\r
  IN UINT32                     MaxPacketSize\r
  );\r
\r
/**\r
  Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  SlotId        The slot id to be evaluated.\r
  @param  MaxPacketSize The max packet size supported by the device control transfer.\r
\r
  @retval EFI_SUCCESS   Successfully evaluate the device endpoint 0.\r
\r
**/\r
EFI_STATUS\r
XhcPeiEvaluateContext64 (\r
  IN PEI_XHC_DEV                *Xhc,\r
  IN UINT8                      SlotId,\r
  IN UINT32                     MaxPacketSize\r
  );\r
\r
/**\r
  Disable the specified device slot.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  SlotId        The slot id to be disabled.\r
\r
  @retval EFI_SUCCESS   Successfully disable the device slot.\r
\r
**/\r
EFI_STATUS\r
XhcPeiDisableSlotCmd (\r
  IN PEI_XHC_DEV              *Xhc,\r
  IN UINT8                    SlotId\r
  );\r
\r
/**\r
  Disable the specified device slot.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  SlotId        The slot id to be disabled.\r
\r
  @retval EFI_SUCCESS   Successfully disable the device slot.\r
\r
**/\r
EFI_STATUS\r
XhcPeiDisableSlotCmd64 (\r
  IN PEI_XHC_DEV              *Xhc,\r
  IN UINT8                    SlotId\r
  );\r
\r
/**\r
  System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted\r
  condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint\r
  Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is\r
  reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the\r
  Stopped to the Running state.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  Urb           The urb which makes the endpoint halted.\r
\r
  @retval EFI_SUCCESS   The recovery is successful.\r
  @retval Others        Failed to recovery halted endpoint.\r
\r
**/\r
EFI_STATUS\r
XhcPeiRecoverHaltedEndpoint (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN URB                *Urb\r
  );\r
\r
/**\r
  System software shall use a Stop Endpoint Command (section 4.6.9) and the Set TR Dequeue Pointer\r
  Command (section 4.6.10) to remove the timed-out TDs from the xHC transfer ring. The next write to\r
  the Doorbell of the Endpoint will transition the Endpoint Context from the Stopped to the Running\r
  state.\r
\r
  @param  Xhc                   The XHCI device.\r
  @param  Urb                   The urb which doesn't get completed in a specified timeout range.\r
\r
  @retval EFI_SUCCESS           The dequeuing of the TDs is successful.\r
  @retval Others                Failed to stop the endpoint and dequeue the TDs.\r
\r
**/\r
EFI_STATUS\r
XhcPeiDequeueTrbFromEndpoint (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN URB                *Urb\r
  );\r
\r
/**\r
  Create a new URB for a new transaction.\r
\r
  @param  Xhc       The XHCI device\r
  @param  DevAddr   The device address\r
  @param  EpAddr    Endpoint addrress\r
  @param  DevSpeed  The device speed\r
  @param  MaxPacket The max packet length of the endpoint\r
  @param  Type      The transaction type\r
  @param  Request   The standard USB request for control transfer\r
  @param  Data      The user data to transfer\r
  @param  DataLen   The length of data buffer\r
  @param  Callback  The function to call when data is transferred\r
  @param  Context   The context to the callback\r
\r
  @return Created URB or NULL\r
\r
**/\r
URB*\r
XhcPeiCreateUrb (\r
  IN PEI_XHC_DEV                        *Xhc,\r
  IN UINT8                              DevAddr,\r
  IN UINT8                              EpAddr,\r
  IN UINT8                              DevSpeed,\r
  IN UINTN                              MaxPacket,\r
  IN UINTN                              Type,\r
  IN EFI_USB_DEVICE_REQUEST             *Request,\r
  IN VOID                               *Data,\r
  IN UINTN                              DataLen,\r
  IN EFI_ASYNC_USB_TRANSFER_CALLBACK    Callback,\r
  IN VOID                               *Context\r
  );\r
\r
/**\r
  Free an allocated URB.\r
\r
  @param  Xhc       The XHCI device.\r
  @param  Urb       The URB to free.\r
\r
**/\r
VOID\r
XhcPeiFreeUrb (\r
  IN PEI_XHC_DEV    *Xhc,\r
  IN URB            *Urb\r
  );\r
\r
/**\r
  Create a transfer TRB.\r
\r
  @param  Xhc       The XHCI device\r
  @param  Urb       The urb used to construct the transfer TRB.\r
\r
  @return Created TRB or NULL\r
\r
**/\r
EFI_STATUS\r
XhcPeiCreateTransferTrb (\r
  IN PEI_XHC_DEV    *Xhc,\r
  IN URB            *Urb\r
  );\r
\r
/**\r
  Synchronize the specified transfer ring to update the enqueue and dequeue pointer.\r
\r
  @param  Xhc       The XHCI device.\r
  @param  TrsRing   The transfer ring to sync.\r
\r
  @retval EFI_SUCCESS The transfer ring is synchronized successfully.\r
\r
**/\r
EFI_STATUS\r
XhcPeiSyncTrsRing (\r
  IN PEI_XHC_DEV    *Xhc,\r
  IN TRANSFER_RING  *TrsRing\r
  );\r
\r
/**\r
  Create XHCI transfer ring.\r
\r
  @param  Xhc               The XHCI Device.\r
  @param  TrbNum            The number of TRB in the ring.\r
  @param  TransferRing      The created transfer ring.\r
\r
**/\r
VOID\r
XhcPeiCreateTransferRing (\r
  IN PEI_XHC_DEV            *Xhc,\r
  IN UINTN                  TrbNum,\r
  OUT TRANSFER_RING         *TransferRing\r
  );\r
\r
/**\r
  Check if there is a new generated event.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  EvtRing       The event ring to check.\r
  @param  NewEvtTrb     The new event TRB found.\r
\r
  @retval EFI_SUCCESS   Found a new event TRB at the event ring.\r
  @retval EFI_NOT_READY The event ring has no new event.\r
\r
**/\r
EFI_STATUS\r
XhcPeiCheckNewEvent (\r
  IN PEI_XHC_DEV        *Xhc,\r
  IN EVENT_RING         *EvtRing,\r
  OUT TRB_TEMPLATE      **NewEvtTrb\r
  );\r
\r
/**\r
  Synchronize the specified event ring to update the enqueue and dequeue pointer.\r
\r
  @param  Xhc       The XHCI device.\r
  @param  EvtRing   The event ring to sync.\r
\r
  @retval EFI_SUCCESS The event ring is synchronized successfully.\r
\r
**/\r
EFI_STATUS\r
XhcPeiSyncEventRing (\r
  IN PEI_XHC_DEV    *Xhc,\r
  IN EVENT_RING     *EvtRing\r
  );\r
\r
/**\r
  Create XHCI event ring.\r
\r
  @param  Xhc           The XHCI device.\r
  @param  EventRing     The created event ring.\r
\r
**/\r
VOID\r
XhcPeiCreateEventRing (\r
  IN PEI_XHC_DEV        *Xhc,\r
  OUT EVENT_RING        *EventRing\r
  );\r
\r
/**\r
  Initialize the XHCI host controller for schedule.\r
\r
  @param  Xhc       The XHCI device to be initialized.\r
\r
**/\r
VOID\r
XhcPeiInitSched (\r
  IN PEI_XHC_DEV        *Xhc\r
  );\r
\r
/**\r
  Free the resouce allocated at initializing schedule.\r
\r
  @param  Xhc       The XHCI device.\r
\r
**/\r
VOID\r
XhcPeiFreeSched (\r
  IN PEI_XHC_DEV    *Xhc\r
  );\r
\r
#endif\r