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d987459f
SZ		 1/** @file\r
2Private Header file for Usb Host Controller PEIM\r
3\r
12e6c738 4Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r
d987459f 5\r
9d510e61 6SPDX-License-Identifier: BSD-2-Clause-Patent\r
d987459f
SZ		 7\r
8**/\r
9\r
10#ifndef _EFI_PEI_XHCI_SCHED_H_\r
11#define _EFI_PEI_XHCI_SCHED_H_\r
12\r
13//\r
14// Transfer types, used in URB to identify the transfer type\r
15//\r
16#define XHC_CTRL_TRANSFER 0x01\r
17#define XHC_BULK_TRANSFER 0x02\r
18\r
19//\r
20// 6.4.6 TRB Types\r
21//\r
22#define TRB_TYPE_NORMAL 1\r
23#define TRB_TYPE_SETUP_STAGE 2\r
24#define TRB_TYPE_DATA_STAGE 3\r
25#define TRB_TYPE_STATUS_STAGE 4\r
26#define TRB_TYPE_ISOCH 5\r
27#define TRB_TYPE_LINK 6\r
28#define TRB_TYPE_EVENT_DATA 7\r
29#define TRB_TYPE_NO_OP 8\r
30#define TRB_TYPE_EN_SLOT 9\r
31#define TRB_TYPE_DIS_SLOT 10\r
32#define TRB_TYPE_ADDRESS_DEV 11\r
33#define TRB_TYPE_CON_ENDPOINT 12\r
34#define TRB_TYPE_EVALU_CONTXT 13\r
35#define TRB_TYPE_RESET_ENDPOINT 14\r
36#define TRB_TYPE_STOP_ENDPOINT 15\r
37#define TRB_TYPE_SET_TR_DEQUE 16\r
38#define TRB_TYPE_RESET_DEV 17\r
39#define TRB_TYPE_GET_PORT_BANW 21\r
40#define TRB_TYPE_FORCE_HEADER 22\r
41#define TRB_TYPE_NO_OP_COMMAND 23\r
42#define TRB_TYPE_TRANS_EVENT 32\r
43#define TRB_TYPE_COMMAND_COMPLT_EVENT 33\r
44#define TRB_TYPE_PORT_STATUS_CHANGE_EVENT 34\r
45#define TRB_TYPE_HOST_CONTROLLER_EVENT 37\r
46#define TRB_TYPE_DEVICE_NOTIFI_EVENT 38\r
47#define TRB_TYPE_MFINDEX_WRAP_EVENT 39\r
48\r
49//\r
50// Endpoint Type (EP Type).\r
51//\r
52#define ED_NOT_VALID 0\r
53#define ED_ISOCH_OUT 1\r
54#define ED_BULK_OUT 2\r
55#define ED_INTERRUPT_OUT 3\r
56#define ED_CONTROL_BIDIR 4\r
57#define ED_ISOCH_IN 5\r
58#define ED_BULK_IN 6\r
59#define ED_INTERRUPT_IN 7\r
60\r
61//\r
62// 6.4.5 TRB Completion Codes\r
63//\r
64#define TRB_COMPLETION_INVALID 0\r
65#define TRB_COMPLETION_SUCCESS 1\r
66#define TRB_COMPLETION_DATA_BUFFER_ERROR 2\r
67#define TRB_COMPLETION_BABBLE_ERROR 3\r
68#define TRB_COMPLETION_USB_TRANSACTION_ERROR 4\r
69#define TRB_COMPLETION_TRB_ERROR 5\r
70#define TRB_COMPLETION_STALL_ERROR 6\r
71#define TRB_COMPLETION_SHORT_PACKET 13\r
72\r
73//\r
74// The topology string used to present usb device location\r
75//\r
76typedef struct _USB_DEV_TOPOLOGY {\r
77 //\r
78 // The tier concatenation of down stream port.\r
79 //\r
80 UINT32 RouteString:20;\r
81 //\r
82 // The root port number of the chain.\r
83 //\r
84 UINT32 RootPortNum:8;\r
85 //\r
86 // The Tier the device reside.\r
87 //\r
88 UINT32 TierNum:4;\r
89} USB_DEV_TOPOLOGY;\r
90\r
91//\r
92// USB Device's RouteChart\r
93//\r
94typedef union _USB_DEV_ROUTE {\r
95 UINT32 Dword;\r
96 USB_DEV_TOPOLOGY Route;\r
97} USB_DEV_ROUTE;\r
98\r
99//\r
100// Endpoint address and its capabilities\r
101//\r
102typedef struct _USB_ENDPOINT {\r
103 //\r
104 // Store logical device address assigned by UsbBus\r
105 // It's because some XHCI host controllers may assign the same physcial device\r
106 // address for those devices inserted at different root port.\r
107 //\r
108 UINT8 BusAddr;\r
109 UINT8 DevAddr;\r
110 UINT8 EpAddr;\r
111 EFI_USB_DATA_DIRECTION Direction;\r
112 UINT8 DevSpeed;\r
113 UINTN MaxPacket;\r
114 UINTN Type;\r
115} USB_ENDPOINT;\r
116\r
117//\r
118// TRB Template\r
119//\r
120typedef struct _TRB_TEMPLATE {\r
121 UINT32 Parameter1;\r
122\r
123 UINT32 Parameter2;\r
124\r
125 UINT32 Status;\r
126\r
127 UINT32 CycleBit:1;\r
128 UINT32 RsvdZ1:9;\r
129 UINT32 Type:6;\r
130 UINT32 Control:16;\r
131} TRB_TEMPLATE;\r
132\r
133typedef struct _TRANSFER_RING {\r
134 VOID *RingSeg0;\r
135 UINTN TrbNumber;\r
136 TRB_TEMPLATE *RingEnqueue;\r
137 TRB_TEMPLATE *RingDequeue;\r
138 UINT32 RingPCS;\r
139} TRANSFER_RING;\r
140\r
141typedef struct _EVENT_RING {\r
142 VOID *ERSTBase;\r
143 VOID *EventRingSeg0;\r
144 UINTN TrbNumber;\r
145 TRB_TEMPLATE *EventRingEnqueue;\r
146 TRB_TEMPLATE *EventRingDequeue;\r
147 UINT32 EventRingCCS;\r
148} EVENT_RING;\r
149\r
150#define XHC_URB_SIG SIGNATURE_32 ('U', 'S', 'B', 'R')\r
151\r
152//\r
153// URB (Usb Request Block) contains information for all kinds of\r
154// usb requests.\r
155//\r
156typedef struct _URB {\r
157 UINT32 Signature;\r
158 //\r
159 // Usb Device URB related information\r
160 //\r
161 USB_ENDPOINT Ep;\r
162 EFI_USB_DEVICE_REQUEST *Request;\r
163 VOID *Data;\r
164 UINTN DataLen;\r
165 VOID *DataPhy;\r
b575ca32 166 VOID *DataMap;\r
d987459f
SZ		 167 EFI_ASYNC_USB_TRANSFER_CALLBACK Callback;\r
168 VOID *Context;\r
169 //\r
170 // Execute result\r
171 //\r
172 UINT32 Result;\r
173 //\r
174 // completed data length\r
175 //\r
176 UINTN Completed;\r
177 //\r
178 // Command/Tranfer Ring info\r
179 //\r
180 TRANSFER_RING *Ring;\r
181 TRB_TEMPLATE *TrbStart;\r
182 TRB_TEMPLATE *TrbEnd;\r
183 UINTN TrbNum;\r
184 BOOLEAN StartDone;\r
185 BOOLEAN EndDone;\r
186 BOOLEAN Finished;\r
187\r
188 TRB_TEMPLATE *EvtTrb;\r
189} URB;\r
190\r
191//\r
192// 6.5 Event Ring Segment Table\r
193// The Event Ring Segment Table is used to define multi-segment Event Rings and to enable runtime\r
194// expansion and shrinking of the Event Ring. The location of the Event Ring Segment Table is defined by the\r
195// Event Ring Segment Table Base Address Register (5.5.2.3.2). The size of the Event Ring Segment Table\r
196// is defined by the Event Ring Segment Table Base Size Register (5.5.2.3.1).\r
197//\r
198typedef struct _EVENT_RING_SEG_TABLE_ENTRY {\r
199 UINT32 PtrLo;\r
200 UINT32 PtrHi;\r
201 UINT32 RingTrbSize:16;\r
202 UINT32 RsvdZ1:16;\r
203 UINT32 RsvdZ2;\r
204} EVENT_RING_SEG_TABLE_ENTRY;\r
205\r
206//\r
207// 6.4.1.1 Normal TRB\r
208// A Normal TRB is used in several ways; exclusively on Bulk and Interrupt Transfer Rings for normal and\r
209// Scatter/Gather operations, to define additional data buffers for Scatter/Gather operations on Isoch Transfer\r
210// Rings, and to define the Data stage information for Control Transfer Rings.\r
211//\r
212typedef struct _TRANSFER_TRB_NORMAL {\r
213 UINT32 TRBPtrLo;\r
214\r
215 UINT32 TRBPtrHi;\r
216\r
217 UINT32 Length:17;\r
218 UINT32 TDSize:5;\r
219 UINT32 IntTarget:10;\r
220\r
221 UINT32 CycleBit:1;\r
222 UINT32 ENT:1;\r
223 UINT32 ISP:1;\r
224 UINT32 NS:1;\r
225 UINT32 CH:1;\r
226 UINT32 IOC:1;\r
227 UINT32 IDT:1;\r
228 UINT32 RsvdZ1:2;\r
229 UINT32 BEI:1;\r
230 UINT32 Type:6;\r
231 UINT32 RsvdZ2:16;\r
232} TRANSFER_TRB_NORMAL;\r
233\r
234//\r
235// 6.4.1.2.1 Setup Stage TRB\r
236// A Setup Stage TRB is created by system software to initiate a USB Setup packet on a control endpoint.\r
237//\r
238typedef struct _TRANSFER_TRB_CONTROL_SETUP {\r
239 UINT32 bmRequestType:8;\r
240 UINT32 bRequest:8;\r
241 UINT32 wValue:16;\r
242\r
243 UINT32 wIndex:16;\r
244 UINT32 wLength:16;\r
245\r
246 UINT32 Length:17;\r
247 UINT32 RsvdZ1:5;\r
248 UINT32 IntTarget:10;\r
249\r
250 UINT32 CycleBit:1;\r
251 UINT32 RsvdZ2:4;\r
252 UINT32 IOC:1;\r
253 UINT32 IDT:1;\r
254 UINT32 RsvdZ3:3;\r
255 UINT32 Type:6;\r
256 UINT32 TRT:2;\r
257 UINT32 RsvdZ4:14;\r
258} TRANSFER_TRB_CONTROL_SETUP;\r
259\r
260//\r
261// 6.4.1.2.2 Data Stage TRB\r
262// A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.\r
263//\r
264typedef struct _TRANSFER_TRB_CONTROL_DATA {\r
265 UINT32 TRBPtrLo;\r
266\r
267 UINT32 TRBPtrHi;\r
268\r
269 UINT32 Length:17;\r
270 UINT32 TDSize:5;\r
271 UINT32 IntTarget:10;\r
272\r
273 UINT32 CycleBit:1;\r
274 UINT32 ENT:1;\r
275 UINT32 ISP:1;\r
276 UINT32 NS:1;\r
277 UINT32 CH:1;\r
278 UINT32 IOC:1;\r
279 UINT32 IDT:1;\r
280 UINT32 RsvdZ1:3;\r
281 UINT32 Type:6;\r
282 UINT32 DIR:1;\r
283 UINT32 RsvdZ2:15;\r
284} TRANSFER_TRB_CONTROL_DATA;\r
285\r
286//\r
287// 6.4.1.2.2 Data Stage TRB\r
288// A Data Stage TRB is used generate the Data stage transaction of a USB Control transfer.\r
289//\r
290typedef struct _TRANSFER_TRB_CONTROL_STATUS {\r
291 UINT32 RsvdZ1;\r
292 UINT32 RsvdZ2;\r
293\r
294 UINT32 RsvdZ3:22;\r
295 UINT32 IntTarget:10;\r
296\r
297 UINT32 CycleBit:1;\r
298 UINT32 ENT:1;\r
299 UINT32 RsvdZ4:2;\r
300 UINT32 CH:1;\r
301 UINT32 IOC:1;\r
302 UINT32 RsvdZ5:4;\r
303 UINT32 Type:6;\r
304 UINT32 DIR:1;\r
305 UINT32 RsvdZ6:15;\r
306} TRANSFER_TRB_CONTROL_STATUS;\r
307\r
308//\r
309// 6.4.2.1 Transfer Event TRB\r
310// A Transfer Event provides the completion status associated with a Transfer TRB. Refer to section 4.11.3.1\r
311// for more information on the use and operation of Transfer Events.\r
312//\r
313typedef struct _EVT_TRB_TRANSFER {\r
314 UINT32 TRBPtrLo;\r
315\r
316 UINT32 TRBPtrHi;\r
317\r
318 UINT32 Length:24;\r
319 UINT32 Completecode:8;\r
320\r
321 UINT32 CycleBit:1;\r
322 UINT32 RsvdZ1:1;\r
323 UINT32 ED:1;\r
324 UINT32 RsvdZ2:7;\r
325 UINT32 Type:6;\r
326 UINT32 EndpointId:5;\r
327 UINT32 RsvdZ3:3;\r
328 UINT32 SlotId:8;\r
329} EVT_TRB_TRANSFER;\r
330\r
331//\r
332// 6.4.2.2 Command Completion Event TRB\r
333// A Command Completion Event TRB shall be generated by the xHC when a command completes on the\r
334// Command Ring. Refer to section 4.11.4 for more information on the use of Command Completion Events.\r
335//\r
336typedef struct _EVT_TRB_COMMAND_COMPLETION {\r
337 UINT32 TRBPtrLo;\r
338\r
339 UINT32 TRBPtrHi;\r
340\r
341 UINT32 RsvdZ2:24;\r
342 UINT32 Completecode:8;\r
343\r
344 UINT32 CycleBit:1;\r
345 UINT32 RsvdZ3:9;\r
346 UINT32 Type:6;\r
347 UINT32 VFID:8;\r
348 UINT32 SlotId:8;\r
349} EVT_TRB_COMMAND_COMPLETION;\r
350\r
351typedef union _TRB {\r
352 TRB_TEMPLATE TrbTemplate;\r
353 TRANSFER_TRB_NORMAL TrbNormal;\r
354 TRANSFER_TRB_CONTROL_SETUP TrbCtrSetup;\r
355 TRANSFER_TRB_CONTROL_DATA TrbCtrData;\r
356 TRANSFER_TRB_CONTROL_STATUS TrbCtrStatus;\r
357} TRB;\r
358\r
359//\r
360// 6.4.3.1 No Op Command TRB\r
361// The No Op Command TRB provides a simple means for verifying the operation of the Command Ring\r
362// mechanisms offered by the xHCI.\r
363//\r
364typedef struct _CMD_TRB_NO_OP {\r
365 UINT32 RsvdZ0;\r
366 UINT32 RsvdZ1;\r
367 UINT32 RsvdZ2;\r
368\r
369 UINT32 CycleBit:1;\r
370 UINT32 RsvdZ3:9;\r
371 UINT32 Type:6;\r
372 UINT32 RsvdZ4:16;\r
373} CMD_TRB_NO_OP;\r
374\r
375//\r
376// 6.4.3.2 Enable Slot Command TRB\r
377// The Enable Slot Command TRB causes the xHC to select an available Device Slot and return the ID of the\r
378// selected slot to the host in a Command Completion Event.\r
379//\r
380typedef struct _CMD_TRB_ENABLE_SLOT {\r
381 UINT32 RsvdZ0;\r
382 UINT32 RsvdZ1;\r
383 UINT32 RsvdZ2;\r
384\r
385 UINT32 CycleBit:1;\r
386 UINT32 RsvdZ3:9;\r
387 UINT32 Type:6;\r
388 UINT32 RsvdZ4:16;\r
389} CMD_TRB_ENABLE_SLOT;\r
390\r
391//\r
392// 6.4.3.3 Disable Slot Command TRB\r
393// The Disable Slot Command TRB releases any bandwidth assigned to the disabled slot and frees any\r
394// internal xHC resources assigned to the slot.\r
395//\r
396typedef struct _CMD_TRB_DISABLE_SLOT {\r
397 UINT32 RsvdZ0;\r
398 UINT32 RsvdZ1;\r
399 UINT32 RsvdZ2;\r
400\r
401 UINT32 CycleBit:1;\r
402 UINT32 RsvdZ3:9;\r
403 UINT32 Type:6;\r
404 UINT32 RsvdZ4:8;\r
405 UINT32 SlotId:8;\r
406} CMD_TRB_DISABLE_SLOT;\r
407\r
408//\r
409// 6.4.3.4 Address Device Command TRB\r
410// The Address Device Command TRB transitions the selected Device Context from the Default to the\r
411// Addressed state and causes the xHC to select an address for the USB device in the Default State and\r
412// issue a SET_ADDRESS request to the USB device.\r
413//\r
414typedef struct _CMD_TRB_ADDRESS_DEVICE {\r
415 UINT32 PtrLo;\r
416\r
417 UINT32 PtrHi;\r
418\r
419 UINT32 RsvdZ1;\r
420\r
421 UINT32 CycleBit:1;\r
422 UINT32 RsvdZ2:8;\r
423 UINT32 BSR:1;\r
424 UINT32 Type:6;\r
425 UINT32 RsvdZ3:8;\r
426 UINT32 SlotId:8;\r
427} CMD_TRB_ADDRESS_DEVICE;\r
428\r
429//\r
430// 6.4.3.5 Configure Endpoint Command TRB\r
431// The Configure Endpoint Command TRB evaluates the bandwidth and resource requirements of the\r
432// endpoints selected by the command.\r
433//\r
434typedef struct _CMD_TRB_CONFIG_ENDPOINT {\r
435 UINT32 PtrLo;\r
436\r
437 UINT32 PtrHi;\r
438\r
439 UINT32 RsvdZ1;\r
440\r
441 UINT32 CycleBit:1;\r
442 UINT32 RsvdZ2:8;\r
443 UINT32 DC:1;\r
444 UINT32 Type:6;\r
445 UINT32 RsvdZ3:8;\r
446 UINT32 SlotId:8;\r
447} CMD_TRB_CONFIG_ENDPOINT;\r
448\r
449//\r
450// 6.4.3.6 Evaluate Context Command TRB\r
451// The Evaluate Context Command TRB is used by system software to inform the xHC that the selected\r
452// Context data structures in the Device Context have been modified by system software and that the xHC\r
453// shall evaluate any changes\r
454//\r
455typedef struct _CMD_TRB_EVALUATE_CONTEXT {\r
456 UINT32 PtrLo;\r
457\r
458 UINT32 PtrHi;\r
459\r
460 UINT32 RsvdZ1;\r
461\r
462 UINT32 CycleBit:1;\r
463 UINT32 RsvdZ2:9;\r
464 UINT32 Type:6;\r
465 UINT32 RsvdZ3:8;\r
466 UINT32 SlotId:8;\r
467} CMD_TRB_EVALUATE_CONTEXT;\r
468\r
469//\r
470// 6.4.3.7 Reset Endpoint Command TRB\r
471// The Reset Endpoint Command TRB is used by system software to reset a specified Transfer Ring\r
472//\r
473typedef struct _CMD_TRB_RESET_ENDPOINT {\r
474 UINT32 RsvdZ0;\r
475 UINT32 RsvdZ1;\r
476 UINT32 RsvdZ2;\r
477\r
478 UINT32 CycleBit:1;\r
479 UINT32 RsvdZ3:8;\r
480 UINT32 TSP:1;\r
481 UINT32 Type:6;\r
482 UINT32 EDID:5;\r
483 UINT32 RsvdZ4:3;\r
484 UINT32 SlotId:8;\r
485} CMD_TRB_RESET_ENDPOINT;\r
486\r
487//\r
488// 6.4.3.8 Stop Endpoint Command TRB\r
489// The Stop Endpoint Command TRB command allows software to stop the xHC execution of the TDs on a\r
490// Transfer Ring and temporarily take ownership of TDs that had previously been passed to the xHC.\r
491//\r
492typedef struct _CMD_TRB_STOP_ENDPOINT {\r
493 UINT32 RsvdZ0;\r
494 UINT32 RsvdZ1;\r
495 UINT32 RsvdZ2;\r
496\r
497 UINT32 CycleBit:1;\r
498 UINT32 RsvdZ3:9;\r
499 UINT32 Type:6;\r
500 UINT32 EDID:5;\r
501 UINT32 RsvdZ4:2;\r
502 UINT32 SP:1;\r
503 UINT32 SlotId:8;\r
504} CMD_TRB_STOP_ENDPOINT;\r
505\r
506//\r
507// 6.4.3.9 Set TR Dequeue Pointer Command TRB\r
508// The Set TR Dequeue Pointer Command TRB is used by system software to modify the TR Dequeue\r
509// Pointer and DCS fields of an Endpoint or Stream Context.\r
510//\r
511typedef struct _CMD_SET_TR_DEQ_POINTER {\r
512 UINT32 PtrLo;\r
513\r
514 UINT32 PtrHi;\r
515\r
516 UINT32 RsvdZ1:16;\r
517 UINT32 StreamID:16;\r
518\r
519 UINT32 CycleBit:1;\r
520 UINT32 RsvdZ2:9;\r
521 UINT32 Type:6;\r
522 UINT32 Endpoint:5;\r
523 UINT32 RsvdZ3:3;\r
524 UINT32 SlotId:8;\r
525} CMD_SET_TR_DEQ_POINTER;\r
526\r
527//\r
528// 6.4.4.1 Link TRB\r
529// A Link TRB provides support for non-contiguous TRB Rings.\r
530//\r
531typedef struct _LINK_TRB {\r
532 UINT32 PtrLo;\r
533\r
534 UINT32 PtrHi;\r
535\r
536 UINT32 RsvdZ1:22;\r
537 UINT32 InterTarget:10;\r
538\r
539 UINT32 CycleBit:1;\r
540 UINT32 TC:1;\r
541 UINT32 RsvdZ2:2;\r
542 UINT32 CH:1;\r
543 UINT32 IOC:1;\r
544 UINT32 RsvdZ3:4;\r
545 UINT32 Type:6;\r
546 UINT32 RsvdZ4:16;\r
547} LINK_TRB;\r
548\r
549//\r
550// 6.2.2 Slot Context\r
551//\r
552typedef struct _SLOT_CONTEXT {\r
553 UINT32 RouteString:20;\r
554 UINT32 Speed:4;\r
555 UINT32 RsvdZ1:1;\r
556 UINT32 MTT:1;\r
557 UINT32 Hub:1;\r
558 UINT32 ContextEntries:5;\r
559\r
560 UINT32 MaxExitLatency:16;\r
561 UINT32 RootHubPortNum:8;\r
562 UINT32 PortNum:8;\r
563\r
564 UINT32 TTHubSlotId:8;\r
565 UINT32 TTPortNum:8;\r
566 UINT32 TTT:2;\r
567 UINT32 RsvdZ2:4;\r
568 UINT32 InterTarget:10;\r
569\r
570 UINT32 DeviceAddress:8;\r
571 UINT32 RsvdZ3:19;\r
572 UINT32 SlotState:5;\r
573\r
574 UINT32 RsvdZ4;\r
575 UINT32 RsvdZ5;\r
576 UINT32 RsvdZ6;\r
577 UINT32 RsvdZ7;\r
578} SLOT_CONTEXT;\r
579\r
580typedef struct _SLOT_CONTEXT_64 {\r
581 UINT32 RouteString:20;\r
582 UINT32 Speed:4;\r
583 UINT32 RsvdZ1:1;\r
584 UINT32 MTT:1;\r
585 UINT32 Hub:1;\r
586 UINT32 ContextEntries:5;\r
587\r
588 UINT32 MaxExitLatency:16;\r
589 UINT32 RootHubPortNum:8;\r
590 UINT32 PortNum:8;\r
591\r
592 UINT32 TTHubSlotId:8;\r
593 UINT32 TTPortNum:8;\r
594 UINT32 TTT:2;\r
595 UINT32 RsvdZ2:4;\r
596 UINT32 InterTarget:10;\r
597\r
598 UINT32 DeviceAddress:8;\r
599 UINT32 RsvdZ3:19;\r
600 UINT32 SlotState:5;\r
601\r
602 UINT32 RsvdZ4;\r
603 UINT32 RsvdZ5;\r
604 UINT32 RsvdZ6;\r
605 UINT32 RsvdZ7;\r
606\r
607 UINT32 RsvdZ8;\r
608 UINT32 RsvdZ9;\r
609 UINT32 RsvdZ10;\r
610 UINT32 RsvdZ11;\r
611\r
612 UINT32 RsvdZ12;\r
613 UINT32 RsvdZ13;\r
614 UINT32 RsvdZ14;\r
615 UINT32 RsvdZ15;\r
616\r
617} SLOT_CONTEXT_64;\r
618\r
619\r
620//\r
621// 6.2.3 Endpoint Context\r
622//\r
623typedef struct _ENDPOINT_CONTEXT {\r
624 UINT32 EPState:3;\r
625 UINT32 RsvdZ1:5;\r
626 UINT32 Mult:2;\r
627 UINT32 MaxPStreams:5;\r
628 UINT32 LSA:1;\r
629 UINT32 Interval:8;\r
630 UINT32 RsvdZ2:8;\r
631\r
632 UINT32 RsvdZ3:1;\r
633 UINT32 CErr:2;\r
634 UINT32 EPType:3;\r
635 UINT32 RsvdZ4:1;\r
636 UINT32 HID:1;\r
637 UINT32 MaxBurstSize:8;\r
638 UINT32 MaxPacketSize:16;\r
639\r
640 UINT32 PtrLo;\r
641\r
642 UINT32 PtrHi;\r
643\r
644 UINT32 AverageTRBLength:16;\r
645 UINT32 MaxESITPayload:16;\r
646\r
647 UINT32 RsvdZ5;\r
648 UINT32 RsvdZ6;\r
649 UINT32 RsvdZ7;\r
650} ENDPOINT_CONTEXT;\r
651\r
652typedef struct _ENDPOINT_CONTEXT_64 {\r
653 UINT32 EPState:3;\r
654 UINT32 RsvdZ1:5;\r
655 UINT32 Mult:2;\r
656 UINT32 MaxPStreams:5;\r
657 UINT32 LSA:1;\r
658 UINT32 Interval:8;\r
659 UINT32 RsvdZ2:8;\r
660\r
661 UINT32 RsvdZ3:1;\r
662 UINT32 CErr:2;\r
663 UINT32 EPType:3;\r
664 UINT32 RsvdZ4:1;\r
665 UINT32 HID:1;\r
666 UINT32 MaxBurstSize:8;\r
667 UINT32 MaxPacketSize:16;\r
668\r
669 UINT32 PtrLo;\r
670\r
671 UINT32 PtrHi;\r
672\r
673 UINT32 AverageTRBLength:16;\r
674 UINT32 MaxESITPayload:16;\r
675\r
676 UINT32 RsvdZ5;\r
677 UINT32 RsvdZ6;\r
678 UINT32 RsvdZ7;\r
679\r
680 UINT32 RsvdZ8;\r
681 UINT32 RsvdZ9;\r
682 UINT32 RsvdZ10;\r
683 UINT32 RsvdZ11;\r
684\r
685 UINT32 RsvdZ12;\r
686 UINT32 RsvdZ13;\r
687 UINT32 RsvdZ14;\r
688 UINT32 RsvdZ15;\r
689\r
690} ENDPOINT_CONTEXT_64;\r
691\r
692\r
693//\r
694// 6.2.5.1 Input Control Context\r
695//\r
696typedef struct _INPUT_CONTRL_CONTEXT {\r
697 UINT32 Dword1;\r
698 UINT32 Dword2;\r
699 UINT32 RsvdZ1;\r
700 UINT32 RsvdZ2;\r
701 UINT32 RsvdZ3;\r
702 UINT32 RsvdZ4;\r
703 UINT32 RsvdZ5;\r
704 UINT32 RsvdZ6;\r
705} INPUT_CONTRL_CONTEXT;\r
706\r
707typedef struct _INPUT_CONTRL_CONTEXT_64 {\r
708 UINT32 Dword1;\r
709 UINT32 Dword2;\r
710 UINT32 RsvdZ1;\r
711 UINT32 RsvdZ2;\r
712 UINT32 RsvdZ3;\r
713 UINT32 RsvdZ4;\r
714 UINT32 RsvdZ5;\r
715 UINT32 RsvdZ6;\r
716 UINT32 RsvdZ7;\r
717 UINT32 RsvdZ8;\r
718 UINT32 RsvdZ9;\r
719 UINT32 RsvdZ10;\r
720 UINT32 RsvdZ11;\r
721 UINT32 RsvdZ12;\r
722 UINT32 RsvdZ13;\r
723 UINT32 RsvdZ14;\r
724} INPUT_CONTRL_CONTEXT_64;\r
725\r
726//\r
727// 6.2.1 Device Context\r
728//\r
729typedef struct _DEVICE_CONTEXT {\r
730 SLOT_CONTEXT Slot;\r
731 ENDPOINT_CONTEXT EP[31];\r
732} DEVICE_CONTEXT;\r
733\r
734typedef struct _DEVICE_CONTEXT_64 {\r
735 SLOT_CONTEXT_64 Slot;\r
736 ENDPOINT_CONTEXT_64 EP[31];\r
737} DEVICE_CONTEXT_64;\r
738\r
739//\r
740// 6.2.5 Input Context\r
741//\r
742typedef struct _INPUT_CONTEXT {\r
743 INPUT_CONTRL_CONTEXT InputControlContext;\r
744 SLOT_CONTEXT Slot;\r
745 ENDPOINT_CONTEXT EP[31];\r
746} INPUT_CONTEXT;\r
747\r
748typedef struct _INPUT_CONTEXT_64 {\r
749 INPUT_CONTRL_CONTEXT_64 InputControlContext;\r
750 SLOT_CONTEXT_64 Slot;\r
751 ENDPOINT_CONTEXT_64 EP[31];\r
752} INPUT_CONTEXT_64;\r
753\r
754/**\r
755 Execute the transfer by polling the URB. This is a synchronous operation.\r
756\r
757 @param Xhc The XHCI device.\r
758 @param CmdTransfer The executed URB is for cmd transfer or not.\r
759 @param Urb The URB to execute.\r
760 @param Timeout The time to wait before abort, in millisecond.\r
761\r
762 @return EFI_DEVICE_ERROR The transfer failed due to transfer error.\r
763 @return EFI_TIMEOUT The transfer failed due to time out.\r
764 @return EFI_SUCCESS The transfer finished OK.\r
765\r
766**/\r
767EFI_STATUS\r
768XhcPeiExecTransfer (\r
769 IN PEI_XHC_DEV *Xhc,\r
770 IN BOOLEAN CmdTransfer,\r
771 IN URB *Urb,\r
772 IN UINTN Timeout\r
773 );\r
774\r
775/**\r
776 Find out the actual device address according to the requested device address from UsbBus.\r
777\r
778 @param Xhc The XHCI device.\r
779 @param BusDevAddr The requested device address by UsbBus upper driver.\r
780\r
781 @return The actual device address assigned to the device.\r
782\r
783**/\r
784UINT8\r
785XhcPeiBusDevAddrToSlotId (\r
786 IN PEI_XHC_DEV *Xhc,\r
787 IN UINT8 BusDevAddr\r
788 );\r
789\r
790/**\r
791 Find out the slot id according to the device's route string.\r
792\r
793 @param Xhc The XHCI device.\r
794 @param RouteString The route string described the device location.\r
795\r
796 @return The slot id used by the device.\r
797\r
798**/\r
799UINT8\r
800XhcPeiRouteStringToSlotId (\r
801 IN PEI_XHC_DEV *Xhc,\r
802 IN USB_DEV_ROUTE RouteString\r
803 );\r
804\r
805/**\r
806 Calculate the device context index by endpoint address and direction.\r
807\r
808 @param EpAddr The target endpoint number.\r
809 @param Direction The direction of the target endpoint.\r
810\r
811 @return The device context index of endpoint.\r
812\r
813**/\r
814UINT8\r
815XhcPeiEndpointToDci (\r
816 IN UINT8 EpAddr,\r
817 IN EFI_USB_DATA_DIRECTION Direction\r
818 );\r
819\r
820/**\r
821 Ring the door bell to notify XHCI there is a transaction to be executed.\r
822\r
823 @param Xhc The XHCI device.\r
824 @param SlotId The slot id of the target device.\r
825 @param Dci The device context index of the target slot or endpoint.\r
826\r
827**/\r
828VOID\r
829XhcPeiRingDoorBell (\r
830 IN PEI_XHC_DEV *Xhc,\r
831 IN UINT8 SlotId,\r
832 IN UINT8 Dci\r
833 );\r
834\r
835/**\r
836 Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.\r
837\r
838 @param Xhc The XHCI device.\r
839 @param ParentRouteChart The route string pointed to the parent device if it exists.\r
840 @param Port The port to be polled.\r
841 @param PortState The port state.\r
842\r
843 @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.\r
844 @retval Others Should not appear.\r
845\r
846**/\r
847EFI_STATUS\r
848XhcPeiPollPortStatusChange (\r
849 IN PEI_XHC_DEV *Xhc,\r
850 IN USB_DEV_ROUTE ParentRouteChart,\r
851 IN UINT8 Port,\r
852 IN EFI_USB_PORT_STATUS *PortState\r
853 );\r
854\r
855/**\r
856 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r
857\r
858 @param Xhc The XHCI device.\r
859 @param SlotId The slot id to be configured.\r
860 @param PortNum The total number of downstream port supported by the hub.\r
861 @param TTT The TT think time of the hub device.\r
862 @param MTT The multi-TT of the hub device.\r
863\r
864 @retval EFI_SUCCESS Successfully configure the hub device's slot context.\r
865\r
866**/\r
867EFI_STATUS\r
868XhcPeiConfigHubContext (\r
869 IN PEI_XHC_DEV *Xhc,\r
870 IN UINT8 SlotId,\r
871 IN UINT8 PortNum,\r
872 IN UINT8 TTT,\r
873 IN UINT8 MTT\r
874 );\r
875\r
876/**\r
877 Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r
878\r
879 @param Xhc The XHCI device.\r
880 @param SlotId The slot id to be configured.\r
881 @param PortNum The total number of downstream port supported by the hub.\r
882 @param TTT The TT think time of the hub device.\r
883 @param MTT The multi-TT of the hub device.\r
884\r
885 @retval EFI_SUCCESS Successfully configure the hub device's slot context.\r
886\r
887**/\r
888EFI_STATUS\r
889XhcPeiConfigHubContext64 (\r
890 IN PEI_XHC_DEV *Xhc,\r
891 IN UINT8 SlotId,\r
892 IN UINT8 PortNum,\r
893 IN UINT8 TTT,\r
894 IN UINT8 MTT\r
895 );\r
896\r
897/**\r
898 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r
899\r
900 @param Xhc The XHCI device.\r
901 @param SlotId The slot id to be configured.\r
902 @param DeviceSpeed The device's speed.\r
903 @param ConfigDesc The pointer to the usb device configuration descriptor.\r
904\r
905 @retval EFI_SUCCESS Successfully configure all the device endpoints.\r
906\r
907**/\r
908EFI_STATUS\r
909XhcPeiSetConfigCmd (\r
910 IN PEI_XHC_DEV *Xhc,\r
911 IN UINT8 SlotId,\r
912 IN UINT8 DeviceSpeed,\r
913 IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r
914 );\r
915\r
916/**\r
917 Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r
918\r
919 @param Xhc The XHCI device.\r
920 @param SlotId The slot id to be configured.\r
921 @param DeviceSpeed The device's speed.\r
922 @param ConfigDesc The pointer to the usb device configuration descriptor.\r
923\r
924 @retval EFI_SUCCESS Successfully configure all the device endpoints.\r
925\r
926**/\r
927EFI_STATUS\r
928XhcPeiSetConfigCmd64 (\r
929 IN PEI_XHC_DEV *Xhc,\r
930 IN UINT8 SlotId,\r
931 IN UINT8 DeviceSpeed,\r
932 IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r
933 );\r
934\r
12e6c738
FT		 935/**\r
936 Stop endpoint through XHCI's Stop_Endpoint cmd.\r
937\r
938 @param Xhc The XHCI device.\r
939 @param SlotId The slot id of the target device.\r
940 @param Dci The device context index of the target slot or endpoint.\r
941\r
942 @retval EFI_SUCCESS Stop endpoint successfully.\r
943 @retval Others Failed to stop endpoint.\r
944\r
945**/\r
946EFI_STATUS\r
947EFIAPI\r
948XhcPeiStopEndpoint (\r
949 IN PEI_XHC_DEV *Xhc,\r
950 IN UINT8 SlotId,\r
951 IN UINT8 Dci\r
952 );\r
953\r
954/**\r
955 Reset endpoint through XHCI's Reset_Endpoint cmd.\r
956\r
957 @param Xhc The XHCI device.\r
958 @param SlotId The slot id of the target device.\r
959 @param Dci The device context index of the target slot or endpoint.\r
960\r
961 @retval EFI_SUCCESS Reset endpoint successfully.\r
962 @retval Others Failed to reset endpoint.\r
963\r
964**/\r
965EFI_STATUS\r
966EFIAPI\r
967XhcPeiResetEndpoint (\r
968 IN PEI_XHC_DEV *Xhc,\r
969 IN UINT8 SlotId,\r
970 IN UINT8 Dci\r
971 );\r
972\r
973/**\r
974 Set transfer ring dequeue pointer through XHCI's Set_Tr_Dequeue_Pointer cmd.\r
975\r
976 @param Xhc The XHCI device.\r
977 @param SlotId The slot id of the target device.\r
978 @param Dci The device context index of the target slot or endpoint.\r
979 @param Urb The dequeue pointer of the transfer ring specified\r
980 by the urb to be updated.\r
981\r
982 @retval EFI_SUCCESS Set transfer ring dequeue pointer succeeds.\r
983 @retval Others Failed to set transfer ring dequeue pointer.\r
984\r
985**/\r
986EFI_STATUS\r
987EFIAPI\r
988XhcPeiSetTrDequeuePointer (\r
989 IN PEI_XHC_DEV *Xhc,\r
990 IN UINT8 SlotId,\r
991 IN UINT8 Dci,\r
992 IN URB *Urb\r
993 );\r
994\r
d987459f
SZ		 995/**\r
996 Assign and initialize the device slot for a new device.\r
997\r
998 @param Xhc The XHCI device.\r
999 @param ParentRouteChart The route string pointed to the parent device.\r
1000 @param ParentPort The port at which the device is located.\r
1001 @param RouteChart The route string pointed to the device.\r
1002 @param DeviceSpeed The device speed.\r
1003\r
1004 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.\r
1005 @retval Others Fail to initialize device slot.\r
1006\r
1007**/\r
1008EFI_STATUS\r
1009XhcPeiInitializeDeviceSlot (\r
1010 IN PEI_XHC_DEV *Xhc,\r
1011 IN USB_DEV_ROUTE ParentRouteChart,\r
1012 IN UINT16 ParentPort,\r
1013 IN USB_DEV_ROUTE RouteChart,\r
1014 IN UINT8 DeviceSpeed\r
1015 );\r
1016\r
1017/**\r
1018 Assign and initialize the device slot for a new device.\r
1019\r
1020 @param Xhc The XHCI device.\r
1021 @param ParentRouteChart The route string pointed to the parent device.\r
1022 @param ParentPort The port at which the device is located.\r
1023 @param RouteChart The route string pointed to the device.\r
1024 @param DeviceSpeed The device speed.\r
1025\r
1026 @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.\r
1027 @retval Others Fail to initialize device slot.\r
1028\r
1029**/\r
1030EFI_STATUS\r
1031XhcPeiInitializeDeviceSlot64 (\r
1032 IN PEI_XHC_DEV *Xhc,\r
1033 IN USB_DEV_ROUTE ParentRouteChart,\r
1034 IN UINT16 ParentPort,\r
1035 IN USB_DEV_ROUTE RouteChart,\r
1036 IN UINT8 DeviceSpeed\r
1037 );\r
1038\r
1039/**\r
1040 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r
1041\r
1042 @param Xhc The XHCI device.\r
1043 @param SlotId The slot id to be evaluated.\r
1044 @param MaxPacketSize The max packet size supported by the device control transfer.\r
1045\r
1046 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.\r
1047\r
1048**/\r
1049EFI_STATUS\r
1050XhcPeiEvaluateContext (\r
1051 IN PEI_XHC_DEV *Xhc,\r
1052 IN UINT8 SlotId,\r
1053 IN UINT32 MaxPacketSize\r
1054 );\r
1055\r
1056/**\r
1057 Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r
1058\r
1059 @param Xhc The XHCI device.\r
1060 @param SlotId The slot id to be evaluated.\r
1061 @param MaxPacketSize The max packet size supported by the device control transfer.\r
1062\r
1063 @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.\r
1064\r
1065**/\r
1066EFI_STATUS\r
1067XhcPeiEvaluateContext64 (\r
1068 IN PEI_XHC_DEV *Xhc,\r
1069 IN UINT8 SlotId,\r
1070 IN UINT32 MaxPacketSize\r
1071 );\r
1072\r
1073/**\r
1074 Disable the specified device slot.\r
1075\r
1076 @param Xhc The XHCI device.\r
1077 @param SlotId The slot id to be disabled.\r
1078\r
1079 @retval EFI_SUCCESS Successfully disable the device slot.\r
1080\r
1081**/\r
1082EFI_STATUS\r
1083XhcPeiDisableSlotCmd (\r
1084 IN PEI_XHC_DEV *Xhc,\r
1085 IN UINT8 SlotId\r
1086 );\r
1087\r
1088/**\r
1089 Disable the specified device slot.\r
1090\r
1091 @param Xhc The XHCI device.\r
1092 @param SlotId The slot id to be disabled.\r
1093\r
1094 @retval EFI_SUCCESS Successfully disable the device slot.\r
1095\r
1096**/\r
1097EFI_STATUS\r
1098XhcPeiDisableSlotCmd64 (\r
1099 IN PEI_XHC_DEV *Xhc,\r
1100 IN UINT8 SlotId\r
1101 );\r
1102\r
1103/**\r
1104 System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted\r
1105 condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint\r
1106 Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is\r
1107 reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the\r
1108 Stopped to the Running state.\r
1109\r
1110 @param Xhc The XHCI device.\r
1111 @param Urb The urb which makes the endpoint halted.\r
1112\r
1113 @retval EFI_SUCCESS The recovery is successful.\r
1114 @retval Others Failed to recovery halted endpoint.\r
1115\r
1116**/\r
1117EFI_STATUS\r
1118XhcPeiRecoverHaltedEndpoint (\r
1119 IN PEI_XHC_DEV *Xhc,\r
1120 IN URB *Urb\r
1121 );\r
1122\r
12e6c738
FT		 1123/**\r
1124 System software shall use a Stop Endpoint Command (section 4.6.9) and the Set TR Dequeue Pointer\r
1125 Command (section 4.6.10) to remove the timed-out TDs from the xHC transfer ring. The next write to\r
1126 the Doorbell of the Endpoint will transition the Endpoint Context from the Stopped to the Running\r
1127 state.\r
1128\r
1129 @param Xhc The XHCI device.\r
1130 @param Urb The urb which doesn't get completed in a specified timeout range.\r
1131\r
1132 @retval EFI_SUCCESS The dequeuing of the TDs is successful.\r
1133 @retval Others Failed to stop the endpoint and dequeue the TDs.\r
1134\r
1135**/\r
1136EFI_STATUS\r
1137XhcPeiDequeueTrbFromEndpoint (\r
1138 IN PEI_XHC_DEV *Xhc,\r
1139 IN URB *Urb\r
1140 );\r
1141\r
d987459f
SZ		 1142/**\r
1143 Create a new URB for a new transaction.\r
1144\r
1145 @param Xhc The XHCI device\r
1146 @param DevAddr The device address\r
1147 @param EpAddr Endpoint addrress\r
1148 @param DevSpeed The device speed\r
1149 @param MaxPacket The max packet length of the endpoint\r
1150 @param Type The transaction type\r
1151 @param Request The standard USB request for control transfer\r
1152 @param Data The user data to transfer\r
1153 @param DataLen The length of data buffer\r
1154 @param Callback The function to call when data is transferred\r
1155 @param Context The context to the callback\r
1156\r
1157 @return Created URB or NULL\r
1158\r
1159**/\r
1160URB*\r
1161XhcPeiCreateUrb (\r
1162 IN PEI_XHC_DEV *Xhc,\r
1163 IN UINT8 DevAddr,\r
1164 IN UINT8 EpAddr,\r
1165 IN UINT8 DevSpeed,\r
1166 IN UINTN MaxPacket,\r
1167 IN UINTN Type,\r
1168 IN EFI_USB_DEVICE_REQUEST *Request,\r
1169 IN VOID *Data,\r
1170 IN UINTN DataLen,\r
1171 IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r
1172 IN VOID *Context\r
1173 );\r
1174\r
1175/**\r
1176 Free an allocated URB.\r
1177\r
1178 @param Xhc The XHCI device.\r
1179 @param Urb The URB to free.\r
1180\r
1181**/\r
1182VOID\r
1183XhcPeiFreeUrb (\r
1184 IN PEI_XHC_DEV *Xhc,\r
1185 IN URB *Urb\r
1186 );\r
1187\r
1188/**\r
1189 Create a transfer TRB.\r
1190\r
1191 @param Xhc The XHCI device\r
1192 @param Urb The urb used to construct the transfer TRB.\r
1193\r
1194 @return Created TRB or NULL\r
1195\r
1196**/\r
1197EFI_STATUS\r
1198XhcPeiCreateTransferTrb (\r
1199 IN PEI_XHC_DEV *Xhc,\r
1200 IN URB *Urb\r
1201 );\r
1202\r
1203/**\r
1204 Synchronize the specified transfer ring to update the enqueue and dequeue pointer.\r
1205\r
1206 @param Xhc The XHCI device.\r
1207 @param TrsRing The transfer ring to sync.\r
1208\r
1209 @retval EFI_SUCCESS The transfer ring is synchronized successfully.\r
1210\r
1211**/\r
1212EFI_STATUS\r
1213XhcPeiSyncTrsRing (\r
1214 IN PEI_XHC_DEV *Xhc,\r
1215 IN TRANSFER_RING *TrsRing\r
1216 );\r
1217\r
1218/**\r
1219 Create XHCI transfer ring.\r
1220\r
1221 @param Xhc The XHCI Device.\r
1222 @param TrbNum The number of TRB in the ring.\r
1223 @param TransferRing The created transfer ring.\r
1224\r
1225**/\r
1226VOID\r
1227XhcPeiCreateTransferRing (\r
1228 IN PEI_XHC_DEV *Xhc,\r
1229 IN UINTN TrbNum,\r
1230 OUT TRANSFER_RING *TransferRing\r
1231 );\r
1232\r
1233/**\r
1234 Check if there is a new generated event.\r
1235\r
1236 @param Xhc The XHCI device.\r
1237 @param EvtRing The event ring to check.\r
1238 @param NewEvtTrb The new event TRB found.\r
1239\r
1240 @retval EFI_SUCCESS Found a new event TRB at the event ring.\r
1241 @retval EFI_NOT_READY The event ring has no new event.\r
1242\r
1243**/\r
1244EFI_STATUS\r
1245XhcPeiCheckNewEvent (\r
1246 IN PEI_XHC_DEV *Xhc,\r
1247 IN EVENT_RING *EvtRing,\r
1248 OUT TRB_TEMPLATE **NewEvtTrb\r
1249 );\r
1250\r
1251/**\r
1252 Synchronize the specified event ring to update the enqueue and dequeue pointer.\r
1253\r
1254 @param Xhc The XHCI device.\r
1255 @param EvtRing The event ring to sync.\r
1256\r
1257 @retval EFI_SUCCESS The event ring is synchronized successfully.\r
1258\r
1259**/\r
1260EFI_STATUS\r
1261XhcPeiSyncEventRing (\r
1262 IN PEI_XHC_DEV *Xhc,\r
1263 IN EVENT_RING *EvtRing\r
1264 );\r
1265\r
1266/**\r
1267 Create XHCI event ring.\r
1268\r
1269 @param Xhc The XHCI device.\r
1270 @param EventRing The created event ring.\r
1271\r
1272**/\r
1273VOID\r
1274XhcPeiCreateEventRing (\r
1275 IN PEI_XHC_DEV *Xhc,\r
1276 OUT EVENT_RING *EventRing\r
1277 );\r
1278\r
1279/**\r
1280 Initialize the XHCI host controller for schedule.\r
1281\r
1282 @param Xhc The XHCI device to be initialized.\r
1283\r
1284**/\r
1285VOID\r
1286XhcPeiInitSched (\r
1287 IN PEI_XHC_DEV *Xhc\r
1288 );\r
1289\r
1290/**\r
1291 Free the resouce allocated at initializing schedule.\r
1292\r
1293 @param Xhc The XHCI device.\r
1294\r
1295**/\r
1296VOID\r
1297XhcPeiFreeSched (\r
1298 IN PEI_XHC_DEV *Xhc\r
1299 );\r
1300\r
1301#endif\r
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