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MdeModulePkg/SdMmcPciHcDxe: Use BaseClk if the target clock is larger
[mirror_edk2.git] / MdeModulePkg / Bus / Sd / EmmcBlockIoPei / EmmcHci.c
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48555339
FT		 1/** @file\r
2\r
3 Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
4 This program and the accompanying materials\r
5 are licensed and made available under the terms and conditions of the BSD License\r
6 which accompanies this distribution. The full text of the license may be found at\r
7 http://opensource.org/licenses/bsd-license.php.\r
8\r
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
11\r
12**/\r
13\r
14#include "EmmcBlockIoPei.h"\r
15\r
16/**\r
17 Read/Write specified EMMC host controller mmio register.\r
18\r
19 @param[in] Address The address of the mmio register to be read/written.\r
20 @param[in] Read A boolean to indicate it's read or write operation.\r
21 @param[in] Count The width of the mmio register in bytes.\r
22 Must be 1, 2 , 4 or 8 bytes.\r
23 @param[in, out] Data For read operations, the destination buffer to store\r
24 the results. For write operations, the source buffer\r
25 to write data from. The caller is responsible for\r
26 having ownership of the data buffer and ensuring its\r
27 size not less than Count bytes.\r
28\r
29 @retval EFI_INVALID_PARAMETER The Address or the Data or the Count is not valid.\r
30 @retval EFI_SUCCESS The read/write operation succeeds.\r
31 @retval Others The read/write operation fails.\r
32\r
33**/\r
34EFI_STATUS\r
35EFIAPI\r
36EmmcPeimHcRwMmio (\r
37 IN UINTN Address,\r
38 IN BOOLEAN Read,\r
39 IN UINT8 Count,\r
40 IN OUT VOID *Data\r
41 )\r
42{\r
43 if ((Address == 0) || (Data == NULL)) {\r
44 return EFI_INVALID_PARAMETER;\r
45 }\r
46\r
47 if ((Count != 1) && (Count != 2) && (Count != 4) && (Count != 8)) {\r
48 return EFI_INVALID_PARAMETER;\r
49 }\r
50\r
51 switch (Count) {\r
52 case 1:\r
53 if (Read) {\r
54 *(UINT8*)Data = MmioRead8 (Address);\r
55 } else {\r
56 MmioWrite8 (Address, *(UINT8*)Data);\r
57 }\r
58 break;\r
59 case 2:\r
60 if (Read) {\r
61 *(UINT16*)Data = MmioRead16 (Address);\r
62 } else {\r
63 MmioWrite16 (Address, *(UINT16*)Data);\r
64 }\r
65 break;\r
66 case 4:\r
67 if (Read) {\r
68 *(UINT32*)Data = MmioRead32 (Address);\r
69 } else {\r
70 MmioWrite32 (Address, *(UINT32*)Data);\r
71 }\r
72 break;\r
73 case 8:\r
74 if (Read) {\r
75 *(UINT64*)Data = MmioRead64 (Address);\r
76 } else {\r
77 MmioWrite64 (Address, *(UINT64*)Data);\r
78 }\r
79 break;\r
80 default:\r
81 ASSERT (FALSE);\r
82 return EFI_INVALID_PARAMETER;\r
83 }\r
84\r
85 return EFI_SUCCESS;\r
86}\r
87\r
88/**\r
89 Do OR operation with the value of the specified EMMC host controller mmio register.\r
90\r
91 @param[in] Address The address of the mmio register to be read/written.\r
92 @param[in] Count The width of the mmio register in bytes.\r
93 Must be 1, 2 , 4 or 8 bytes.\r
94 @param[in] OrData The pointer to the data used to do OR operation.\r
95 The caller is responsible for having ownership of\r
96 the data buffer and ensuring its size not less than\r
97 Count bytes.\r
98\r
99 @retval EFI_INVALID_PARAMETER The Address or the OrData or the Count is not valid.\r
100 @retval EFI_SUCCESS The OR operation succeeds.\r
101 @retval Others The OR operation fails.\r
102\r
103**/\r
104EFI_STATUS\r
105EFIAPI\r
106EmmcPeimHcOrMmio (\r
107 IN UINTN Address,\r
108 IN UINT8 Count,\r
109 IN VOID *OrData\r
110 )\r
111{\r
112 EFI_STATUS Status;\r
113 UINT64 Data;\r
114 UINT64 Or;\r
115\r
116 Status = EmmcPeimHcRwMmio (Address, TRUE, Count, &Data);\r
117 if (EFI_ERROR (Status)) {\r
118 return Status;\r
119 }\r
120\r
121 if (Count == 1) {\r
122 Or = *(UINT8*) OrData;\r
123 } else if (Count == 2) {\r
124 Or = *(UINT16*) OrData;\r
125 } else if (Count == 4) {\r
126 Or = *(UINT32*) OrData;\r
127 } else if (Count == 8) {\r
128 Or = *(UINT64*) OrData;\r
129 } else {\r
130 return EFI_INVALID_PARAMETER;\r
131 }\r
132\r
133 Data |= Or;\r
134 Status = EmmcPeimHcRwMmio (Address, FALSE, Count, &Data);\r
135\r
136 return Status;\r
137}\r
138\r
139/**\r
140 Do AND operation with the value of the specified EMMC host controller mmio register.\r
141\r
142 @param[in] Address The address of the mmio register to be read/written.\r
143 @param[in] Count The width of the mmio register in bytes.\r
144 Must be 1, 2 , 4 or 8 bytes.\r
145 @param[in] AndData The pointer to the data used to do AND operation.\r
146 The caller is responsible for having ownership of\r
147 the data buffer and ensuring its size not less than\r
148 Count bytes.\r
149\r
150 @retval EFI_INVALID_PARAMETER The Address or the AndData or the Count is not valid.\r
151 @retval EFI_SUCCESS The AND operation succeeds.\r
152 @retval Others The AND operation fails.\r
153\r
154**/\r
155EFI_STATUS\r
156EFIAPI\r
157EmmcPeimHcAndMmio (\r
158 IN UINTN Address,\r
159 IN UINT8 Count,\r
160 IN VOID *AndData\r
161 )\r
162{\r
163 EFI_STATUS Status;\r
164 UINT64 Data;\r
165 UINT64 And;\r
166\r
167 Status = EmmcPeimHcRwMmio (Address, TRUE, Count, &Data);\r
168 if (EFI_ERROR (Status)) {\r
169 return Status;\r
170 }\r
171\r
172 if (Count == 1) {\r
173 And = *(UINT8*) AndData;\r
174 } else if (Count == 2) {\r
175 And = *(UINT16*) AndData;\r
176 } else if (Count == 4) {\r
177 And = *(UINT32*) AndData;\r
178 } else if (Count == 8) {\r
179 And = *(UINT64*) AndData;\r
180 } else {\r
181 return EFI_INVALID_PARAMETER;\r
182 }\r
183\r
184 Data &= And;\r
185 Status = EmmcPeimHcRwMmio (Address, FALSE, Count, &Data);\r
186\r
187 return Status;\r
188}\r
189\r
190/**\r
191 Wait for the value of the specified MMIO register set to the test value.\r
192\r
193 @param[in] Address The address of the mmio register to be checked.\r
194 @param[in] Count The width of the mmio register in bytes.\r
195 Must be 1, 2, 4 or 8 bytes.\r
196 @param[in] MaskValue The mask value of memory.\r
197 @param[in] TestValue The test value of memory.\r
198\r
199 @retval EFI_NOT_READY The MMIO register hasn't set to the expected value.\r
200 @retval EFI_SUCCESS The MMIO register has expected value.\r
201 @retval Others The MMIO operation fails.\r
202\r
203**/\r
204EFI_STATUS\r
205EFIAPI\r
206EmmcPeimHcCheckMmioSet (\r
207 IN UINTN Address,\r
208 IN UINT8 Count,\r
209 IN UINT64 MaskValue,\r
210 IN UINT64 TestValue\r
211 )\r
212{\r
213 EFI_STATUS Status;\r
214 UINT64 Value;\r
215\r
216 //\r
217 // Access PCI MMIO space to see if the value is the tested one.\r
218 //\r
219 Value = 0;\r
220 Status = EmmcPeimHcRwMmio (Address, TRUE, Count, &Value);\r
221 if (EFI_ERROR (Status)) {\r
222 return Status;\r
223 }\r
224\r
225 Value &= MaskValue;\r
226\r
227 if (Value == TestValue) {\r
228 return EFI_SUCCESS;\r
229 }\r
230\r
231 return EFI_NOT_READY;\r
232}\r
233\r
234/**\r
235 Wait for the value of the specified MMIO register set to the test value.\r
236\r
237 @param[in] Address The address of the mmio register to wait.\r
238 @param[in] Count The width of the mmio register in bytes.\r
239 Must be 1, 2, 4 or 8 bytes.\r
240 @param[in] MaskValue The mask value of memory.\r
241 @param[in] TestValue The test value of memory.\r
242 @param[in] Timeout The time out value for wait memory set, uses 1\r
243 microsecond as a unit.\r
244\r
245 @retval EFI_TIMEOUT The MMIO register hasn't expected value in timeout\r
246 range.\r
247 @retval EFI_SUCCESS The MMIO register has expected value.\r
248 @retval Others The MMIO operation fails.\r
249\r
250**/\r
251EFI_STATUS\r
252EFIAPI\r
253EmmcPeimHcWaitMmioSet (\r
254 IN UINTN Address,\r
255 IN UINT8 Count,\r
256 IN UINT64 MaskValue,\r
257 IN UINT64 TestValue,\r
258 IN UINT64 Timeout\r
259 )\r
260{\r
261 EFI_STATUS Status;\r
262 BOOLEAN InfiniteWait;\r
263\r
264 if (Timeout == 0) {\r
265 InfiniteWait = TRUE;\r
266 } else {\r
267 InfiniteWait = FALSE;\r
268 }\r
269\r
270 while (InfiniteWait || (Timeout > 0)) {\r
271 Status = EmmcPeimHcCheckMmioSet (\r
272 Address,\r
273 Count,\r
274 MaskValue,\r
275 TestValue\r
276 );\r
277 if (Status != EFI_NOT_READY) {\r
278 return Status;\r
279 }\r
280\r
281 //\r
282 // Stall for 1 microsecond.\r
283 //\r
284 MicroSecondDelay (1);\r
285\r
286 Timeout--;\r
287 }\r
288\r
289 return EFI_TIMEOUT;\r
290}\r
291\r
292/**\r
293 Software reset the specified EMMC host controller and enable all interrupts.\r
294\r
295 @param[in] Bar The mmio base address of the slot to be accessed.\r
296\r
297 @retval EFI_SUCCESS The software reset executes successfully.\r
298 @retval Others The software reset fails.\r
299\r
300**/\r
301EFI_STATUS\r
302EmmcPeimHcReset (\r
303 IN UINTN Bar\r
304 )\r
305{\r
306 EFI_STATUS Status;\r
307 UINT8 SwReset;\r
308\r
309 SwReset = 0xFF;\r
310 Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_SW_RST, FALSE, sizeof (SwReset), &SwReset);\r
311\r
312 if (EFI_ERROR (Status)) {\r
313 DEBUG ((EFI_D_ERROR, "EmmcPeimHcReset: write full 1 fails: %r\n", Status));\r
314 return Status;\r
315 }\r
316\r
317 Status = EmmcPeimHcWaitMmioSet (\r
318 Bar + EMMC_HC_SW_RST,\r
319 sizeof (SwReset),\r
320 0xFF,\r
321 0x00,\r
322 EMMC_TIMEOUT\r
323 );\r
324 if (EFI_ERROR (Status)) {\r
325 DEBUG ((EFI_D_INFO, "EmmcPeimHcReset: reset done with %r\n", Status));\r
326 return Status;\r
327 }\r
328 //\r
329 // Enable all interrupt after reset all.\r
330 //\r
331 Status = EmmcPeimHcEnableInterrupt (Bar);\r
332\r
333 return Status;\r
334}\r
335\r
336/**\r
337 Set all interrupt status bits in Normal and Error Interrupt Status Enable\r
338 register.\r
339\r
340 @param[in] Bar The mmio base address of the slot to be accessed.\r
341\r
342 @retval EFI_SUCCESS The operation executes successfully.\r
343 @retval Others The operation fails.\r
344\r
345**/\r
346EFI_STATUS\r
347EmmcPeimHcEnableInterrupt (\r
348 IN UINTN Bar\r
349 )\r
350{\r
351 EFI_STATUS Status;\r
352 UINT16 IntStatus;\r
353\r
354 //\r
355 // Enable all bits in Error Interrupt Status Enable Register\r
356 //\r
357 IntStatus = 0xFFFF;\r
358 Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_ERR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);\r
359 if (EFI_ERROR (Status)) {\r
360 return Status;\r
361 }\r
362 //\r
363 // Enable all bits in Normal Interrupt Status Enable Register\r
364 //\r
365 IntStatus = 0xFFFF;\r
366 Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_NOR_INT_STS_EN, FALSE, sizeof (IntStatus), &IntStatus);\r
367\r
368 return Status;\r
369}\r
370\r
371/**\r
372 Get the capability data from the specified slot.\r
373\r
374 @param[in] Bar The mmio base address of the slot to be accessed.\r
375 @param[out] Capability The buffer to store the capability data.\r
376\r
377 @retval EFI_SUCCESS The operation executes successfully.\r
378 @retval Others The operation fails.\r
379\r
380**/\r
381EFI_STATUS\r
382EmmcPeimHcGetCapability (\r
383 IN UINTN Bar,\r
384 OUT EMMC_HC_SLOT_CAP *Capability\r
385 )\r
386{\r
387 EFI_STATUS Status;\r
388 UINT64 Cap;\r
389\r
390 Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_CAP, TRUE, sizeof (Cap), &Cap);\r
391 if (EFI_ERROR (Status)) {\r
392 return Status;\r
393 }\r
394\r
395 CopyMem (Capability, &Cap, sizeof (Cap));\r
396\r
397 return EFI_SUCCESS;\r
398}\r
399\r
400/**\r
401 Detect whether there is a EMMC card attached at the specified EMMC host controller\r
402 slot.\r
403\r
404 Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.\r
405\r
406 @param[in] Bar The mmio base address of the slot to be accessed.\r
407\r
408 @retval EFI_SUCCESS There is a EMMC card attached.\r
409 @retval EFI_NO_MEDIA There is not a EMMC card attached.\r
410 @retval Others The detection fails.\r
411\r
412**/\r
413EFI_STATUS\r
414EmmcPeimHcCardDetect (\r
415 IN UINTN Bar\r
416 )\r
417{\r
418 EFI_STATUS Status;\r
419 UINT16 Data;\r
420 UINT32 PresentState;\r
421\r
422 //\r
423 // Check Normal Interrupt Status Register\r
424 //\r
425 Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_NOR_INT_STS, TRUE, sizeof (Data), &Data);\r
426 if (EFI_ERROR (Status)) {\r
427 return Status;\r
428 }\r
429\r
430 if ((Data & (BIT6 | BIT7)) != 0) {\r
431 //\r
432 // Clear BIT6 and BIT7 by writing 1 to these two bits if set.\r
433 //\r
434 Data &= BIT6 | BIT7;\r
435 Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_NOR_INT_STS, FALSE, sizeof (Data), &Data);\r
436 if (EFI_ERROR (Status)) {\r
437 return Status;\r
438 }\r
439 }\r
440\r
441 //\r
442 // Check Present State Register to see if there is a card presented.\r
443 //\r
444 Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_PRESENT_STATE, TRUE, sizeof (PresentState), &PresentState);\r
445 if (EFI_ERROR (Status)) {\r
446 return Status;\r
447 }\r
448\r
449 if ((PresentState & BIT16) != 0) {\r
450 return EFI_SUCCESS;\r
451 } else {\r
452 return EFI_NO_MEDIA;\r
453 }\r
454}\r
455\r
456/**\r
457 Stop EMMC card clock.\r
458\r
459 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.2 for details.\r
460\r
461 @param[in] Bar The mmio base address of the slot to be accessed.\r
462\r
463 @retval EFI_SUCCESS Succeed to stop EMMC clock.\r
464 @retval Others Fail to stop EMMC clock.\r
465\r
466**/\r
467EFI_STATUS\r
468EmmcPeimHcStopClock (\r
469 IN UINTN Bar\r
470 )\r
471{\r
472 EFI_STATUS Status;\r
473 UINT32 PresentState;\r
474 UINT16 ClockCtrl;\r
475\r
476 //\r
477 // Ensure no SD transactions are occurring on the SD Bus by\r
478 // waiting for Command Inhibit (DAT) and Command Inhibit (CMD)\r
479 // in the Present State register to be 0.\r
480 //\r
481 Status = EmmcPeimHcWaitMmioSet (\r
482 Bar + EMMC_HC_PRESENT_STATE,\r
483 sizeof (PresentState),\r
484 BIT0 | BIT1,\r
485 0,\r
486 EMMC_TIMEOUT\r
487 );\r
488 if (EFI_ERROR (Status)) {\r
489 return Status;\r
490 }\r
491\r
492 //\r
493 // Set SD Clock Enable in the Clock Control register to 0\r
494 //\r
495 ClockCtrl = (UINT16)~BIT2;\r
496 Status = EmmcPeimHcAndMmio (Bar + EMMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r
497\r
498 return Status;\r
499}\r
500\r
501/**\r
502 EMMC card clock supply.\r
503\r
504 Refer to SD Host Controller Simplified spec 3.0 Section 3.2.1 for details.\r
505\r
506 @param[in] Bar The mmio base address of the slot to be accessed.\r
507 @param[in] ClockFreq The max clock frequency to be set. The unit is KHz.\r
508\r
509 @retval EFI_SUCCESS The clock is supplied successfully.\r
510 @retval Others The clock isn't supplied successfully.\r
511\r
512**/\r
513EFI_STATUS\r
514EmmcPeimHcClockSupply (\r
515 IN UINTN Bar,\r
516 IN UINT64 ClockFreq\r
517 )\r
518{\r
519 EFI_STATUS Status;\r
520 EMMC_HC_SLOT_CAP Capability;\r
521 UINT32 BaseClkFreq;\r
522 UINT32 SettingFreq;\r
523 UINT32 Divisor;\r
524 UINT32 Remainder;\r
525 UINT16 ControllerVer;\r
526 UINT16 ClockCtrl;\r
527\r
528 //\r
529 // Calculate a divisor for SD clock frequency\r
530 //\r
531 Status = EmmcPeimHcGetCapability (Bar, &Capability);\r
532 if (EFI_ERROR (Status)) {\r
533 return Status;\r
534 }\r
535 ASSERT (Capability.BaseClkFreq != 0);\r
536\r
537 BaseClkFreq = Capability.BaseClkFreq;\r
cb9cb9e2
FT		 538\r
539 if (ClockFreq == 0) {\r
48555339
FT		 540 return EFI_INVALID_PARAMETER;\r
541 }\r
cb9cb9e2
FT		 542\r
543 if (ClockFreq > (BaseClkFreq * 1000)) {\r
544 ClockFreq = BaseClkFreq * 1000;\r
545 }\r
546\r
48555339
FT		 547 //\r
548 // Calculate the divisor of base frequency.\r
549 //\r
550 Divisor = 0;\r
551 SettingFreq = BaseClkFreq * 1000;\r
552 while (ClockFreq < SettingFreq) {\r
553 Divisor++;\r
554\r
555 SettingFreq = (BaseClkFreq * 1000) / (2 * Divisor);\r
556 Remainder = (BaseClkFreq * 1000) % (2 * Divisor);\r
557 if ((ClockFreq == SettingFreq) && (Remainder == 0)) {\r
558 break;\r
559 }\r
560 if ((ClockFreq == SettingFreq) && (Remainder != 0)) {\r
561 SettingFreq ++;\r
562 }\r
563 }\r
564\r
565 DEBUG ((EFI_D_INFO, "BaseClkFreq %dMHz Divisor %d ClockFreq %dKhz\n", BaseClkFreq, Divisor, ClockFreq));\r
566\r
567 Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_CTRL_VER, TRUE, sizeof (ControllerVer), &ControllerVer);\r
568 if (EFI_ERROR (Status)) {\r
569 return Status;\r
570 }\r
571 //\r
572 // Set SDCLK Frequency Select and Internal Clock Enable fields in Clock Control register.\r
573 //\r
574 if ((ControllerVer & 0xFF) == 2) {\r
575 ASSERT (Divisor <= 0x3FF);\r
576 ClockCtrl = ((Divisor & 0xFF) << 8) | ((Divisor & 0x300) >> 2);\r
577 } else if (((ControllerVer & 0xFF) == 0) || ((ControllerVer & 0xFF) == 1)) {\r
578 //\r
579 // Only the most significant bit can be used as divisor.\r
580 //\r
581 if (((Divisor - 1) & Divisor) != 0) {\r
582 Divisor = 1 << (HighBitSet32 (Divisor) + 1);\r
583 }\r
584 ASSERT (Divisor <= 0x80);\r
585 ClockCtrl = (Divisor & 0xFF) << 8;\r
586 } else {\r
587 DEBUG ((EFI_D_ERROR, "Unknown SD Host Controller Spec version [0x%x]!!!\n", ControllerVer));\r
588 return EFI_UNSUPPORTED;\r
589 }\r
590\r
591 //\r
592 // Stop bus clock at first\r
593 //\r
594 Status = EmmcPeimHcStopClock (Bar);\r
595 if (EFI_ERROR (Status)) {\r
596 return Status;\r
597 }\r
598\r
599 //\r
600 // Supply clock frequency with specified divisor\r
601 //\r
602 ClockCtrl |= BIT0;\r
603 Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_CLOCK_CTRL, FALSE, sizeof (ClockCtrl), &ClockCtrl);\r
604 if (EFI_ERROR (Status)) {\r
605 DEBUG ((EFI_D_ERROR, "Set SDCLK Frequency Select and Internal Clock Enable fields fails\n"));\r
606 return Status;\r
607 }\r
608\r
609 //\r
610 // Wait Internal Clock Stable in the Clock Control register to be 1\r
611 //\r
612 Status = EmmcPeimHcWaitMmioSet (\r
613 Bar + EMMC_HC_CLOCK_CTRL,\r
614 sizeof (ClockCtrl),\r
615 BIT1,\r
616 BIT1,\r
617 EMMC_TIMEOUT\r
618 );\r
619 if (EFI_ERROR (Status)) {\r
620 return Status;\r
621 }\r
622\r
623 //\r
624 // Set SD Clock Enable in the Clock Control register to 1\r
625 //\r
626 ClockCtrl = BIT2;\r
627 Status = EmmcPeimHcOrMmio (Bar + EMMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r
628\r
629 return Status;\r
630}\r
631\r
632/**\r
633 EMMC bus power control.\r
634\r
635 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r
636\r
637 @param[in] Bar The mmio base address of the slot to be accessed.\r
638 @param[in] PowerCtrl The value setting to the power control register.\r
639\r
640 @retval TRUE There is a EMMC card attached.\r
641 @retval FALSE There is no a EMMC card attached.\r
642\r
643**/\r
644EFI_STATUS\r
645EmmcPeimHcPowerControl (\r
646 IN UINTN Bar,\r
647 IN UINT8 PowerCtrl\r
648 )\r
649{\r
650 EFI_STATUS Status;\r
651\r
652 //\r
653 // Clr SD Bus Power\r
654 //\r
655 PowerCtrl &= (UINT8)~BIT0;\r
656 Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);\r
657 if (EFI_ERROR (Status)) {\r
658 return Status;\r
659 }\r
660\r
661 //\r
662 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register\r
663 //\r
664 PowerCtrl |= BIT0;\r
665 Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_POWER_CTRL, FALSE, sizeof (PowerCtrl), &PowerCtrl);\r
666\r
667 return Status;\r
668}\r
669\r
670/**\r
671 Set the EMMC bus width.\r
672\r
673 Refer to SD Host Controller Simplified spec 3.0 Section 3.4 for details.\r
674\r
675 @param[in] Bar The mmio base address of the slot to be accessed.\r
676 @param[in] BusWidth The bus width used by the EMMC device, it must be 1, 4 or 8.\r
677\r
678 @retval EFI_SUCCESS The bus width is set successfully.\r
679 @retval Others The bus width isn't set successfully.\r
680\r
681**/\r
682EFI_STATUS\r
683EmmcPeimHcSetBusWidth (\r
684 IN UINTN Bar,\r
685 IN UINT16 BusWidth\r
686 )\r
687{\r
688 EFI_STATUS Status;\r
689 UINT8 HostCtrl1;\r
690\r
691 if (BusWidth == 1) {\r
692 HostCtrl1 = (UINT8)~(BIT5 | BIT1);\r
693 Status = EmmcPeimHcAndMmio (Bar + EMMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
694 } else if (BusWidth == 4) {\r
695 Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);\r
696 if (EFI_ERROR (Status)) {\r
697 return Status;\r
698 }\r
699 HostCtrl1 |= BIT1;\r
700 HostCtrl1 &= (UINT8)~BIT5;\r
701 Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);\r
702 } else if (BusWidth == 8) {\r
703 Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_HOST_CTRL1, TRUE, sizeof (HostCtrl1), &HostCtrl1);\r
704 if (EFI_ERROR (Status)) {\r
705 return Status;\r
706 }\r
707 HostCtrl1 &= (UINT8)~BIT1;\r
708 HostCtrl1 |= BIT5;\r
709 Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_HOST_CTRL1, FALSE, sizeof (HostCtrl1), &HostCtrl1);\r
710 } else {\r
711 ASSERT (FALSE);\r
712 return EFI_INVALID_PARAMETER;\r
713 }\r
714\r
715 return Status;\r
716}\r
717\r
718/**\r
719 Supply EMMC card with lowest clock frequency at initialization.\r
720\r
721 @param[in] Bar The mmio base address of the slot to be accessed.\r
722\r
723 @retval EFI_SUCCESS The clock is supplied successfully.\r
724 @retval Others The clock isn't supplied successfully.\r
725\r
726**/\r
727EFI_STATUS\r
728EmmcPeimHcInitClockFreq (\r
729 IN UINTN Bar\r
730 )\r
731{\r
732 EFI_STATUS Status;\r
733 EMMC_HC_SLOT_CAP Capability;\r
734 UINT32 InitFreq;\r
735\r
736 //\r
737 // Calculate a divisor for SD clock frequency\r
738 //\r
739 Status = EmmcPeimHcGetCapability (Bar, &Capability);\r
740 if (EFI_ERROR (Status)) {\r
741 return Status;\r
742 }\r
743\r
744 if (Capability.BaseClkFreq == 0) {\r
745 //\r
746 // Don't support get Base Clock Frequency information via another method\r
747 //\r
748 return EFI_UNSUPPORTED;\r
749 }\r
750 //\r
751 // Supply 400KHz clock frequency at initialization phase.\r
752 //\r
753 InitFreq = 400;\r
754 Status = EmmcPeimHcClockSupply (Bar, InitFreq);\r
755 return Status;\r
756}\r
757\r
758/**\r
759 Supply EMMC card with maximum voltage at initialization.\r
760\r
761 Refer to SD Host Controller Simplified spec 3.0 Section 3.3 for details.\r
762\r
763 @param[in] Bar The mmio base address of the slot to be accessed.\r
764\r
765 @retval EFI_SUCCESS The voltage is supplied successfully.\r
766 @retval Others The voltage isn't supplied successfully.\r
767\r
768**/\r
769EFI_STATUS\r
770EmmcPeimHcInitPowerVoltage (\r
771 IN UINTN Bar\r
772 )\r
773{\r
774 EFI_STATUS Status;\r
775 EMMC_HC_SLOT_CAP Capability;\r
776 UINT8 MaxVoltage;\r
777 UINT8 HostCtrl2;\r
778\r
779 //\r
780 // Get the support voltage of the Host Controller\r
781 //\r
782 Status = EmmcPeimHcGetCapability (Bar, &Capability);\r
783 if (EFI_ERROR (Status)) {\r
784 return Status;\r
785 }\r
786 //\r
787 // Calculate supported maximum voltage according to SD Bus Voltage Select\r
788 //\r
789 if (Capability.Voltage33 != 0) {\r
790 //\r
791 // Support 3.3V\r
792 //\r
793 MaxVoltage = 0x0E;\r
794 } else if (Capability.Voltage30 != 0) {\r
795 //\r
796 // Support 3.0V\r
797 //\r
798 MaxVoltage = 0x0C;\r
799 } else if (Capability.Voltage18 != 0) {\r
800 //\r
801 // Support 1.8V\r
802 //\r
803 MaxVoltage = 0x0A;\r
804 HostCtrl2 = BIT3;\r
805 Status = EmmcPeimHcOrMmio (Bar + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
806 if (EFI_ERROR (Status)) {\r
807 return Status;\r
808 }\r
809 MicroSecondDelay (5000);\r
810 } else {\r
811 ASSERT (FALSE);\r
812 return EFI_DEVICE_ERROR;\r
813 }\r
814\r
815 //\r
816 // Set SD Bus Voltage Select and SD Bus Power fields in Power Control Register\r
817 //\r
818 Status = EmmcPeimHcPowerControl (Bar, MaxVoltage);\r
819\r
820 return Status;\r
821}\r
822\r
823/**\r
824 Initialize the Timeout Control register with most conservative value at initialization.\r
825\r
826 Refer to SD Host Controller Simplified spec 3.0 Section 2.2.15 for details.\r
827\r
828 @param[in] Bar The mmio base address of the slot to be accessed.\r
829\r
830 @retval EFI_SUCCESS The timeout control register is configured successfully.\r
831 @retval Others The timeout control register isn't configured successfully.\r
832\r
833**/\r
834EFI_STATUS\r
835EmmcPeimHcInitTimeoutCtrl (\r
836 IN UINTN Bar\r
837 )\r
838{\r
839 EFI_STATUS Status;\r
840 UINT8 Timeout;\r
841\r
842 Timeout = 0x0E;\r
843 Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_TIMEOUT_CTRL, FALSE, sizeof (Timeout), &Timeout);\r
844\r
845 return Status;\r
846}\r
847\r
848/**\r
849 Initial EMMC host controller with lowest clock frequency, max power and max timeout value\r
850 at initialization.\r
851\r
852 @param[in] Bar The mmio base address of the slot to be accessed.\r
853\r
854 @retval EFI_SUCCESS The host controller is initialized successfully.\r
855 @retval Others The host controller isn't initialized successfully.\r
856\r
857**/\r
858EFI_STATUS\r
859EmmcPeimHcInitHost (\r
860 IN UINTN Bar\r
861 )\r
862{\r
863 EFI_STATUS Status;\r
864\r
865 Status = EmmcPeimHcInitClockFreq (Bar);\r
866 if (EFI_ERROR (Status)) {\r
867 return Status;\r
868 }\r
869\r
870 Status = EmmcPeimHcInitPowerVoltage (Bar);\r
871 if (EFI_ERROR (Status)) {\r
872 return Status;\r
873 }\r
874\r
875 Status = EmmcPeimHcInitTimeoutCtrl (Bar);\r
876 return Status;\r
877}\r
878\r
879/**\r
880 Turn on/off LED.\r
881\r
882 @param[in] Bar The mmio base address of the slot to be accessed.\r
883 @param[in] On The boolean to turn on/off LED.\r
884\r
885 @retval EFI_SUCCESS The LED is turned on/off successfully.\r
886 @retval Others The LED isn't turned on/off successfully.\r
887\r
888**/\r
889EFI_STATUS\r
890EmmcPeimHcLedOnOff (\r
891 IN UINTN Bar,\r
892 IN BOOLEAN On\r
893 )\r
894{\r
895 EFI_STATUS Status;\r
896 UINT8 HostCtrl1;\r
897\r
898 if (On) {\r
899 HostCtrl1 = BIT0;\r
900 Status = EmmcPeimHcOrMmio (Bar + EMMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
901 } else {\r
902 HostCtrl1 = (UINT8)~BIT0;\r
903 Status = EmmcPeimHcAndMmio (Bar + EMMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
904 }\r
905\r
906 return Status;\r
907}\r
908\r
909/**\r
910 Build ADMA descriptor table for transfer.\r
911\r
912 Refer to SD Host Controller Simplified spec 3.0 Section 1.13 for details.\r
913\r
914 @param[in] Trb The pointer to the EMMC_TRB instance.\r
915\r
916 @retval EFI_SUCCESS The ADMA descriptor table is created successfully.\r
917 @retval Others The ADMA descriptor table isn't created successfully.\r
918\r
919**/\r
920EFI_STATUS\r
921BuildAdmaDescTable (\r
922 IN EMMC_TRB *Trb\r
923 )\r
924{\r
925 EFI_PHYSICAL_ADDRESS Data;\r
926 UINT64 DataLen;\r
927 UINT64 Entries;\r
928 UINT32 Index;\r
929 UINT64 Remaining;\r
930 UINT32 Address;\r
931\r
932 Data = (EFI_PHYSICAL_ADDRESS)(UINTN)Trb->Data;\r
933 DataLen = Trb->DataLen;\r
934 //\r
935 // Only support 32bit ADMA Descriptor Table\r
936 //\r
937 if ((Data >= 0x100000000ul) || ((Data + DataLen) > 0x100000000ul)) {\r
938 return EFI_INVALID_PARAMETER;\r
939 }\r
940 //\r
941 // Address field shall be set on 32-bit boundary (Lower 2-bit is always set to 0)\r
942 // for 32-bit address descriptor table.\r
943 //\r
944 if ((Data & (BIT0 | BIT1)) != 0) {\r
945 DEBUG ((EFI_D_INFO, "The buffer [0x%x] to construct ADMA desc is not aligned to 4 bytes boundary!\n", Data));\r
946 }\r
947\r
948 Entries = DivU64x32 ((DataLen + ADMA_MAX_DATA_PER_LINE - 1), ADMA_MAX_DATA_PER_LINE);\r
949\r
950 Trb->AdmaDescSize = (UINTN)MultU64x32 (Entries, sizeof (EMMC_HC_ADMA_DESC_LINE));\r
951 Trb->AdmaDesc = EmmcPeimAllocateMem (Trb->Slot->Private->Pool, Trb->AdmaDescSize);\r
952 if (Trb->AdmaDesc == NULL) {\r
953 return EFI_OUT_OF_RESOURCES;\r
954 }\r
955\r
956 Remaining = DataLen;\r
957 Address = (UINT32)Data;\r
958 for (Index = 0; Index < Entries; Index++) {\r
959 if (Remaining <= ADMA_MAX_DATA_PER_LINE) {\r
960 Trb->AdmaDesc[Index].Valid = 1;\r
961 Trb->AdmaDesc[Index].Act = 2;\r
962 Trb->AdmaDesc[Index].Length = (UINT16)Remaining;\r
963 Trb->AdmaDesc[Index].Address = Address;\r
964 break;\r
965 } else {\r
966 Trb->AdmaDesc[Index].Valid = 1;\r
967 Trb->AdmaDesc[Index].Act = 2;\r
968 Trb->AdmaDesc[Index].Length = 0;\r
969 Trb->AdmaDesc[Index].Address = Address;\r
970 }\r
971\r
972 Remaining -= ADMA_MAX_DATA_PER_LINE;\r
973 Address += ADMA_MAX_DATA_PER_LINE;\r
974 }\r
975\r
976 //\r
977 // Set the last descriptor line as end of descriptor table\r
978 //\r
979 Trb->AdmaDesc[Index].End = 1;\r
980 return EFI_SUCCESS;\r
981}\r
982\r
983/**\r
984 Create a new TRB for the EMMC cmd request.\r
985\r
986 @param[in] Slot The slot number of the EMMC card to send the command to.\r
987 @param[in] Packet A pointer to the SD command data structure.\r
988\r
989 @return Created Trb or NULL.\r
990\r
991**/\r
992EMMC_TRB *\r
993EmmcPeimCreateTrb (\r
994 IN EMMC_PEIM_HC_SLOT *Slot,\r
995 IN EMMC_COMMAND_PACKET *Packet\r
996 )\r
997{\r
998 EMMC_TRB *Trb;\r
999 EFI_STATUS Status;\r
1000 EMMC_HC_SLOT_CAP Capability;\r
1001\r
1002 //\r
1003 // Calculate a divisor for SD clock frequency\r
1004 //\r
1005 Status = EmmcPeimHcGetCapability (Slot->EmmcHcBase, &Capability);\r
1006 if (EFI_ERROR (Status)) {\r
1007 return NULL;\r
1008 }\r
1009\r
1010 Trb = EmmcPeimAllocateMem (Slot->Private->Pool, sizeof (EMMC_TRB));\r
1011 if (Trb == NULL) {\r
1012 return NULL;\r
1013 }\r
1014\r
1015 Trb->Slot = Slot;\r
1016 Trb->BlockSize = 0x200;\r
1017 Trb->Packet = Packet;\r
1018 Trb->Timeout = Packet->Timeout;\r
1019\r
1020 if ((Packet->InTransferLength != 0) && (Packet->InDataBuffer != NULL)) {\r
1021 Trb->Data = Packet->InDataBuffer;\r
1022 Trb->DataLen = Packet->InTransferLength;\r
1023 Trb->Read = TRUE;\r
1024 } else if ((Packet->OutTransferLength != 0) && (Packet->OutDataBuffer != NULL)) {\r
1025 Trb->Data = Packet->OutDataBuffer;\r
1026 Trb->DataLen = Packet->OutTransferLength;\r
1027 Trb->Read = FALSE;\r
1028 } else if ((Packet->InTransferLength == 0) && (Packet->OutTransferLength == 0)) {\r
1029 Trb->Data = NULL;\r
1030 Trb->DataLen = 0;\r
1031 } else {\r
1032 goto Error;\r
1033 }\r
1034\r
1035 if ((Trb->DataLen % Trb->BlockSize) != 0) {\r
1036 if (Trb->DataLen < Trb->BlockSize) {\r
1037 Trb->BlockSize = (UINT16)Trb->DataLen;\r
1038 }\r
1039 }\r
1040\r
1041 if (Trb->DataLen == 0) {\r
1042 Trb->Mode = EmmcNoData;\r
1043 } else if (Capability.Adma2 != 0) {\r
1044 Trb->Mode = EmmcAdmaMode;\r
1045 Status = BuildAdmaDescTable (Trb);\r
1046 if (EFI_ERROR (Status)) {\r
1047 goto Error;\r
1048 }\r
1049 } else if (Capability.Sdma != 0) {\r
1050 Trb->Mode = EmmcSdmaMode;\r
1051 } else {\r
1052 Trb->Mode = EmmcPioMode;\r
1053 }\r
1054\r
1055 return Trb;\r
1056\r
1057Error:\r
1058 EmmcPeimFreeTrb (Trb);\r
1059 return NULL;\r
1060}\r
1061\r
1062/**\r
1063 Free the resource used by the TRB.\r
1064\r
1065 @param[in] Trb The pointer to the EMMC_TRB instance.\r
1066\r
1067**/\r
1068VOID\r
1069EmmcPeimFreeTrb (\r
1070 IN EMMC_TRB *Trb\r
1071 )\r
1072{\r
1073 if ((Trb != NULL) && (Trb->AdmaDesc != NULL)) {\r
1074 EmmcPeimFreeMem (Trb->Slot->Private->Pool, Trb->AdmaDesc, Trb->AdmaDescSize);\r
1075 }\r
1076\r
1077 if (Trb != NULL) {\r
1078 EmmcPeimFreeMem (Trb->Slot->Private->Pool, Trb, sizeof (EMMC_TRB));\r
1079 }\r
1080 return;\r
1081}\r
1082\r
1083/**\r
1084 Check if the env is ready for execute specified TRB.\r
1085\r
1086 @param[in] Bar The mmio base address of the slot to be accessed.\r
1087 @param[in] Trb The pointer to the EMMC_TRB instance.\r
1088\r
1089 @retval EFI_SUCCESS The env is ready for TRB execution.\r
1090 @retval EFI_NOT_READY The env is not ready for TRB execution.\r
1091 @retval Others Some erros happen.\r
1092\r
1093**/\r
1094EFI_STATUS\r
1095EmmcPeimCheckTrbEnv (\r
1096 IN UINTN Bar,\r
1097 IN EMMC_TRB *Trb\r
1098 )\r
1099{\r
1100 EFI_STATUS Status;\r
1101 EMMC_COMMAND_PACKET *Packet;\r
1102 UINT32 PresentState;\r
1103\r
1104 Packet = Trb->Packet;\r
1105\r
1106 if ((Packet->EmmcCmdBlk->CommandType == EmmcCommandTypeAdtc) ||\r
1107 (Packet->EmmcCmdBlk->ResponseType == EmmcResponceTypeR1b) ||\r
1108 (Packet->EmmcCmdBlk->ResponseType == EmmcResponceTypeR5b)) {\r
1109 //\r
1110 // Wait Command Inhibit (CMD) and Command Inhibit (DAT) in\r
1111 // the Present State register to be 0\r
1112 //\r
1113 PresentState = BIT0 | BIT1;\r
1114 if (Packet->EmmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK) {\r
1115 PresentState = BIT0;\r
1116 }\r
1117 } else {\r
1118 //\r
1119 // Wait Command Inhibit (CMD) in the Present State register\r
1120 // to be 0\r
1121 //\r
1122 PresentState = BIT0;\r
1123 }\r
1124\r
1125 Status = EmmcPeimHcCheckMmioSet (\r
1126 Bar + EMMC_HC_PRESENT_STATE,\r
1127 sizeof (PresentState),\r
1128 PresentState,\r
1129 0\r
1130 );\r
1131\r
1132 return Status;\r
1133}\r
1134\r
1135/**\r
1136 Wait for the env to be ready for execute specified TRB.\r
1137\r
1138 @param[in] Bar The mmio base address of the slot to be accessed.\r
1139 @param[in] Trb The pointer to the EMMC_TRB instance.\r
1140\r
1141 @retval EFI_SUCCESS The env is ready for TRB execution.\r
1142 @retval EFI_TIMEOUT The env is not ready for TRB execution in time.\r
1143 @retval Others Some erros happen.\r
1144\r
1145**/\r
1146EFI_STATUS\r
1147EmmcPeimWaitTrbEnv (\r
1148 IN UINTN Bar,\r
1149 IN EMMC_TRB *Trb\r
1150 )\r
1151{\r
1152 EFI_STATUS Status;\r
1153 EMMC_COMMAND_PACKET *Packet;\r
1154 UINT64 Timeout;\r
1155 BOOLEAN InfiniteWait;\r
1156\r
1157 //\r
1158 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register\r
1159 //\r
1160 Packet = Trb->Packet;\r
1161 Timeout = Packet->Timeout;\r
1162 if (Timeout == 0) {\r
1163 InfiniteWait = TRUE;\r
1164 } else {\r
1165 InfiniteWait = FALSE;\r
1166 }\r
1167\r
1168 while (InfiniteWait || (Timeout > 0)) {\r
1169 //\r
1170 // Check Trb execution result by reading Normal Interrupt Status register.\r
1171 //\r
1172 Status = EmmcPeimCheckTrbEnv (Bar, Trb);\r
1173 if (Status != EFI_NOT_READY) {\r
1174 return Status;\r
1175 }\r
1176 //\r
1177 // Stall for 1 microsecond.\r
1178 //\r
1179 MicroSecondDelay (1);\r
1180\r
1181 Timeout--;\r
1182 }\r
1183\r
1184 return EFI_TIMEOUT;\r
1185}\r
1186\r
1187/**\r
1188 Execute the specified TRB.\r
1189\r
1190 @param[in] Bar The mmio base address of the slot to be accessed.\r
1191 @param[in] Trb The pointer to the EMMC_TRB instance.\r
1192\r
1193 @retval EFI_SUCCESS The TRB is sent to host controller successfully.\r
1194 @retval Others Some erros happen when sending this request to the host controller.\r
1195\r
1196**/\r
1197EFI_STATUS\r
1198EmmcPeimExecTrb (\r
1199 IN UINTN Bar,\r
1200 IN EMMC_TRB *Trb\r
1201 )\r
1202{\r
1203 EFI_STATUS Status;\r
1204 EMMC_COMMAND_PACKET *Packet;\r
1205 UINT16 Cmd;\r
1206 UINT16 IntStatus;\r
1207 UINT32 Argument;\r
1208 UINT16 BlkCount;\r
1209 UINT16 BlkSize;\r
1210 UINT16 TransMode;\r
1211 UINT8 HostCtrl1;\r
1212 UINT32 SdmaAddr;\r
1213 UINT64 AdmaAddr;\r
1214\r
1215 Packet = Trb->Packet;\r
1216 //\r
1217 // Clear all bits in Error Interrupt Status Register\r
1218 //\r
1219 IntStatus = 0xFFFF;\r
1220 Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_ERR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);\r
1221 if (EFI_ERROR (Status)) {\r
1222 return Status;\r
1223 }\r
1224 //\r
1225 // Clear all bits in Normal Interrupt Status Register\r
1226 //\r
1227 IntStatus = 0xFFFF;\r
1228 Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_NOR_INT_STS, FALSE, sizeof (IntStatus), &IntStatus);\r
1229 if (EFI_ERROR (Status)) {\r
1230 return Status;\r
1231 }\r
1232 //\r
1233 // Set Host Control 1 register DMA Select field\r
1234 //\r
1235 if (Trb->Mode == EmmcAdmaMode) {\r
1236 HostCtrl1 = BIT4;\r
1237 Status = EmmcPeimHcOrMmio (Bar + EMMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
1238 if (EFI_ERROR (Status)) {\r
1239 return Status;\r
1240 }\r
1241 }\r
1242\r
1243 EmmcPeimHcLedOnOff (Bar, TRUE);\r
1244\r
1245 if (Trb->Mode == EmmcSdmaMode) {\r
1246 if ((UINT64)(UINTN)Trb->Data >= 0x100000000ul) {\r
1247 return EFI_INVALID_PARAMETER;\r
1248 }\r
1249\r
1250 SdmaAddr = (UINT32)(UINTN)Trb->Data;\r
1251 Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_SDMA_ADDR, FALSE, sizeof (SdmaAddr), &SdmaAddr);\r
1252 if (EFI_ERROR (Status)) {\r
1253 return Status;\r
1254 }\r
1255 } else if (Trb->Mode == EmmcAdmaMode) {\r
1256 AdmaAddr = (UINT64)(UINTN)Trb->AdmaDesc;\r
1257 Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr);\r
1258 if (EFI_ERROR (Status)) {\r
1259 return Status;\r
1260 }\r
1261 }\r
1262\r
1263 BlkSize = Trb->BlockSize;\r
1264 if (Trb->Mode == EmmcSdmaMode) {\r
1265 //\r
1266 // Set SDMA boundary to be 512K bytes.\r
1267 //\r
1268 BlkSize |= 0x7000;\r
1269 }\r
1270\r
1271 Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_BLK_SIZE, FALSE, sizeof (BlkSize), &BlkSize);\r
1272 if (EFI_ERROR (Status)) {\r
1273 return Status;\r
1274 }\r
1275\r
1276 BlkCount = (UINT16)(Trb->DataLen / Trb->BlockSize);\r
1277 Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_BLK_COUNT, FALSE, sizeof (BlkCount), &BlkCount);\r
1278 if (EFI_ERROR (Status)) {\r
1279 return Status;\r
1280 }\r
1281\r
1282 Argument = Packet->EmmcCmdBlk->CommandArgument;\r
1283 Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_ARG1, FALSE, sizeof (Argument), &Argument);\r
1284 if (EFI_ERROR (Status)) {\r
1285 return Status;\r
1286 }\r
1287\r
1288 TransMode = 0;\r
1289 if (Trb->Mode != EmmcNoData) {\r
1290 if (Trb->Mode != EmmcPioMode) {\r
1291 TransMode |= BIT0;\r
1292 }\r
1293 if (Trb->Read) {\r
1294 TransMode |= BIT4;\r
1295 }\r
1296 if (BlkCount != 0) {\r
1297 TransMode |= BIT5 | BIT1;\r
1298 }\r
1299 }\r
1300\r
1301 Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_TRANS_MOD, FALSE, sizeof (TransMode), &TransMode);\r
1302 if (EFI_ERROR (Status)) {\r
1303 return Status;\r
1304 }\r
1305\r
1306 Cmd = (UINT16)LShiftU64(Packet->EmmcCmdBlk->CommandIndex, 8);\r
1307 if (Packet->EmmcCmdBlk->CommandType == EmmcCommandTypeAdtc) {\r
1308 Cmd |= BIT5;\r
1309 }\r
1310 //\r
1311 // Convert ResponseType to value\r
1312 //\r
1313 if (Packet->EmmcCmdBlk->CommandType != EmmcCommandTypeBc) {\r
1314 switch (Packet->EmmcCmdBlk->ResponseType) {\r
1315 case EmmcResponceTypeR1:\r
1316 case EmmcResponceTypeR5:\r
1317 case EmmcResponceTypeR6:\r
1318 case EmmcResponceTypeR7:\r
1319 Cmd |= (BIT1 | BIT3 | BIT4);\r
1320 break;\r
1321 case EmmcResponceTypeR2:\r
1322 Cmd |= (BIT0 | BIT3);\r
1323 break;\r
1324 case EmmcResponceTypeR3:\r
1325 case EmmcResponceTypeR4:\r
1326 Cmd |= BIT1;\r
1327 break;\r
1328 case EmmcResponceTypeR1b:\r
1329 case EmmcResponceTypeR5b:\r
1330 Cmd |= (BIT0 | BIT1 | BIT3 | BIT4);\r
1331 break;\r
1332 default:\r
1333 ASSERT (FALSE);\r
1334 break;\r
1335 }\r
1336 }\r
1337 //\r
1338 // Execute cmd\r
1339 //\r
1340 Status = EmmcPeimHcRwMmio (Bar + EMMC_HC_COMMAND, FALSE, sizeof (Cmd), &Cmd);\r
1341 return Status;\r
1342}\r
1343\r
1344/**\r
1345 Check the TRB execution result.\r
1346\r
1347 @param[in] Bar The mmio base address of the slot to be accessed.\r
1348 @param[in] Trb The pointer to the EMMC_TRB instance.\r
1349\r
1350 @retval EFI_SUCCESS The TRB is executed successfully.\r
1351 @retval EFI_NOT_READY The TRB is not completed for execution.\r
1352 @retval Others Some erros happen when executing this request.\r
1353\r
1354**/\r
1355EFI_STATUS\r
1356EmmcPeimCheckTrbResult (\r
1357 IN UINTN Bar,\r
1358 IN EMMC_TRB *Trb\r
1359 )\r
1360{\r
1361 EFI_STATUS Status;\r
1362 EMMC_COMMAND_PACKET *Packet;\r
1363 UINT16 IntStatus;\r
1364 UINT32 Response[4];\r
1365 UINT32 SdmaAddr;\r
1366 UINT8 Index;\r
1367 UINT8 SwReset;\r
1368\r
1369 SwReset = 0;\r
1370 Packet = Trb->Packet;\r
1371 //\r
1372 // Check Trb execution result by reading Normal Interrupt Status register.\r
1373 //\r
1374 Status = EmmcPeimHcRwMmio (\r
1375 Bar + EMMC_HC_NOR_INT_STS,\r
1376 TRUE,\r
1377 sizeof (IntStatus),\r
1378 &IntStatus\r
1379 );\r
1380 if (EFI_ERROR (Status)) {\r
1381 goto Done;\r
1382 }\r
1383 //\r
1384 // Check Transfer Complete bit is set or not.\r
1385 //\r
1386 if ((IntStatus & BIT1) == BIT1) {\r
1387 if ((IntStatus & BIT15) == BIT15) {\r
1388 //\r
1389 // Read Error Interrupt Status register to check if the error is\r
1390 // Data Timeout Error.\r
1391 // If yes, treat it as success as Transfer Complete has higher\r
1392 // priority than Data Timeout Error.\r
1393 //\r
1394 Status = EmmcPeimHcRwMmio (\r
1395 Bar + EMMC_HC_ERR_INT_STS,\r
1396 TRUE,\r
1397 sizeof (IntStatus),\r
1398 &IntStatus\r
1399 );\r
1400 if (!EFI_ERROR (Status)) {\r
1401 if ((IntStatus & BIT4) == BIT4) {\r
1402 Status = EFI_SUCCESS;\r
1403 } else {\r
1404 Status = EFI_DEVICE_ERROR;\r
1405 }\r
1406 }\r
1407 }\r
1408\r
1409 goto Done;\r
1410 }\r
1411 //\r
1412 // Check if there is a error happened during cmd execution.\r
1413 // If yes, then do error recovery procedure to follow SD Host Controller\r
1414 // Simplified Spec 3.0 section 3.10.1.\r
1415 //\r
1416 if ((IntStatus & BIT15) == BIT15) {\r
1417 Status = EmmcPeimHcRwMmio (\r
1418 Bar + EMMC_HC_ERR_INT_STS,\r
1419 TRUE,\r
1420 sizeof (IntStatus),\r
1421 &IntStatus\r
1422 );\r
1423 if (EFI_ERROR (Status)) {\r
1424 goto Done;\r
1425 }\r
1426\r
1427 if ((IntStatus & 0x0F) != 0) {\r
1428 SwReset |= BIT1;\r
1429 }\r
1430 if ((IntStatus & 0xF0) != 0) {\r
1431 SwReset |= BIT2;\r
1432 }\r
1433\r
1434 Status = EmmcPeimHcRwMmio (\r
1435 Bar + EMMC_HC_SW_RST,\r
1436 FALSE,\r
1437 sizeof (SwReset),\r
1438 &SwReset\r
1439 );\r
1440 if (EFI_ERROR (Status)) {\r
1441 goto Done;\r
1442 }\r
1443 Status = EmmcPeimHcWaitMmioSet (\r
1444 Bar + EMMC_HC_SW_RST,\r
1445 sizeof (SwReset),\r
1446 0xFF,\r
1447 0,\r
1448 EMMC_TIMEOUT\r
1449 );\r
1450 if (EFI_ERROR (Status)) {\r
1451 goto Done;\r
1452 }\r
1453\r
1454 Status = EFI_DEVICE_ERROR;\r
1455 goto Done;\r
1456 }\r
1457 //\r
1458 // Check if DMA interrupt is signalled for the SDMA transfer.\r
1459 //\r
1460 if ((Trb->Mode == EmmcSdmaMode) && ((IntStatus & BIT3) == BIT3)) {\r
1461 //\r
1462 // Clear DMA interrupt bit.\r
1463 //\r
1464 IntStatus = BIT3;\r
1465 Status = EmmcPeimHcRwMmio (\r
1466 Bar + EMMC_HC_NOR_INT_STS,\r
1467 FALSE,\r
1468 sizeof (IntStatus),\r
1469 &IntStatus\r
1470 );\r
1471 if (EFI_ERROR (Status)) {\r
1472 goto Done;\r
1473 }\r
1474 //\r
1475 // Update SDMA Address register.\r
1476 //\r
1477 SdmaAddr = EMMC_SDMA_ROUND_UP ((UINT32)(UINTN)Trb->Data, EMMC_SDMA_BOUNDARY);\r
1478 Status = EmmcPeimHcRwMmio (\r
1479 Bar + EMMC_HC_SDMA_ADDR,\r
1480 FALSE,\r
1481 sizeof (UINT32),\r
1482 &SdmaAddr\r
1483 );\r
1484 if (EFI_ERROR (Status)) {\r
1485 goto Done;\r
1486 }\r
1487 Trb->Data = (VOID*)(UINTN)SdmaAddr;\r
1488 }\r
1489\r
1490 if ((Packet->EmmcCmdBlk->CommandType != EmmcCommandTypeAdtc) &&\r
1491 (Packet->EmmcCmdBlk->ResponseType != EmmcResponceTypeR1b) &&\r
1492 (Packet->EmmcCmdBlk->ResponseType != EmmcResponceTypeR5b)) {\r
1493 if ((IntStatus & BIT0) == BIT0) {\r
1494 Status = EFI_SUCCESS;\r
1495 goto Done;\r
1496 }\r
1497 }\r
1498\r
1499 if (Packet->EmmcCmdBlk->CommandIndex == EMMC_SEND_TUNING_BLOCK) {\r
1500 Status = EFI_SUCCESS;\r
1501 goto Done;\r
1502 }\r
1503\r
1504 Status = EFI_NOT_READY;\r
1505Done:\r
1506 //\r
1507 // Get response data when the cmd is executed successfully.\r
1508 //\r
1509 if (!EFI_ERROR (Status)) {\r
1510 if (Packet->EmmcCmdBlk->CommandType != EmmcCommandTypeBc) {\r
1511 for (Index = 0; Index < 4; Index++) {\r
1512 Status = EmmcPeimHcRwMmio (\r
1513 Bar + EMMC_HC_RESPONSE + Index * 4,\r
1514 TRUE,\r
1515 sizeof (UINT32),\r
1516 &Response[Index]\r
1517 );\r
1518 if (EFI_ERROR (Status)) {\r
1519 EmmcPeimHcLedOnOff (Bar, FALSE);\r
1520 return Status;\r
1521 }\r
1522 }\r
1523 CopyMem (Packet->EmmcStatusBlk, Response, sizeof (Response));\r
1524 }\r
1525 }\r
1526\r
1527 if (Status != EFI_NOT_READY) {\r
1528 EmmcPeimHcLedOnOff (Bar, FALSE);\r
1529 }\r
1530\r
1531 return Status;\r
1532}\r
1533\r
1534/**\r
1535 Wait for the TRB execution result.\r
1536\r
1537 @param[in] Bar The mmio base address of the slot to be accessed.\r
1538 @param[in] Trb The pointer to the EMMC_TRB instance.\r
1539\r
1540 @retval EFI_SUCCESS The TRB is executed successfully.\r
1541 @retval Others Some erros happen when executing this request.\r
1542\r
1543**/\r
1544EFI_STATUS\r
1545EmmcPeimWaitTrbResult (\r
1546 IN UINTN Bar,\r
1547 IN EMMC_TRB *Trb\r
1548 )\r
1549{\r
1550 EFI_STATUS Status;\r
1551 EMMC_COMMAND_PACKET *Packet;\r
1552 UINT64 Timeout;\r
1553 BOOLEAN InfiniteWait;\r
1554\r
1555 Packet = Trb->Packet;\r
1556 //\r
1557 // Wait Command Complete Interrupt Status bit in Normal Interrupt Status Register\r
1558 //\r
1559 Timeout = Packet->Timeout;\r
1560 if (Timeout == 0) {\r
1561 InfiniteWait = TRUE;\r
1562 } else {\r
1563 InfiniteWait = FALSE;\r
1564 }\r
1565\r
1566 while (InfiniteWait || (Timeout > 0)) {\r
1567 //\r
1568 // Check Trb execution result by reading Normal Interrupt Status register.\r
1569 //\r
1570 Status = EmmcPeimCheckTrbResult (Bar, Trb);\r
1571 if (Status != EFI_NOT_READY) {\r
1572 return Status;\r
1573 }\r
1574 //\r
1575 // Stall for 1 microsecond.\r
1576 //\r
1577 MicroSecondDelay (1);\r
1578\r
1579 Timeout--;\r
1580 }\r
1581\r
1582 return EFI_TIMEOUT;\r
1583}\r
1584\r
1585/**\r
1586 Sends EMMC command to an EMMC card that is attached to the EMMC controller.\r
1587\r
1588 If Packet is successfully sent to the EMMC card, then EFI_SUCCESS is returned.\r
1589\r
1590 If a device error occurs while sending the Packet, then EFI_DEVICE_ERROR is returned.\r
1591\r
1592 If Slot is not in a valid range for the EMMC controller, then EFI_INVALID_PARAMETER\r
1593 is returned.\r
1594\r
1595 If Packet defines a data command but both InDataBuffer and OutDataBuffer are NULL,\r
1596 EFI_INVALID_PARAMETER is returned.\r
1597\r
1598 @param[in] Slot The slot number of the Emmc card to send the command to.\r
1599 @param[in,out] Packet A pointer to the EMMC command data structure.\r
1600\r
1601 @retval EFI_SUCCESS The EMMC Command Packet was sent by the host.\r
1602 @retval EFI_DEVICE_ERROR A device error occurred while attempting to send the SD\r
1603 command Packet.\r
1604 @retval EFI_INVALID_PARAMETER Packet, Slot, or the contents of the Packet is invalid.\r
1605 @retval EFI_INVALID_PARAMETER Packet defines a data command but both InDataBuffer and\r
1606 OutDataBuffer are NULL.\r
1607 @retval EFI_NO_MEDIA SD Device not present in the Slot.\r
1608 @retval EFI_UNSUPPORTED The command described by the EMMC Command Packet is not\r
1609 supported by the host controller.\r
1610 @retval EFI_BAD_BUFFER_SIZE The InTransferLength or OutTransferLength exceeds the\r
1611 limit supported by EMMC card ( i.e. if the number of bytes\r
1612 exceed the Last LBA).\r
1613\r
1614**/\r
1615EFI_STATUS\r
1616EFIAPI\r
1617EmmcPeimExecCmd (\r
1618 IN EMMC_PEIM_HC_SLOT *Slot,\r
1619 IN OUT EMMC_COMMAND_PACKET *Packet\r
1620 )\r
1621{\r
1622 EFI_STATUS Status;\r
1623 EMMC_TRB *Trb;\r
1624\r
1625 if (Packet == NULL) {\r
1626 return EFI_INVALID_PARAMETER;\r
1627 }\r
1628\r
1629 if ((Packet->EmmcCmdBlk == NULL) || (Packet->EmmcStatusBlk == NULL)) {\r
1630 return EFI_INVALID_PARAMETER;\r
1631 }\r
1632\r
1633 if ((Packet->OutDataBuffer == NULL) && (Packet->OutTransferLength != 0)) {\r
1634 return EFI_INVALID_PARAMETER;\r
1635 }\r
1636\r
1637 if ((Packet->InDataBuffer == NULL) && (Packet->InTransferLength != 0)) {\r
1638 return EFI_INVALID_PARAMETER;\r
1639 }\r
1640\r
1641 Trb = EmmcPeimCreateTrb (Slot, Packet);\r
1642 if (Trb == NULL) {\r
1643 return EFI_OUT_OF_RESOURCES;\r
1644 }\r
1645\r
1646 Status = EmmcPeimWaitTrbEnv (Slot->EmmcHcBase, Trb);\r
1647 if (EFI_ERROR (Status)) {\r
1648 goto Done;\r
1649 }\r
1650\r
1651 Status = EmmcPeimExecTrb (Slot->EmmcHcBase, Trb);\r
1652 if (EFI_ERROR (Status)) {\r
1653 goto Done;\r
1654 }\r
1655\r
1656 Status = EmmcPeimWaitTrbResult (Slot->EmmcHcBase, Trb);\r
1657 if (EFI_ERROR (Status)) {\r
1658 goto Done;\r
1659 }\r
1660\r
1661Done:\r
1662 EmmcPeimFreeTrb (Trb);\r
1663\r
1664 return Status;\r
1665}\r
1666\r
1667/**\r
1668 Send command GO_IDLE_STATE (CMD0 with argument of 0x00000000) to the device to\r
1669 make it go to Idle State.\r
1670\r
1671 Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.\r
1672\r
1673 @param[in] Slot The slot number of the Emmc card to send the command to.\r
1674\r
1675 @retval EFI_SUCCESS The EMMC device is reset correctly.\r
1676 @retval Others The device reset fails.\r
1677\r
1678**/\r
1679EFI_STATUS\r
1680EmmcPeimReset (\r
1681 IN EMMC_PEIM_HC_SLOT *Slot\r
1682 )\r
1683{\r
1684 EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
1685 EMMC_STATUS_BLOCK EmmcStatusBlk;\r
1686 EMMC_COMMAND_PACKET Packet;\r
1687 EFI_STATUS Status;\r
1688\r
1689 ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
1690 ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
1691 ZeroMem (&Packet, sizeof (Packet));\r
1692\r
1693 Packet.EmmcCmdBlk = &EmmcCmdBlk;\r
1694 Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
1695 Packet.Timeout = EMMC_TIMEOUT;\r
1696\r
1697 EmmcCmdBlk.CommandIndex = EMMC_GO_IDLE_STATE;\r
1698 EmmcCmdBlk.CommandType = EmmcCommandTypeBc;\r
1699 EmmcCmdBlk.ResponseType = 0;\r
1700 EmmcCmdBlk.CommandArgument = 0;\r
1701\r
1702 Status = EmmcPeimExecCmd (Slot, &Packet);\r
1703\r
1704 return Status;\r
1705}\r
1706\r
1707/**\r
1708 Send command SEND_OP_COND to the EMMC device to get the data of the OCR register.\r
1709\r
1710 Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.\r
1711\r
1712 @param[in] Slot The slot number of the Emmc card to send the command to.\r
1713 @param[in, out] Argument On input, the argument of SEND_OP_COND is to send to the device.\r
1714 On output, the argument is the value of OCR register.\r
1715\r
1716 @retval EFI_SUCCESS The operation is done correctly.\r
1717 @retval Others The operation fails.\r
1718\r
1719**/\r
1720EFI_STATUS\r
1721EmmcPeimGetOcr (\r
1722 IN EMMC_PEIM_HC_SLOT *Slot,\r
1723 IN OUT UINT32 *Argument\r
1724 )\r
1725{\r
1726 EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
1727 EMMC_STATUS_BLOCK EmmcStatusBlk;\r
1728 EMMC_COMMAND_PACKET Packet;\r
1729 EFI_STATUS Status;\r
1730\r
1731 ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
1732 ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
1733 ZeroMem (&Packet, sizeof (Packet));\r
1734\r
1735 Packet.EmmcCmdBlk = &EmmcCmdBlk;\r
1736 Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
1737 Packet.Timeout = EMMC_TIMEOUT;\r
1738\r
1739 EmmcCmdBlk.CommandIndex = EMMC_SEND_OP_COND;\r
1740 EmmcCmdBlk.CommandType = EmmcCommandTypeBcr;\r
1741 EmmcCmdBlk.ResponseType = EmmcResponceTypeR3;\r
1742 EmmcCmdBlk.CommandArgument = *Argument;\r
1743\r
1744 Status = EmmcPeimExecCmd (Slot, &Packet);\r
1745 if (!EFI_ERROR (Status)) {\r
1746 //\r
1747 // For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12.\r
1748 //\r
1749 *Argument = EmmcStatusBlk.Resp0;\r
1750 }\r
1751\r
1752 return Status;\r
1753}\r
1754\r
1755/**\r
1756 Broadcast command ALL_SEND_CID to the bus to ask all the EMMC devices to send the\r
1757 data of their CID registers.\r
1758\r
1759 Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.\r
1760\r
1761 @param[in] Slot The slot number of the Emmc card to send the command to.\r
1762\r
1763 @retval EFI_SUCCESS The operation is done correctly.\r
1764 @retval Others The operation fails.\r
1765\r
1766**/\r
1767EFI_STATUS\r
1768EmmcPeimGetAllCid (\r
1769 IN EMMC_PEIM_HC_SLOT *Slot\r
1770 )\r
1771{\r
1772 EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
1773 EMMC_STATUS_BLOCK EmmcStatusBlk;\r
1774 EMMC_COMMAND_PACKET Packet;\r
1775 EFI_STATUS Status;\r
1776\r
1777 ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
1778 ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
1779 ZeroMem (&Packet, sizeof (Packet));\r
1780\r
1781 Packet.EmmcCmdBlk = &EmmcCmdBlk;\r
1782 Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
1783 Packet.Timeout = EMMC_TIMEOUT;\r
1784\r
1785 EmmcCmdBlk.CommandIndex = EMMC_ALL_SEND_CID;\r
1786 EmmcCmdBlk.CommandType = EmmcCommandTypeBcr;\r
1787 EmmcCmdBlk.ResponseType = EmmcResponceTypeR2;\r
1788 EmmcCmdBlk.CommandArgument = 0;\r
1789\r
1790 Status = EmmcPeimExecCmd (Slot, &Packet);\r
1791\r
1792 return Status;\r
1793}\r
1794\r
1795/**\r
1796 Send command SET_RELATIVE_ADDR to the EMMC device to assign a Relative device\r
1797 Address (RCA).\r
1798\r
1799 Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.\r
1800\r
1801 @param[in] Slot The slot number of the Emmc card to send the command to.\r
1802 @param[in] Rca The relative device address to be assigned.\r
1803\r
1804 @retval EFI_SUCCESS The operation is done correctly.\r
1805 @retval Others The operation fails.\r
1806\r
1807**/\r
1808EFI_STATUS\r
1809EmmcPeimSetRca (\r
1810 IN EMMC_PEIM_HC_SLOT *Slot,\r
1811 IN UINT32 Rca\r
1812 )\r
1813{\r
1814 EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
1815 EMMC_STATUS_BLOCK EmmcStatusBlk;\r
1816 EMMC_COMMAND_PACKET Packet;\r
1817 EFI_STATUS Status;\r
1818\r
1819 ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
1820 ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
1821 ZeroMem (&Packet, sizeof (Packet));\r
1822\r
1823 Packet.EmmcCmdBlk = &EmmcCmdBlk;\r
1824 Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
1825 Packet.Timeout = EMMC_TIMEOUT;\r
1826\r
1827 EmmcCmdBlk.CommandIndex = EMMC_SET_RELATIVE_ADDR;\r
1828 EmmcCmdBlk.CommandType = EmmcCommandTypeAc;\r
1829 EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;\r
1830 EmmcCmdBlk.CommandArgument = Rca << 16;\r
1831\r
1832 Status = EmmcPeimExecCmd (Slot, &Packet);\r
1833\r
1834 return Status;\r
1835}\r
1836\r
1837/**\r
1838 Send command SEND_CSD to the EMMC device to get the data of the CSD register.\r
1839\r
1840 Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r
1841\r
1842 @param[in] Slot The slot number of the Emmc card to send the command to.\r
1843 @param[in] Rca The relative device address of selected device.\r
1844 @param[out] Csd The buffer to store the content of the CSD register.\r
1845 Note the caller should ignore the lowest byte of this\r
1846 buffer as the content of this byte is meaningless even\r
1847 if the operation succeeds.\r
1848\r
1849 @retval EFI_SUCCESS The operation is done correctly.\r
1850 @retval Others The operation fails.\r
1851\r
1852**/\r
1853EFI_STATUS\r
1854EmmcPeimGetCsd (\r
1855 IN EMMC_PEIM_HC_SLOT *Slot,\r
1856 IN UINT32 Rca,\r
1857 OUT EMMC_CSD *Csd\r
1858 )\r
1859{\r
1860 EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
1861 EMMC_STATUS_BLOCK EmmcStatusBlk;\r
1862 EMMC_COMMAND_PACKET Packet;\r
1863 EFI_STATUS Status;\r
1864\r
1865 ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
1866 ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
1867 ZeroMem (&Packet, sizeof (Packet));\r
1868\r
1869 Packet.EmmcCmdBlk = &EmmcCmdBlk;\r
1870 Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
1871 Packet.Timeout = EMMC_TIMEOUT;\r
1872\r
1873 EmmcCmdBlk.CommandIndex = EMMC_SEND_CSD;\r
1874 EmmcCmdBlk.CommandType = EmmcCommandTypeAc;\r
1875 EmmcCmdBlk.ResponseType = EmmcResponceTypeR2;\r
1876 EmmcCmdBlk.CommandArgument = Rca << 16;\r
1877\r
1878 Status = EmmcPeimExecCmd (Slot, &Packet);\r
1879 if (!EFI_ERROR (Status)) {\r
1880 //\r
1881 // For details, refer to SD Host Controller Simplified Spec 3.0 Table 2-12.\r
1882 //\r
1883 CopyMem (((UINT8*)Csd) + 1, &EmmcStatusBlk.Resp0, sizeof (EMMC_CSD) - 1);\r
1884 }\r
1885\r
1886 return Status;\r
1887}\r
1888\r
1889/**\r
1890 Send command SELECT_DESELECT_CARD to the EMMC device to select/deselect it.\r
1891\r
1892 Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r
1893\r
1894 @param[in] Slot The slot number of the Emmc card to send the command to.\r
1895 @param[in] Rca The relative device address of selected device.\r
1896\r
1897 @retval EFI_SUCCESS The operation is done correctly.\r
1898 @retval Others The operation fails.\r
1899\r
1900**/\r
1901EFI_STATUS\r
1902EmmcPeimSelect (\r
1903 IN EMMC_PEIM_HC_SLOT *Slot,\r
1904 IN UINT32 Rca\r
1905 )\r
1906{\r
1907 EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
1908 EMMC_STATUS_BLOCK EmmcStatusBlk;\r
1909 EMMC_COMMAND_PACKET Packet;\r
1910 EFI_STATUS Status;\r
1911\r
1912 ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
1913 ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
1914 ZeroMem (&Packet, sizeof (Packet));\r
1915\r
1916 Packet.EmmcCmdBlk = &EmmcCmdBlk;\r
1917 Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
1918 Packet.Timeout = EMMC_TIMEOUT;\r
1919\r
1920 EmmcCmdBlk.CommandIndex = EMMC_SELECT_DESELECT_CARD;\r
1921 EmmcCmdBlk.CommandType = EmmcCommandTypeAc;\r
1922 EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;\r
1923 EmmcCmdBlk.CommandArgument = Rca << 16;\r
1924\r
1925 Status = EmmcPeimExecCmd (Slot, &Packet);\r
1926\r
1927 return Status;\r
1928}\r
1929\r
1930/**\r
1931 Send command SEND_EXT_CSD to the EMMC device to get the data of the EXT_CSD register.\r
1932\r
1933 Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r
1934\r
1935 @param[in] Slot The slot number of the Emmc card to send the command to.\r
1936 @param[out] ExtCsd The buffer to store the content of the EXT_CSD register.\r
1937\r
1938 @retval EFI_SUCCESS The operation is done correctly.\r
1939 @retval Others The operation fails.\r
1940\r
1941**/\r
1942EFI_STATUS\r
1943EmmcPeimGetExtCsd (\r
1944 IN EMMC_PEIM_HC_SLOT *Slot,\r
1945 OUT EMMC_EXT_CSD *ExtCsd\r
1946 )\r
1947{\r
1948 EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
1949 EMMC_STATUS_BLOCK EmmcStatusBlk;\r
1950 EMMC_COMMAND_PACKET Packet;\r
1951 EFI_STATUS Status;\r
1952\r
1953 ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
1954 ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
1955 ZeroMem (&Packet, sizeof (Packet));\r
1956\r
1957 Packet.EmmcCmdBlk = &EmmcCmdBlk;\r
1958 Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
1959 Packet.Timeout = EMMC_TIMEOUT;\r
1960\r
1961 EmmcCmdBlk.CommandIndex = EMMC_SEND_EXT_CSD;\r
1962 EmmcCmdBlk.CommandType = EmmcCommandTypeAdtc;\r
1963 EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;\r
1964 EmmcCmdBlk.CommandArgument = 0x00000000;\r
1965\r
1966 Packet.InDataBuffer = ExtCsd;\r
1967 Packet.InTransferLength = sizeof (EMMC_EXT_CSD);\r
1968\r
1969 Status = EmmcPeimExecCmd (Slot, &Packet);\r
1970 return Status;\r
1971}\r
1972\r
1973/**\r
1974 Send command SWITCH to the EMMC device to switch the mode of operation of the\r
1975 selected Device or modifies the EXT_CSD registers.\r
1976\r
1977 Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r
1978\r
1979 @param[in] Slot The slot number of the Emmc card to send the command to.\r
1980 @param[in] Access The access mode of SWTICH command.\r
1981 @param[in] Index The offset of the field to be access.\r
1982 @param[in] Value The value to be set to the specified field of EXT_CSD register.\r
1983 @param[in] CmdSet The value of CmdSet field of EXT_CSD register.\r
1984\r
1985 @retval EFI_SUCCESS The operation is done correctly.\r
1986 @retval Others The operation fails.\r
1987\r
1988**/\r
1989EFI_STATUS\r
1990EmmcPeimSwitch (\r
1991 IN EMMC_PEIM_HC_SLOT *Slot,\r
1992 IN UINT8 Access,\r
1993 IN UINT8 Index,\r
1994 IN UINT8 Value,\r
1995 IN UINT8 CmdSet\r
1996 )\r
1997{\r
1998 EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
1999 EMMC_STATUS_BLOCK EmmcStatusBlk;\r
2000 EMMC_COMMAND_PACKET Packet;\r
2001 EFI_STATUS Status;\r
2002\r
2003 ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
2004 ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
2005 ZeroMem (&Packet, sizeof (Packet));\r
2006\r
2007 Packet.EmmcCmdBlk = &EmmcCmdBlk;\r
2008 Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
2009 Packet.Timeout = EMMC_TIMEOUT;\r
2010\r
2011 EmmcCmdBlk.CommandIndex = EMMC_SWITCH;\r
2012 EmmcCmdBlk.CommandType = EmmcCommandTypeAc;\r
2013 EmmcCmdBlk.ResponseType = EmmcResponceTypeR1b;\r
2014 EmmcCmdBlk.CommandArgument = (Access << 24) | (Index << 16) | (Value << 8) | CmdSet;\r
2015\r
2016 Status = EmmcPeimExecCmd (Slot, &Packet);\r
2017\r
2018 return Status;\r
2019}\r
2020\r
2021/**\r
2022 Send command SEND_STATUS to the addressed EMMC device to get its status register.\r
2023\r
2024 Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r
2025\r
2026 @param[in] Slot The slot number of the Emmc card to send the command to.\r
2027 @param[in] Rca The relative device address of addressed device.\r
2028 @param[out] DevStatus The returned device status.\r
2029\r
2030 @retval EFI_SUCCESS The operation is done correctly.\r
2031 @retval Others The operation fails.\r
2032\r
2033**/\r
2034EFI_STATUS\r
2035EmmcPeimSendStatus (\r
2036 IN EMMC_PEIM_HC_SLOT *Slot,\r
2037 IN UINT32 Rca,\r
2038 OUT UINT32 *DevStatus\r
2039 )\r
2040{\r
2041 EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
2042 EMMC_STATUS_BLOCK EmmcStatusBlk;\r
2043 EMMC_COMMAND_PACKET Packet;\r
2044 EFI_STATUS Status;\r
2045\r
2046 ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
2047 ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
2048 ZeroMem (&Packet, sizeof (Packet));\r
2049\r
2050 Packet.EmmcCmdBlk = &EmmcCmdBlk;\r
2051 Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
2052 Packet.Timeout = EMMC_TIMEOUT;\r
2053\r
2054 EmmcCmdBlk.CommandIndex = EMMC_SEND_STATUS;\r
2055 EmmcCmdBlk.CommandType = EmmcCommandTypeAc;\r
2056 EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;\r
2057 EmmcCmdBlk.CommandArgument = Rca << 16;\r
2058\r
2059 Status = EmmcPeimExecCmd (Slot, &Packet);\r
2060 if (!EFI_ERROR (Status)) {\r
2061 *DevStatus = EmmcStatusBlk.Resp0;\r
2062 }\r
2063\r
2064 return Status;\r
2065}\r
2066\r
2067/**\r
2068 Send command SET_BLOCK_COUNT to the addressed EMMC device to set the number of\r
2069 blocks for the following block read/write cmd.\r
2070\r
2071 Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r
2072\r
2073 @param[in] Slot The slot number of the Emmc card to send the command to.\r
2074 @param[in] BlockCount The number of the logical block to access.\r
2075\r
2076 @retval EFI_SUCCESS The operation is done correctly.\r
2077 @retval Others The operation fails.\r
2078\r
2079**/\r
2080EFI_STATUS\r
2081EmmcPeimSetBlkCount (\r
2082 IN EMMC_PEIM_HC_SLOT *Slot,\r
2083 IN UINT16 BlockCount\r
2084 )\r
2085{\r
2086 EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
2087 EMMC_STATUS_BLOCK EmmcStatusBlk;\r
2088 EMMC_COMMAND_PACKET Packet;\r
2089 EFI_STATUS Status;\r
2090\r
2091 ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
2092 ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
2093 ZeroMem (&Packet, sizeof (Packet));\r
2094\r
2095 Packet.EmmcCmdBlk = &EmmcCmdBlk;\r
2096 Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
2097 Packet.Timeout = EMMC_TIMEOUT;\r
2098\r
2099 EmmcCmdBlk.CommandIndex = EMMC_SET_BLOCK_COUNT;\r
2100 EmmcCmdBlk.CommandType = EmmcCommandTypeAc;\r
2101 EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;\r
2102 EmmcCmdBlk.CommandArgument = BlockCount;\r
2103\r
2104 Status = EmmcPeimExecCmd (Slot, &Packet);\r
2105\r
2106 return Status;\r
2107}\r
2108\r
2109/**\r
2110 Send command READ_MULTIPLE_BLOCK/WRITE_MULTIPLE_BLOCK to the addressed EMMC device\r
2111 to read/write the specified number of blocks.\r
2112\r
2113 Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r
2114\r
2115 @param[in] Slot The slot number of the Emmc card to send the command to.\r
2116 @param[in] Lba The logical block address of starting access.\r
2117 @param[in] BlockSize The block size of specified EMMC device partition.\r
2118 @param[in] Buffer The pointer to the transfer buffer.\r
2119 @param[in] BufferSize The size of transfer buffer.\r
2120 @param[in] IsRead Boolean to show the operation direction.\r
2121\r
2122 @retval EFI_SUCCESS The operation is done correctly.\r
2123 @retval Others The operation fails.\r
2124\r
2125**/\r
2126EFI_STATUS\r
2127EmmcPeimRwMultiBlocks (\r
2128 IN EMMC_PEIM_HC_SLOT *Slot,\r
2129 IN EFI_LBA Lba,\r
2130 IN UINT32 BlockSize,\r
2131 IN VOID *Buffer,\r
2132 IN UINTN BufferSize,\r
2133 IN BOOLEAN IsRead\r
2134 )\r
2135{\r
2136 EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
2137 EMMC_STATUS_BLOCK EmmcStatusBlk;\r
2138 EMMC_COMMAND_PACKET Packet;\r
2139 EFI_STATUS Status;\r
2140\r
2141 ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
2142 ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
2143 ZeroMem (&Packet, sizeof (Packet));\r
2144\r
2145 Packet.EmmcCmdBlk = &EmmcCmdBlk;\r
2146 Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
2147 //\r
2148 // Calculate timeout value through the below formula.\r
2149 // Timeout = (transfer size) / (2MB/s).\r
2150 // Taking 2MB/s as divisor is because it's nearest to the eMMC lowest\r
2151 // transfer speed (2.4MB/s).\r
2152 // Refer to eMMC 5.0 spec section 6.9.1 for details.\r
2153 //\r
2154 Packet.Timeout = (BufferSize / (2 * 1024 * 1024) + 1) * 1000 * 1000;;\r
2155\r
2156 if (IsRead) {\r
2157 Packet.InDataBuffer = Buffer;\r
2158 Packet.InTransferLength = (UINT32)BufferSize;\r
2159\r
2160 EmmcCmdBlk.CommandIndex = EMMC_READ_MULTIPLE_BLOCK;\r
2161 EmmcCmdBlk.CommandType = EmmcCommandTypeAdtc;\r
2162 EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;\r
2163 } else {\r
2164 Packet.OutDataBuffer = Buffer;\r
2165 Packet.OutTransferLength = (UINT32)BufferSize;\r
2166\r
2167 EmmcCmdBlk.CommandIndex = EMMC_WRITE_MULTIPLE_BLOCK;\r
2168 EmmcCmdBlk.CommandType = EmmcCommandTypeAdtc;\r
2169 EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;\r
2170 }\r
2171\r
2172 if (Slot->SectorAddressing) {\r
2173 EmmcCmdBlk.CommandArgument = (UINT32)Lba;\r
2174 } else {\r
2175 EmmcCmdBlk.CommandArgument = (UINT32)MultU64x32 (Lba, BlockSize);\r
2176 }\r
2177\r
2178 Status = EmmcPeimExecCmd (Slot, &Packet);\r
2179\r
2180 return Status;\r
2181}\r
2182\r
2183/**\r
2184 Send command SEND_TUNING_BLOCK to the EMMC device for HS200 optimal sampling point\r
2185 detection.\r
2186\r
2187 It may be sent up to 40 times until the host finishes the tuning procedure.\r
2188\r
2189 Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 for details.\r
2190\r
2191 @param[in] Slot The slot number of the Emmc card to send the command to.\r
2192 @param[in] BusWidth The bus width to work.\r
2193\r
2194 @retval EFI_SUCCESS The operation is done correctly.\r
2195 @retval Others The operation fails.\r
2196\r
2197**/\r
2198EFI_STATUS\r
2199EmmcPeimSendTuningBlk (\r
2200 IN EMMC_PEIM_HC_SLOT *Slot,\r
2201 IN UINT8 BusWidth\r
2202 )\r
2203{\r
2204 EMMC_COMMAND_BLOCK EmmcCmdBlk;\r
2205 EMMC_STATUS_BLOCK EmmcStatusBlk;\r
2206 EMMC_COMMAND_PACKET Packet;\r
2207 EFI_STATUS Status;\r
2208 UINT8 TuningBlock[128];\r
2209\r
2210 ZeroMem (&EmmcCmdBlk, sizeof (EmmcCmdBlk));\r
2211 ZeroMem (&EmmcStatusBlk, sizeof (EmmcStatusBlk));\r
2212 ZeroMem (&Packet, sizeof (Packet));\r
2213\r
2214 Packet.EmmcCmdBlk = &EmmcCmdBlk;\r
2215 Packet.EmmcStatusBlk = &EmmcStatusBlk;\r
2216 Packet.Timeout = EMMC_TIMEOUT;\r
2217\r
2218 EmmcCmdBlk.CommandIndex = EMMC_SEND_TUNING_BLOCK;\r
2219 EmmcCmdBlk.CommandType = EmmcCommandTypeAdtc;\r
2220 EmmcCmdBlk.ResponseType = EmmcResponceTypeR1;\r
2221 EmmcCmdBlk.CommandArgument = 0;\r
2222\r
2223 Packet.InDataBuffer = TuningBlock;\r
2224 if (BusWidth == 8) {\r
2225 Packet.InTransferLength = sizeof (TuningBlock);\r
2226 } else {\r
2227 Packet.InTransferLength = 64;\r
2228 }\r
2229\r
2230 Status = EmmcPeimExecCmd (Slot, &Packet);\r
2231\r
2232 return Status;\r
2233}\r
2234\r
2235/**\r
2236 Tunning the clock to get HS200 optimal sampling point.\r
2237\r
2238 Command SEND_TUNING_BLOCK may be sent up to 40 times until the host finishes the\r
2239 tuning procedure.\r
2240\r
2241 Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller\r
2242 Simplified Spec 3.0 section Figure 2-29 for details.\r
2243\r
2244 @param[in] Slot The slot number of the Emmc card to send the command to.\r
2245 @param[in] BusWidth The bus width to work.\r
2246\r
2247 @retval EFI_SUCCESS The operation is done correctly.\r
2248 @retval Others The operation fails.\r
2249\r
2250**/\r
2251EFI_STATUS\r
2252EmmcPeimTuningClkForHs200 (\r
2253 IN EMMC_PEIM_HC_SLOT *Slot,\r
2254 IN UINT8 BusWidth\r
2255 )\r
2256{\r
2257 EFI_STATUS Status;\r
2258 UINT8 HostCtrl2;\r
2259 UINT8 Retry;\r
2260\r
2261 //\r
2262 // Notify the host that the sampling clock tuning procedure starts.\r
2263 //\r
2264 HostCtrl2 = BIT6;\r
2265 Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
2266 if (EFI_ERROR (Status)) {\r
2267 return Status;\r
2268 }\r
2269 //\r
2270 // Ask the device to send a sequence of tuning blocks till the tuning procedure is done.\r
2271 //\r
2272 Retry = 0;\r
2273 do {\r
2274 Status = EmmcPeimSendTuningBlk (Slot, BusWidth);\r
2275 if (EFI_ERROR (Status)) {\r
2276 return Status;\r
2277 }\r
2278\r
2279 Status = EmmcPeimHcRwMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, TRUE, sizeof (HostCtrl2), &HostCtrl2);\r
2280 if (EFI_ERROR (Status)) {\r
2281 return Status;\r
2282 }\r
2283\r
2284 if ((HostCtrl2 & (BIT6 | BIT7)) == BIT7) {\r
2285 break;\r
2286 }\r
2287 } while (++Retry < 40);\r
2288\r
2289 if (Retry == 40) {\r
2290 Status = EFI_TIMEOUT;\r
2291 }\r
2292 return Status;\r
2293}\r
2294\r
2295/**\r
2296 Switch the bus width to specified width.\r
2297\r
2298 Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.9 and SD Host Controller\r
2299 Simplified Spec 3.0 section Figure 3-7 for details.\r
2300\r
2301 @param[in] Slot The slot number of the Emmc card to send the command to.\r
2302 @param[in] Rca The relative device address to be assigned.\r
2303 @param[in] IsDdr If TRUE, use dual data rate data simpling method. Otherwise\r
2304 use single data rate data simpling method.\r
2305 @param[in] BusWidth The bus width to be set, it could be 4 or 8.\r
2306\r
2307 @retval EFI_SUCCESS The operation is done correctly.\r
2308 @retval Others The operation fails.\r
2309\r
2310**/\r
2311EFI_STATUS\r
2312EmmcPeimSwitchBusWidth (\r
2313 IN EMMC_PEIM_HC_SLOT *Slot,\r
2314 IN UINT32 Rca,\r
2315 IN BOOLEAN IsDdr,\r
2316 IN UINT8 BusWidth\r
2317 )\r
2318{\r
2319 EFI_STATUS Status;\r
2320 UINT8 Access;\r
2321 UINT8 Index;\r
2322 UINT8 Value;\r
2323 UINT8 CmdSet;\r
2324 UINT32 DevStatus;\r
2325\r
2326 //\r
2327 // Write Byte, the Value field is written into the byte pointed by Index.\r
2328 //\r
2329 Access = 0x03;\r
2330 Index = OFFSET_OF (EMMC_EXT_CSD, BusWidth);\r
2331 if (BusWidth == 4) {\r
2332 Value = 1;\r
2333 } else if (BusWidth == 8) {\r
2334 Value = 2;\r
2335 } else {\r
2336 return EFI_INVALID_PARAMETER;\r
2337 }\r
2338\r
2339 if (IsDdr) {\r
2340 Value += 4;\r
2341 }\r
2342\r
2343 CmdSet = 0;\r
2344 Status = EmmcPeimSwitch (Slot, Access, Index, Value, CmdSet);\r
2345 if (EFI_ERROR (Status)) {\r
2346 return Status;\r
2347 }\r
2348\r
2349 Status = EmmcPeimSendStatus (Slot, Rca, &DevStatus);\r
2350 if (EFI_ERROR (Status)) {\r
2351 return Status;\r
2352 }\r
2353 //\r
2354 // Check the switch operation is really successful or not.\r
2355 //\r
2356 if ((DevStatus & BIT7) != 0) {\r
2357 return EFI_DEVICE_ERROR;\r
2358 }\r
2359\r
2360 Status = EmmcPeimHcSetBusWidth (Slot->EmmcHcBase, BusWidth);\r
2361\r
2362 return Status;\r
2363}\r
2364\r
2365/**\r
2366 Switch the clock frequency to the specified value.\r
2367\r
2368 Refer to EMMC Electrical Standard Spec 5.1 Section 6.6 and SD Host Controller\r
2369 Simplified Spec 3.0 section Figure 3-3 for details.\r
2370\r
2371 @param[in] Slot The slot number of the Emmc card to send the command to.\r
2372 @param[in] Rca The relative device address to be assigned.\r
2373 @param[in] HsTiming The value to be written to HS_TIMING field of EXT_CSD register.\r
2374 @param[in] ClockFreq The max clock frequency to be set, the unit is MHz.\r
2375\r
2376 @retval EFI_SUCCESS The operation is done correctly.\r
2377 @retval Others The operation fails.\r
2378\r
2379**/\r
2380EFI_STATUS\r
2381EmmcPeimSwitchClockFreq (\r
2382 IN EMMC_PEIM_HC_SLOT *Slot,\r
2383 IN UINT32 Rca,\r
2384 IN UINT8 HsTiming,\r
2385 IN UINT32 ClockFreq\r
2386 )\r
2387{\r
2388 EFI_STATUS Status;\r
2389 UINT8 Access;\r
2390 UINT8 Index;\r
2391 UINT8 Value;\r
2392 UINT8 CmdSet;\r
2393 UINT32 DevStatus;\r
2394\r
2395 //\r
2396 // Write Byte, the Value field is written into the byte pointed by Index.\r
2397 //\r
2398 Access = 0x03;\r
2399 Index = OFFSET_OF (EMMC_EXT_CSD, HsTiming);\r
2400 Value = HsTiming;\r
2401 CmdSet = 0;\r
2402\r
2403 Status = EmmcPeimSwitch (Slot, Access, Index, Value, CmdSet);\r
2404 if (EFI_ERROR (Status)) {\r
2405 return Status;\r
2406 }\r
2407\r
2408 Status = EmmcPeimSendStatus (Slot, Rca, &DevStatus);\r
2409 if (EFI_ERROR (Status)) {\r
2410 return Status;\r
2411 }\r
2412 //\r
2413 // Check the switch operation is really successful or not.\r
2414 //\r
2415 if ((DevStatus & BIT7) != 0) {\r
2416 return EFI_DEVICE_ERROR;\r
2417 }\r
2418 //\r
2419 // Convert the clock freq unit from MHz to KHz.\r
2420 //\r
2421 Status = EmmcPeimHcClockSupply (Slot->EmmcHcBase, ClockFreq * 1000);\r
2422\r
2423 return Status;\r
2424}\r
2425\r
2426/**\r
2427 Switch to the High Speed timing according to request.\r
2428\r
2429 Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller\r
2430 Simplified Spec 3.0 section Figure 2-29 for details.\r
2431\r
2432 @param[in] Slot The slot number of the Emmc card to send the command to.\r
2433 @param[in] Rca The relative device address to be assigned.\r
2434 @param[in] ClockFreq The max clock frequency to be set.\r
2435 @param[in] IsDdr If TRUE, use dual data rate data simpling method. Otherwise\r
2436 use single data rate data simpling method.\r
2437 @param[in] BusWidth The bus width to be set, it could be 4 or 8.\r
2438\r
2439 @retval EFI_SUCCESS The operation is done correctly.\r
2440 @retval Others The operation fails.\r
2441\r
2442**/\r
2443EFI_STATUS\r
2444EmmcPeimSwitchToHighSpeed (\r
2445 IN EMMC_PEIM_HC_SLOT *Slot,\r
2446 IN UINT32 Rca,\r
2447 IN UINT32 ClockFreq,\r
2448 IN BOOLEAN IsDdr,\r
2449 IN UINT8 BusWidth\r
2450 )\r
2451{\r
2452 EFI_STATUS Status;\r
2453 UINT8 HsTiming;\r
2454 UINT8 HostCtrl1;\r
2455 UINT8 HostCtrl2;\r
2456\r
2457 Status = EmmcPeimSwitchBusWidth (Slot, Rca, IsDdr, BusWidth);\r
2458 if (EFI_ERROR (Status)) {\r
2459 return Status;\r
2460 }\r
2461 //\r
2462 // Set to Hight Speed timing\r
2463 //\r
2464 HostCtrl1 = BIT2;\r
2465 Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL1, sizeof (HostCtrl1), &HostCtrl1);\r
2466 if (EFI_ERROR (Status)) {\r
2467 return Status;\r
2468 }\r
2469\r
2470 HostCtrl2 = (UINT8)~0x7;\r
2471 Status = EmmcPeimHcAndMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
2472 if (EFI_ERROR (Status)) {\r
2473 return Status;\r
2474 }\r
2475 if (IsDdr) {\r
2476 HostCtrl2 = BIT2;\r
2477 } else if (ClockFreq == 52) {\r
2478 HostCtrl2 = BIT0;\r
2479 } else {\r
2480 HostCtrl2 = 0;\r
2481 }\r
2482 Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
2483 if (EFI_ERROR (Status)) {\r
2484 return Status;\r
2485 }\r
2486\r
2487 HsTiming = 1;\r
2488 Status = EmmcPeimSwitchClockFreq (Slot, Rca, HsTiming, ClockFreq);\r
2489 if (EFI_ERROR (Status)) {\r
2490 return Status;\r
2491 }\r
2492\r
2493 return Status;\r
2494}\r
2495\r
2496/**\r
2497 Switch to the HS200 timing according to request.\r
2498\r
2499 Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller\r
2500 Simplified Spec 3.0 section Figure 2-29 for details.\r
2501\r
2502 @param[in] Slot The slot number of the Emmc card to send the command to.\r
2503 @param[in] Rca The relative device address to be assigned.\r
2504 @param[in] ClockFreq The max clock frequency to be set.\r
2505 @param[in] BusWidth The bus width to be set, it could be 4 or 8.\r
2506\r
2507 @retval EFI_SUCCESS The operation is done correctly.\r
2508 @retval Others The operation fails.\r
2509\r
2510**/\r
2511EFI_STATUS\r
2512EmmcPeimSwitchToHS200 (\r
2513 IN EMMC_PEIM_HC_SLOT *Slot,\r
2514 IN UINT32 Rca,\r
2515 IN UINT32 ClockFreq,\r
2516 IN UINT8 BusWidth\r
2517 )\r
2518{\r
2519 EFI_STATUS Status;\r
2520 UINT8 HsTiming;\r
2521 UINT8 HostCtrl2;\r
2522 UINT16 ClockCtrl;\r
2523\r
2524 if ((BusWidth != 4) && (BusWidth != 8)) {\r
2525 return EFI_INVALID_PARAMETER;\r
2526 }\r
2527\r
2528 Status = EmmcPeimSwitchBusWidth (Slot, Rca, FALSE, BusWidth);\r
2529 if (EFI_ERROR (Status)) {\r
2530 return Status;\r
2531 }\r
2532 //\r
2533 // Set to HS200/SDR104 timing\r
2534 //\r
2535 //\r
2536 // Stop bus clock at first\r
2537 //\r
2538 Status = EmmcPeimHcStopClock (Slot->EmmcHcBase);\r
2539 if (EFI_ERROR (Status)) {\r
2540 return Status;\r
2541 }\r
2542\r
2543 HostCtrl2 = (UINT8)~0x7;\r
2544 Status = EmmcPeimHcAndMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
2545 if (EFI_ERROR (Status)) {\r
2546 return Status;\r
2547 }\r
2548 HostCtrl2 = BIT0 | BIT1;\r
2549 Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
2550 if (EFI_ERROR (Status)) {\r
2551 return Status;\r
2552 }\r
2553\r
2554 //\r
2555 // Wait Internal Clock Stable in the Clock Control register to be 1 before set SD Clock Enable bit\r
2556 //\r
2557 Status = EmmcPeimHcWaitMmioSet (\r
2558 Slot->EmmcHcBase + EMMC_HC_CLOCK_CTRL,\r
2559 sizeof (ClockCtrl),\r
2560 BIT1,\r
2561 BIT1,\r
2562 EMMC_TIMEOUT\r
2563 );\r
2564 if (EFI_ERROR (Status)) {\r
2565 return Status;\r
2566 }\r
2567 //\r
2568 // Set SD Clock Enable in the Clock Control register to 1\r
2569 //\r
2570 ClockCtrl = BIT2;\r
2571 Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_CLOCK_CTRL, sizeof (ClockCtrl), &ClockCtrl);\r
2572\r
2573 HsTiming = 2;\r
2574 Status = EmmcPeimSwitchClockFreq (Slot, Rca, HsTiming, ClockFreq);\r
2575 if (EFI_ERROR (Status)) {\r
2576 return Status;\r
2577 }\r
2578\r
2579 Status = EmmcPeimTuningClkForHs200 (Slot, BusWidth);\r
2580\r
2581 return Status;\r
2582}\r
2583\r
2584/**\r
2585 Switch to the HS400 timing according to request.\r
2586\r
2587 Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller\r
2588 Simplified Spec 3.0 section Figure 2-29 for details.\r
2589\r
2590 @param[in] Slot The slot number of the Emmc card to send the command to.\r
2591 @param[in] Rca The relative device address to be assigned.\r
2592 @param[in] ClockFreq The max clock frequency to be set.\r
2593\r
2594 @retval EFI_SUCCESS The operation is done correctly.\r
2595 @retval Others The operation fails.\r
2596\r
2597**/\r
2598EFI_STATUS\r
2599EmmcPeimSwitchToHS400 (\r
2600 IN EMMC_PEIM_HC_SLOT *Slot,\r
2601 IN UINT32 Rca,\r
2602 IN UINT32 ClockFreq\r
2603 )\r
2604{\r
2605 EFI_STATUS Status;\r
2606 UINT8 HsTiming;\r
2607 UINT8 HostCtrl2;\r
2608\r
2609 Status = EmmcPeimSwitchToHS200 (Slot, Rca, ClockFreq, 8);\r
2610 if (EFI_ERROR (Status)) {\r
2611 return Status;\r
2612 }\r
2613 //\r
2614 // Set to Hight Speed timing and set the clock frequency to a value less than 52MHz.\r
2615 //\r
2616 HsTiming = 1;\r
2617 Status = EmmcPeimSwitchClockFreq (Slot, Rca, HsTiming, 52);\r
2618 if (EFI_ERROR (Status)) {\r
2619 return Status;\r
2620 }\r
2621 //\r
2622 // HS400 mode must use 8 data lines.\r
2623 //\r
2624 Status = EmmcPeimSwitchBusWidth (Slot, Rca, TRUE, 8);\r
2625 if (EFI_ERROR (Status)) {\r
2626 return Status;\r
2627 }\r
2628 //\r
2629 // Set to HS400 timing\r
2630 //\r
2631 HostCtrl2 = (UINT8)~0x7;\r
2632 Status = EmmcPeimHcAndMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
2633 if (EFI_ERROR (Status)) {\r
2634 return Status;\r
2635 }\r
2636 HostCtrl2 = BIT0 | BIT2;\r
2637 Status = EmmcPeimHcOrMmio (Slot->EmmcHcBase + EMMC_HC_HOST_CTRL2, sizeof (HostCtrl2), &HostCtrl2);\r
2638 if (EFI_ERROR (Status)) {\r
2639 return Status;\r
2640 }\r
2641\r
2642 HsTiming = 3;\r
2643 Status = EmmcPeimSwitchClockFreq (Slot, Rca, HsTiming, ClockFreq);\r
2644\r
2645 return Status;\r
2646}\r
2647\r
2648/**\r
2649 Switch the high speed timing according to request.\r
2650\r
2651 Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Controller\r
2652 Simplified Spec 3.0 section Figure 2-29 for details.\r
2653\r
2654 @param[in] Slot The slot number of the Emmc card to send the command to.\r
2655 @param[in] Rca The relative device address to be assigned.\r
2656\r
2657 @retval EFI_SUCCESS The operation is done correctly.\r
2658 @retval Others The operation fails.\r
2659\r
2660**/\r
2661EFI_STATUS\r
2662EmmcPeimSetBusMode (\r
2663 IN EMMC_PEIM_HC_SLOT *Slot,\r
2664 IN UINT32 Rca\r
2665 )\r
2666{\r
2667 EFI_STATUS Status;\r
2668 EMMC_HC_SLOT_CAP Capability;\r
2669 UINT8 HsTiming;\r
2670 BOOLEAN IsDdr;\r
2671 UINT32 ClockFreq;\r
2672 UINT8 BusWidth;\r
2673\r
2674 Status = EmmcPeimGetCsd (Slot, Rca, &Slot->Csd);\r
2675 if (EFI_ERROR (Status)) {\r
2676 DEBUG ((EFI_D_ERROR, "EmmcPeimSetBusMode: EmmcPeimGetCsd fails with %r\n", Status));\r
2677 return Status;\r
2678 }\r
2679\r
2680 if ((Slot->Csd.CSizeLow | Slot->Csd.CSizeHigh << 2) == 0xFFF) {\r
2681 Slot->SectorAddressing = TRUE;\r
2682 } else {\r
2683 Slot->SectorAddressing = FALSE;\r
2684 }\r
2685\r
2686 Status = EmmcPeimSelect (Slot, Rca);\r
2687 if (EFI_ERROR (Status)) {\r
2688 DEBUG ((EFI_D_ERROR, "EmmcPeimSetBusMode: EmmcPeimSelect fails with %r\n", Status));\r
2689 return Status;\r
2690 }\r
2691\r
2692 Status = EmmcPeimHcGetCapability (Slot->EmmcHcBase, &Capability);\r
2693 if (EFI_ERROR (Status)) {\r
2694 DEBUG ((EFI_D_ERROR, "EmmcPeimSetBusMode: EmmcPeimHcGetCapability fails with %r\n", Status));\r
2695 return Status;\r
2696 }\r
2697\r
2698 ASSERT (Capability.BaseClkFreq != 0);\r
2699 //\r
2700 // Check if the Host Controller support 8bits bus width.\r
2701 //\r
2702 if (Capability.BusWidth8 != 0) {\r
2703 BusWidth = 8;\r
2704 } else {\r
2705 BusWidth = 4;\r
2706 }\r
2707 //\r
2708 // Get Deivce_Type from EXT_CSD register.\r
2709 //\r
2710 Status = EmmcPeimGetExtCsd (Slot, &Slot->ExtCsd);\r
2711 if (EFI_ERROR (Status)) {\r
2712 DEBUG ((EFI_D_ERROR, "EmmcPeimSetBusMode: EmmcPeimGetExtCsd fails with %r\n", Status));\r
2713 return Status;\r
2714 }\r
2715 //\r
2716 // Calculate supported bus speed/bus width/clock frequency.\r
2717 //\r
2718 HsTiming = 0;\r
2719 IsDdr = FALSE;\r
2720 ClockFreq = 0;\r
2721 if (((Slot->ExtCsd.DeviceType & (BIT4 | BIT5)) != 0) && (Capability.Sdr104 != 0)) {\r
2722 HsTiming = 2;\r
2723 IsDdr = FALSE;\r
2724 ClockFreq = 200;\r
2725 } else if (((Slot->ExtCsd.DeviceType & (BIT2 | BIT3)) != 0) && (Capability.Ddr50 != 0)) {\r
2726 HsTiming = 1;\r
2727 IsDdr = TRUE;\r
2728 ClockFreq = 52;\r
2729 } else if (((Slot->ExtCsd.DeviceType & BIT1) != 0) && (Capability.HighSpeed != 0)) {\r
2730 HsTiming = 1;\r
2731 IsDdr = FALSE;\r
2732 ClockFreq = 52;\r
2733 } else if (((Slot->ExtCsd.DeviceType & BIT0) != 0) && (Capability.HighSpeed != 0)) {\r
2734 HsTiming = 1;\r
2735 IsDdr = FALSE;\r
2736 ClockFreq = 26;\r
2737 }\r
2738 //\r
2739 // Check if both of the device and the host controller support HS400 DDR mode.\r
2740 //\r
2741 if (((Slot->ExtCsd.DeviceType & (BIT6 | BIT7)) != 0) && (Capability.Hs400 != 0)) {\r
2742 //\r
2743 // The host controller supports 8bits bus.\r
2744 //\r
2745 ASSERT (BusWidth == 8);\r
2746 HsTiming = 3;\r
2747 IsDdr = TRUE;\r
2748 ClockFreq = 200;\r
2749 }\r
2750\r
2751 if ((ClockFreq == 0) || (HsTiming == 0)) {\r
2752 //\r
2753 // Continue using default setting.\r
2754 //\r
2755 return EFI_SUCCESS;\r
2756 }\r
2757\r
2758 DEBUG ((EFI_D_INFO, "HsTiming %d ClockFreq %d BusWidth %d Ddr %a\n", HsTiming, ClockFreq, BusWidth, IsDdr ? "TRUE":"FALSE"));\r
2759\r
2760 if (HsTiming == 3) {\r
2761 //\r
2762 // Execute HS400 timing switch procedure\r
2763 //\r
2764 Status = EmmcPeimSwitchToHS400 (Slot, Rca, ClockFreq);\r
2765 } else if (HsTiming == 2) {\r
2766 //\r
2767 // Execute HS200 timing switch procedure\r
2768 //\r
2769 Status = EmmcPeimSwitchToHS200 (Slot, Rca, ClockFreq, BusWidth);\r
2770 } else {\r
2771 //\r
2772 // Execute High Speed timing switch procedure\r
2773 //\r
2774 Status = EmmcPeimSwitchToHighSpeed (Slot, Rca, ClockFreq, BusWidth, IsDdr);\r
2775 }\r
2776\r
2777 return Status;\r
2778}\r
2779\r
2780/**\r
2781 Execute EMMC device identification procedure.\r
2782\r
2783 Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.\r
2784\r
2785 @param[in] Slot The slot number of the Emmc card to send the command to.\r
2786\r
2787 @retval EFI_SUCCESS There is a EMMC card.\r
2788 @retval Others There is not a EMMC card.\r
2789\r
2790**/\r
2791EFI_STATUS\r
2792EmmcPeimIdentification (\r
2793 IN EMMC_PEIM_HC_SLOT *Slot\r
2794 )\r
2795{\r
2796 EFI_STATUS Status;\r
2797 UINT32 Ocr;\r
2798 UINT32 Rca;\r
2799\r
2800 Status = EmmcPeimReset (Slot);\r
2801 if (EFI_ERROR (Status)) {\r
2802 DEBUG ((EFI_D_ERROR, "EmmcPeimIdentification: EmmcPeimReset fails with %r\n", Status));\r
2803 return Status;\r
2804 }\r
2805\r
2806 Ocr = 0;\r
2807 do {\r
2808 Status = EmmcPeimGetOcr (Slot, &Ocr);\r
2809 if (EFI_ERROR (Status)) {\r
2810 DEBUG ((EFI_D_ERROR, "EmmcPeimIdentification: EmmcPeimGetOcr fails with %r\n", Status));\r
2811 return Status;\r
2812 }\r
2813 } while ((Ocr & BIT31) == 0);\r
2814\r
2815 Status = EmmcPeimGetAllCid (Slot);\r
2816 if (EFI_ERROR (Status)) {\r
2817 DEBUG ((EFI_D_ERROR, "EmmcPeimIdentification: EmmcPeimGetAllCid fails with %r\n", Status));\r
2818 return Status;\r
2819 }\r
2820 //\r
2821 // Don't support multiple devices on the slot, that is\r
2822 // shared bus slot feature.\r
2823 //\r
2824 Rca = 1;\r
2825 Status = EmmcPeimSetRca (Slot, Rca);\r
2826 if (EFI_ERROR (Status)) {\r
2827 DEBUG ((EFI_D_ERROR, "EmmcPeimIdentification: EmmcPeimSetRca fails with %r\n", Status));\r
2828 return Status;\r
2829 }\r
2830 //\r
2831 // Enter Data Tranfer Mode.\r
2832 //\r
2833 DEBUG ((EFI_D_INFO, "Found a EMMC device at slot [%d], RCA [%d]\n", Slot, Rca));\r
2834\r
2835 Status = EmmcPeimSetBusMode (Slot, Rca);\r
2836\r
2837 return Status;\r
2838}\r
2839\r
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