[mirror_edk2.git] / MdeModulePkg / Bus / Sd / EmmcBlockIoPei / EmmcHci.h

/** @file\r
\r
  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php.\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef _EMMC_HCI_H_\r
#define _EMMC_HCI_H_\r
\r
//\r
// EMMC Host Controller MMIO Register Offset\r
//\r
#define EMMC_HC_SDMA_ADDR           0x00\r
#define EMMC_HC_ARG2                0x00\r
#define EMMC_HC_BLK_SIZE            0x04\r
#define EMMC_HC_BLK_COUNT           0x06\r
#define EMMC_HC_ARG1                0x08\r
#define EMMC_HC_TRANS_MOD           0x0C\r
#define EMMC_HC_COMMAND             0x0E\r
#define EMMC_HC_RESPONSE            0x10\r
#define EMMC_HC_BUF_DAT_PORT        0x20\r
#define EMMC_HC_PRESENT_STATE       0x24\r
#define EMMC_HC_HOST_CTRL1          0x28\r
#define EMMC_HC_POWER_CTRL          0x29\r
#define EMMC_HC_BLK_GAP_CTRL        0x2A\r
#define EMMC_HC_WAKEUP_CTRL         0x2B\r
#define EMMC_HC_CLOCK_CTRL          0x2C\r
#define EMMC_HC_TIMEOUT_CTRL        0x2E\r
#define EMMC_HC_SW_RST              0x2F\r
#define EMMC_HC_NOR_INT_STS         0x30\r
#define EMMC_HC_ERR_INT_STS         0x32\r
#define EMMC_HC_NOR_INT_STS_EN      0x34\r
#define EMMC_HC_ERR_INT_STS_EN      0x36\r
#define EMMC_HC_NOR_INT_SIG_EN      0x38\r
#define EMMC_HC_ERR_INT_SIG_EN      0x3A\r
#define EMMC_HC_AUTO_CMD_ERR_STS    0x3C\r
#define EMMC_HC_HOST_CTRL2          0x3E\r
#define EMMC_HC_CAP                 0x40\r
#define EMMC_HC_MAX_CURRENT_CAP     0x48\r
#define EMMC_HC_FORCE_EVT_AUTO_CMD  0x50\r
#define EMMC_HC_FORCE_EVT_ERR_INT   0x52\r
#define EMMC_HC_ADMA_ERR_STS        0x54\r
#define EMMC_HC_ADMA_SYS_ADDR       0x58\r
#define EMMC_HC_PRESET_VAL          0x60\r
#define EMMC_HC_SHARED_BUS_CTRL     0xE0\r
#define EMMC_HC_SLOT_INT_STS        0xFC\r
#define EMMC_HC_CTRL_VER            0xFE\r
\r
//\r
// The transfer modes supported by SD Host Controller\r
// Simplified Spec 3.0 Table 1-2\r
//\r
typedef enum {\r
  EmmcNoData,\r
  EmmcPioMode,\r
  EmmcSdmaMode,\r
  EmmcAdmaMode\r
} EMMC_HC_TRANSFER_MODE;\r
\r
//\r
// The maximum data length of each descriptor line\r
//\r
#define ADMA_MAX_DATA_PER_LINE      0x10000\r
#define EMMC_SDMA_BOUNDARY          512 * 1024\r
#define EMMC_SDMA_ROUND_UP(x, n)    (((x) + n) & ~(n - 1))\r
\r
typedef enum {\r
  EmmcCommandTypeBc,  // Broadcast commands, no response\r
  EmmcCommandTypeBcr, // Broadcast commands with response\r
  EmmcCommandTypeAc,  // Addressed(point-to-point) commands\r
  EmmcCommandTypeAdtc // Addressed(point-to-point) data transfer commands\r
} EMMC_COMMAND_TYPE;\r
\r
typedef enum {\r
  EmmcResponceTypeR1,\r
  EmmcResponceTypeR1b,\r
  EmmcResponceTypeR2,\r
  EmmcResponceTypeR3,\r
  EmmcResponceTypeR4,\r
  EmmcResponceTypeR5,\r
  EmmcResponceTypeR5b,\r
  EmmcResponceTypeR6,\r
  EmmcResponceTypeR7\r
} EMMC_RESPONSE_TYPE;\r
\r
typedef struct _EMMC_COMMAND_BLOCK {\r
  UINT16                            CommandIndex;\r
  UINT32                            CommandArgument;\r
  UINT32                            CommandType;      // One of the EMMC_COMMAND_TYPE values\r
  UINT32                            ResponseType;     // One of the EMMC_RESPONSE_TYPE values\r
} EMMC_COMMAND_BLOCK;\r
\r
typedef struct _EMMC_STATUS_BLOCK {\r
  UINT32                            Resp0;\r
  UINT32                            Resp1;\r
  UINT32                            Resp2;\r
  UINT32                            Resp3;\r
} EMMC_STATUS_BLOCK;\r
\r
typedef struct _EMMC_COMMAND_PACKET {\r
  UINT64                            Timeout;\r
  EMMC_COMMAND_BLOCK                *EmmcCmdBlk;\r
  EMMC_STATUS_BLOCK                 *EmmcStatusBlk;\r
  VOID                              *InDataBuffer;\r
  VOID                              *OutDataBuffer;\r
  UINT32                            InTransferLength;\r
  UINT32                            OutTransferLength;\r
} EMMC_COMMAND_PACKET;\r
\r
#pragma pack(1)\r
\r
typedef struct {\r
  UINT32 Valid:1;\r
  UINT32 End:1;\r
  UINT32 Int:1;\r
  UINT32 Reserved:1;\r
  UINT32 Act:2;\r
  UINT32 Reserved1:10;\r
  UINT32 Length:16;\r
  UINT32 Address;\r
} EMMC_HC_ADMA_DESC_LINE;\r
\r
typedef struct {\r
  UINT32   TimeoutFreq:6;     // bit 0:5\r
  UINT32   Reserved:1;        // bit 6\r
  UINT32   TimeoutUnit:1;     // bit 7\r
  UINT32   BaseClkFreq:8;     // bit 8:15\r
  UINT32   MaxBlkLen:2;       // bit 16:17\r
  UINT32   BusWidth8:1;       // bit 18\r
  UINT32   Adma2:1;           // bit 19\r
  UINT32   Reserved2:1;       // bit 20\r
  UINT32   HighSpeed:1;       // bit 21\r
  UINT32   Sdma:1;            // bit 22\r
  UINT32   SuspRes:1;         // bit 23\r
  UINT32   Voltage33:1;       // bit 24\r
  UINT32   Voltage30:1;       // bit 25\r
  UINT32   Voltage18:1;       // bit 26\r
  UINT32   Reserved3:1;       // bit 27\r
  UINT32   SysBus64:1;        // bit 28\r
  UINT32   AsyncInt:1;        // bit 29\r
  UINT32   SlotType:2;        // bit 30:31\r
  UINT32   Sdr50:1;           // bit 32\r
  UINT32   Sdr104:1;          // bit 33\r
  UINT32   Ddr50:1;           // bit 34\r
  UINT32   Reserved4:1;       // bit 35\r
  UINT32   DriverTypeA:1;     // bit 36\r
  UINT32   DriverTypeC:1;     // bit 37\r
  UINT32   DriverTypeD:1;     // bit 38\r
  UINT32   DriverType4:1;     // bit 39\r
  UINT32   TimerCount:4;      // bit 40:43\r
  UINT32   Reserved5:1;       // bit 44\r
  UINT32   TuningSDR50:1;     // bit 45\r
  UINT32   RetuningMod:2;     // bit 46:47\r
  UINT32   ClkMultiplier:8;   // bit 48:55\r
  UINT32   Reserved6:7;       // bit 56:62\r
  UINT32   Hs400:1;           // bit 63\r
} EMMC_HC_SLOT_CAP;\r
\r
#pragma pack()\r
\r
/**\r
  Software reset the specified EMMC host controller and enable all interrupts.\r
\r
  @param[in] Bar            The mmio base address of the slot to be accessed.\r
\r
  @retval EFI_SUCCESS       The software reset executes successfully.\r
  @retval Others            The software reset fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimHcReset (\r
  IN UINTN                  Bar\r
  );\r
\r
/**\r
  Set all interrupt status bits in Normal and Error Interrupt Status Enable\r
  register.\r
\r
  @param[in] Bar            The mmio base address of the slot to be accessed.\r
\r
  @retval EFI_SUCCESS       The operation executes successfully.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimHcEnableInterrupt (\r
  IN UINTN                  Bar\r
  );\r
\r
/**\r
  Get the capability data from the specified slot.\r
\r
  @param[in]  Bar             The mmio base address of the slot to be accessed.\r
  @param[out] Capability      The buffer to store the capability data.\r
\r
  @retval EFI_SUCCESS         The operation executes successfully.\r
  @retval Others              The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimHcGetCapability (\r
  IN     UINTN              Bar,\r
     OUT EMMC_HC_SLOT_CAP   *Capability\r
  );\r
\r
/**\r
  Detect whether there is a EMMC card attached at the specified EMMC host controller\r
  slot.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.\r
\r
  @param[in]  Bar           The mmio base address of the slot to be accessed.\r
\r
  @retval EFI_SUCCESS       There is a EMMC card attached.\r
  @retval EFI_NO_MEDIA      There is not a EMMC card attached.\r
  @retval Others            The detection fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimHcCardDetect (\r
  IN UINTN                  Bar\r
  );\r
\r
/**\r
  Initial EMMC host controller with lowest clock frequency, max power and max timeout value\r
  at initialization.\r
\r
  @param[in] Bar            The mmio base address of the slot to be accessed.\r
\r
  @retval EFI_SUCCESS       The host controller is initialized successfully.\r
  @retval Others            The host controller isn't initialized successfully.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimHcInitHost (\r
  IN UINTN                  Bar\r
  );\r
\r
/**\r
  Send command SWITCH to the EMMC device to switch the mode of operation of the\r
  selected Device or modifies the EXT_CSD registers.\r
\r
  Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r
\r
  @param[in] Slot           The slot number of the Emmc card to send the command to.\r
  @param[in] Access         The access mode of SWTICH command.\r
  @param[in] Index          The offset of the field to be access.\r
  @param[in] Value          The value to be set to the specified field of EXT_CSD register.\r
  @param[in] CmdSet         The value of CmdSet field of EXT_CSD register.\r
\r
  @retval EFI_SUCCESS       The operation is done correctly.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimSwitch (\r
  IN EMMC_PEIM_HC_SLOT                  *Slot,\r
  IN UINT8                              Access,\r
  IN UINT8                              Index,\r
  IN UINT8                              Value,\r
  IN UINT8                              CmdSet\r
  );\r
\r
/**\r
  Send command SET_BLOCK_COUNT to the addressed EMMC device to set the number of\r
  blocks for the following block read/write cmd.\r
\r
  Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r
\r
  @param[in] Slot           The slot number of the Emmc card to send the command to.\r
  @param[in] BlockCount     The number of the logical block to access.\r
\r
  @retval EFI_SUCCESS       The operation is done correctly.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimSetBlkCount (\r
  IN EMMC_PEIM_HC_SLOT              *Slot,\r
  IN UINT16                         BlockCount\r
  );\r
\r
/**\r
  Send command READ_MULTIPLE_BLOCK/WRITE_MULTIPLE_BLOCK to the addressed EMMC device\r
  to read/write the specified number of blocks.\r
\r
  Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r
\r
  @param[in] Slot           The slot number of the Emmc card to send the command to.\r
  @param[in] Lba            The logical block address of starting access.\r
  @param[in] BlockSize      The block size of specified EMMC device partition.\r
  @param[in] Buffer         The pointer to the transfer buffer.\r
  @param[in] BufferSize     The size of transfer buffer.\r
  @param[in] IsRead         Boolean to show the operation direction.\r
\r
  @retval EFI_SUCCESS       The operation is done correctly.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimRwMultiBlocks (\r
  IN EMMC_PEIM_HC_SLOT              *Slot,\r
  IN EFI_LBA                        Lba,\r
  IN UINT32                         BlockSize,\r
  IN VOID                           *Buffer,\r
  IN UINTN                          BufferSize,\r
  IN BOOLEAN                        IsRead\r
  );\r
\r
/**\r
  Execute EMMC device identification procedure.\r
\r
  Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.\r
\r
  @param[in] Slot           The slot number of the Emmc card to send the command to.\r
\r
  @retval EFI_SUCCESS       There is a EMMC card.\r
  @retval Others            There is not a EMMC card.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimIdentification (\r
  IN EMMC_PEIM_HC_SLOT           *Slot\r
  );\r
\r
/**\r
  Free the resource used by the TRB.\r
\r
  @param[in] Trb        The pointer to the EMMC_TRB instance.\r
\r
**/\r
VOID\r
EmmcPeimFreeTrb (\r
  IN EMMC_TRB           *Trb\r
  );\r
\r
#endif\r
\r
Commit	Line	Data
48555339 FT	1	/** @file\r
	2	\r
	3	Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
	4	This program and the accompanying materials\r
	5	are licensed and made available under the terms and conditions of the BSD License\r
	6	which accompanies this distribution. The full text of the license may be found at\r
	7	http://opensource.org/licenses/bsd-license.php.\r
	8	\r
	9	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	10	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	11	\r
	12	**/\r
	13	\r
	14	#ifndef _EMMC_HCI_H_\r
	15	#define _EMMC_HCI_H_\r
	16	\r
	17	//\r
	18	// EMMC Host Controller MMIO Register Offset\r
	19	//\r
	20	#define EMMC_HC_SDMA_ADDR 0x00\r
	21	#define EMMC_HC_ARG2 0x00\r
	22	#define EMMC_HC_BLK_SIZE 0x04\r
	23	#define EMMC_HC_BLK_COUNT 0x06\r
	24	#define EMMC_HC_ARG1 0x08\r
	25	#define EMMC_HC_TRANS_MOD 0x0C\r
	26	#define EMMC_HC_COMMAND 0x0E\r
	27	#define EMMC_HC_RESPONSE 0x10\r
	28	#define EMMC_HC_BUF_DAT_PORT 0x20\r
	29	#define EMMC_HC_PRESENT_STATE 0x24\r
	30	#define EMMC_HC_HOST_CTRL1 0x28\r
	31	#define EMMC_HC_POWER_CTRL 0x29\r
	32	#define EMMC_HC_BLK_GAP_CTRL 0x2A\r
	33	#define EMMC_HC_WAKEUP_CTRL 0x2B\r
	34	#define EMMC_HC_CLOCK_CTRL 0x2C\r
	35	#define EMMC_HC_TIMEOUT_CTRL 0x2E\r
	36	#define EMMC_HC_SW_RST 0x2F\r
	37	#define EMMC_HC_NOR_INT_STS 0x30\r
	38	#define EMMC_HC_ERR_INT_STS 0x32\r
	39	#define EMMC_HC_NOR_INT_STS_EN 0x34\r
	40	#define EMMC_HC_ERR_INT_STS_EN 0x36\r
	41	#define EMMC_HC_NOR_INT_SIG_EN 0x38\r
	42	#define EMMC_HC_ERR_INT_SIG_EN 0x3A\r
	43	#define EMMC_HC_AUTO_CMD_ERR_STS 0x3C\r
	44	#define EMMC_HC_HOST_CTRL2 0x3E\r
	45	#define EMMC_HC_CAP 0x40\r
	46	#define EMMC_HC_MAX_CURRENT_CAP 0x48\r
	47	#define EMMC_HC_FORCE_EVT_AUTO_CMD 0x50\r
	48	#define EMMC_HC_FORCE_EVT_ERR_INT 0x52\r
	49	#define EMMC_HC_ADMA_ERR_STS 0x54\r
	50	#define EMMC_HC_ADMA_SYS_ADDR 0x58\r
	51	#define EMMC_HC_PRESET_VAL 0x60\r
	52	#define EMMC_HC_SHARED_BUS_CTRL 0xE0\r
	53	#define EMMC_HC_SLOT_INT_STS 0xFC\r
	54	#define EMMC_HC_CTRL_VER 0xFE\r
	55	\r
	56	//\r
	57	// The transfer modes supported by SD Host Controller\r
	58	// Simplified Spec 3.0 Table 1-2\r
	59	//\r
	60	typedef enum {\r
	61	EmmcNoData,\r
	62	EmmcPioMode,\r
	63	EmmcSdmaMode,\r
	64	EmmcAdmaMode\r
65	} EMMC_HC_TRANSFER_MODE;\r
66	\r
67	//\r
68	// The maximum data length of each descriptor line\r
69	//\r
70	#define ADMA_MAX_DATA_PER_LINE 0x10000\r
71	#define EMMC_SDMA_BOUNDARY 512 * 1024\r
72	#define EMMC_SDMA_ROUND_UP(x, n) (((x) + n) & ~(n - 1))\r
73	\r
74	typedef enum {\r
75	EmmcCommandTypeBc, // Broadcast commands, no response\r
76	EmmcCommandTypeBcr, // Broadcast commands with response\r
77	EmmcCommandTypeAc, // Addressed(point-to-point) commands\r
78	EmmcCommandTypeAdtc // Addressed(point-to-point) data transfer commands\r
79	} EMMC_COMMAND_TYPE;\r
80	\r
81	typedef enum {\r
82	EmmcResponceTypeR1,\r
83	EmmcResponceTypeR1b,\r
84	EmmcResponceTypeR2,\r
85	EmmcResponceTypeR3,\r
86	EmmcResponceTypeR4,\r
87	EmmcResponceTypeR5,\r
88	EmmcResponceTypeR5b,\r
89	EmmcResponceTypeR6,\r
90	EmmcResponceTypeR7\r
91	} EMMC_RESPONSE_TYPE;\r
92	\r
93	typedef struct _EMMC_COMMAND_BLOCK {\r
94	UINT16 CommandIndex;\r
95	UINT32 CommandArgument;\r
96	UINT32 CommandType; // One of the EMMC_COMMAND_TYPE values\r
97	UINT32 ResponseType; // One of the EMMC_RESPONSE_TYPE values\r
98	} EMMC_COMMAND_BLOCK;\r
99	\r
100	typedef struct _EMMC_STATUS_BLOCK {\r
101	UINT32 Resp0;\r
102	UINT32 Resp1;\r
103	UINT32 Resp2;\r
104	UINT32 Resp3;\r
105	} EMMC_STATUS_BLOCK;\r
106	\r
107	typedef struct _EMMC_COMMAND_PACKET {\r
108	UINT64 Timeout;\r
109	EMMC_COMMAND_BLOCK *EmmcCmdBlk;\r
110	EMMC_STATUS_BLOCK *EmmcStatusBlk;\r
111	VOID *InDataBuffer;\r
112	VOID *OutDataBuffer;\r
113	UINT32 InTransferLength;\r
114	UINT32 OutTransferLength;\r
115	} EMMC_COMMAND_PACKET;\r
116	\r
117	#pragma pack(1)\r
118	\r
119	typedef struct {\r
120	UINT32 Valid:1;\r
121	UINT32 End:1;\r
122	UINT32 Int:1;\r
123	UINT32 Reserved:1;\r
124	UINT32 Act:2;\r
125	UINT32 Reserved1:10;\r
126	UINT32 Length:16;\r
127	UINT32 Address;\r
128	} EMMC_HC_ADMA_DESC_LINE;\r
129	\r
130	typedef struct {\r
131	UINT32 TimeoutFreq:6; // bit 0:5\r
132	UINT32 Reserved:1; // bit 6\r
133	UINT32 TimeoutUnit:1; // bit 7\r
134	UINT32 BaseClkFreq:8; // bit 8:15\r
135	UINT32 MaxBlkLen:2; // bit 16:17\r
136	UINT32 BusWidth8:1; // bit 18\r
137	UINT32 Adma2:1; // bit 19\r
138	UINT32 Reserved2:1; // bit 20\r
139	UINT32 HighSpeed:1; // bit 21\r
140	UINT32 Sdma:1; // bit 22\r
141	UINT32 SuspRes:1; // bit 23\r
142	UINT32 Voltage33:1; // bit 24\r
143	UINT32 Voltage30:1; // bit 25\r
144	UINT32 Voltage18:1; // bit 26\r
145	UINT32 Reserved3:1; // bit 27\r
146	UINT32 SysBus64:1; // bit 28\r
147	UINT32 AsyncInt:1; // bit 29\r
148	UINT32 SlotType:2; // bit 30:31\r
149	UINT32 Sdr50:1; // bit 32\r
150	UINT32 Sdr104:1; // bit 33\r
151	UINT32 Ddr50:1; // bit 34\r
152	UINT32 Reserved4:1; // bit 35\r
153	UINT32 DriverTypeA:1; // bit 36\r
154	UINT32 DriverTypeC:1; // bit 37\r
155	UINT32 DriverTypeD:1; // bit 38\r
156	UINT32 DriverType4:1; // bit 39\r
157	UINT32 TimerCount:4; // bit 40:43\r
158	UINT32 Reserved5:1; // bit 44\r
159	UINT32 TuningSDR50:1; // bit 45\r
160	UINT32 RetuningMod:2; // bit 46:47\r
161	UINT32 ClkMultiplier:8; // bit 48:55\r
162	UINT32 Reserved6:7; // bit 56:62\r
163	UINT32 Hs400:1; // bit 63\r
164	} EMMC_HC_SLOT_CAP;\r
165	\r
166	#pragma pack()\r
167	\r
168	/**\r
169	Software reset the specified EMMC host controller and enable all interrupts.\r
170	\r
171	@param[in] Bar The mmio base address of the slot to be accessed.\r
172	\r
173	@retval EFI_SUCCESS The software reset executes successfully.\r
174	@retval Others The software reset fails.\r
175	\r
176	**/\r
177	EFI_STATUS\r
178	EmmcPeimHcReset (\r
179	IN UINTN Bar\r
180	);\r
181	\r
182	/**\r
183	Set all interrupt status bits in Normal and Error Interrupt Status Enable\r
184	register.\r
185	\r
186	@param[in] Bar The mmio base address of the slot to be accessed.\r
187	\r
188	@retval EFI_SUCCESS The operation executes successfully.\r
189	@retval Others The operation fails.\r
190	\r
191	**/\r
192	EFI_STATUS\r
193	EmmcPeimHcEnableInterrupt (\r
194	IN UINTN Bar\r
195	);\r
196	\r
197	/**\r
198	Get the capability data from the specified slot.\r
199	\r
200	@param[in] Bar The mmio base address of the slot to be accessed.\r
201	@param[out] Capability The buffer to store the capability data.\r
202	\r
203	@retval EFI_SUCCESS The operation executes successfully.\r
204	@retval Others The operation fails.\r
205	\r
206	**/\r
207	EFI_STATUS\r
208	EmmcPeimHcGetCapability (\r
209	IN UINTN Bar,\r
210	OUT EMMC_HC_SLOT_CAP *Capability\r
211	);\r
212	\r
213	/**\r
214	Detect whether there is a EMMC card attached at the specified EMMC host controller\r
215	slot.\r
216	\r
217	Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.\r
218	\r
219	@param[in] Bar The mmio base address of the slot to be accessed.\r
220	\r
221	@retval EFI_SUCCESS There is a EMMC card attached.\r
222	@retval EFI_NO_MEDIA There is not a EMMC card attached.\r
223	@retval Others The detection fails.\r
224	\r
225	**/\r
226	EFI_STATUS\r
227	EmmcPeimHcCardDetect (\r
228	IN UINTN Bar\r
229	);\r
230	\r
231	/**\r
232	Initial EMMC host controller with lowest clock frequency, max power and max timeout value\r
233	at initialization.\r
234	\r
235	@param[in] Bar The mmio base address of the slot to be accessed.\r
236	\r
237	@retval EFI_SUCCESS The host controller is initialized successfully.\r
238	@retval Others The host controller isn't initialized successfully.\r
239	\r
240	**/\r
241	EFI_STATUS\r
242	EmmcPeimHcInitHost (\r
243	IN UINTN Bar\r
244	);\r
245	\r
246	/**\r
247	Send command SWITCH to the EMMC device to switch the mode of operation of the\r
248	selected Device or modifies the EXT_CSD registers.\r
249	\r
250	Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r
251	\r
252	@param[in] Slot The slot number of the Emmc card to send the command to.\r
253	@param[in] Access The access mode of SWTICH command.\r
254	@param[in] Index The offset of the field to be access.\r
255	@param[in] Value The value to be set to the specified field of EXT_CSD register.\r
256	@param[in] CmdSet The value of CmdSet field of EXT_CSD register.\r
257	\r
258	@retval EFI_SUCCESS The operation is done correctly.\r
259	@retval Others The operation fails.\r
260	\r
261	**/\r
262	EFI_STATUS\r
263	EmmcPeimSwitch (\r
264	IN EMMC_PEIM_HC_SLOT *Slot,\r
265	IN UINT8 Access,\r
266	IN UINT8 Index,\r
267	IN UINT8 Value,\r
268	IN UINT8 CmdSet\r
269	);\r
270	\r
271	/**\r
272	Send command SET_BLOCK_COUNT to the addressed EMMC device to set the number of\r
273	blocks for the following block read/write cmd.\r
274	\r
275	Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r
276	\r
277	@param[in] Slot The slot number of the Emmc card to send the command to.\r
278	@param[in] BlockCount The number of the logical block to access.\r
279	\r
280	@retval EFI_SUCCESS The operation is done correctly.\r
281	@retval Others The operation fails.\r
282	\r
283	**/\r
284	EFI_STATUS\r
285	EmmcPeimSetBlkCount (\r
286	IN EMMC_PEIM_HC_SLOT *Slot,\r
287	IN UINT16 BlockCount\r
288	);\r
289	\r
290	/**\r
291	Send command READ_MULTIPLE_BLOCK/WRITE_MULTIPLE_BLOCK to the addressed EMMC device\r
292	to read/write the specified number of blocks.\r
293	\r
294	Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r
295	\r
296	@param[in] Slot The slot number of the Emmc card to send the command to.\r
297	@param[in] Lba The logical block address of starting access.\r
298	@param[in] BlockSize The block size of specified EMMC device partition.\r
299	@param[in] Buffer The pointer to the transfer buffer.\r
300	@param[in] BufferSize The size of transfer buffer.\r
301	@param[in] IsRead Boolean to show the operation direction.\r
302	\r
303	@retval EFI_SUCCESS The operation is done correctly.\r
304	@retval Others The operation fails.\r
305	\r
306	**/\r
307	EFI_STATUS\r
308	EmmcPeimRwMultiBlocks (\r
309	IN EMMC_PEIM_HC_SLOT *Slot,\r
310	IN EFI_LBA Lba,\r
311	IN UINT32 BlockSize,\r
312	IN VOID *Buffer,\r
313	IN UINTN BufferSize,\r
314	IN BOOLEAN IsRead\r
315	);\r
316	\r
317	/**\r
318	Execute EMMC device identification procedure.\r
319	\r
320	Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.\r
321	\r
322	@param[in] Slot The slot number of the Emmc card to send the command to.\r
323	\r
324	@retval EFI_SUCCESS There is a EMMC card.\r
325	@retval Others There is not a EMMC card.\r
326	\r
327	**/\r
328	EFI_STATUS\r
329	EmmcPeimIdentification (\r
330	IN EMMC_PEIM_HC_SLOT *Slot\r
331	);\r
332	\r
333	/**\r
334	Free the resource used by the TRB.\r
335	\r
336	@param[in] Trb The pointer to the EMMC_TRB instance.\r
337	\r
338	**/\r
339	VOID\r
340	EmmcPeimFreeTrb (\r
341	IN EMMC_TRB *Trb\r
342	);\r
343	\r
344	#endif\r
345	\r