[mirror_edk2.git] / MdeModulePkg / Bus / Sd / EmmcBlockIoPei / EmmcHci.h

/** @file\r
\r
  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef _EMMC_HCI_H_\r
#define _EMMC_HCI_H_\r
\r
//\r
// EMMC Host Controller MMIO Register Offset\r
//\r
#define EMMC_HC_SDMA_ADDR           0x00\r
#define EMMC_HC_ARG2                0x00\r
#define EMMC_HC_BLK_SIZE            0x04\r
#define EMMC_HC_BLK_COUNT           0x06\r
#define EMMC_HC_ARG1                0x08\r
#define EMMC_HC_TRANS_MOD           0x0C\r
#define EMMC_HC_COMMAND             0x0E\r
#define EMMC_HC_RESPONSE            0x10\r
#define EMMC_HC_BUF_DAT_PORT        0x20\r
#define EMMC_HC_PRESENT_STATE       0x24\r
#define EMMC_HC_HOST_CTRL1          0x28\r
#define EMMC_HC_POWER_CTRL          0x29\r
#define EMMC_HC_BLK_GAP_CTRL        0x2A\r
#define EMMC_HC_WAKEUP_CTRL         0x2B\r
#define EMMC_HC_CLOCK_CTRL          0x2C\r
#define EMMC_HC_TIMEOUT_CTRL        0x2E\r
#define EMMC_HC_SW_RST              0x2F\r
#define EMMC_HC_NOR_INT_STS         0x30\r
#define EMMC_HC_ERR_INT_STS         0x32\r
#define EMMC_HC_NOR_INT_STS_EN      0x34\r
#define EMMC_HC_ERR_INT_STS_EN      0x36\r
#define EMMC_HC_NOR_INT_SIG_EN      0x38\r
#define EMMC_HC_ERR_INT_SIG_EN      0x3A\r
#define EMMC_HC_AUTO_CMD_ERR_STS    0x3C\r
#define EMMC_HC_HOST_CTRL2          0x3E\r
#define EMMC_HC_CAP                 0x40\r
#define EMMC_HC_MAX_CURRENT_CAP     0x48\r
#define EMMC_HC_FORCE_EVT_AUTO_CMD  0x50\r
#define EMMC_HC_FORCE_EVT_ERR_INT   0x52\r
#define EMMC_HC_ADMA_ERR_STS        0x54\r
#define EMMC_HC_ADMA_SYS_ADDR       0x58\r
#define EMMC_HC_PRESET_VAL          0x60\r
#define EMMC_HC_SHARED_BUS_CTRL     0xE0\r
#define EMMC_HC_SLOT_INT_STS        0xFC\r
#define EMMC_HC_CTRL_VER            0xFE\r
\r
//\r
// The transfer modes supported by SD Host Controller\r
// Simplified Spec 3.0 Table 1-2\r
//\r
typedef enum {\r
  EmmcNoData,\r
  EmmcPioMode,\r
  EmmcSdmaMode,\r
  EmmcAdmaMode\r
} EMMC_HC_TRANSFER_MODE;\r
\r
//\r
// The maximum data length of each descriptor line\r
//\r
#define ADMA_MAX_DATA_PER_LINE      0x10000\r
#define EMMC_SDMA_BOUNDARY          512 * 1024\r
#define EMMC_SDMA_ROUND_UP(x, n)    (((x) + n) & ~(n - 1))\r
\r
typedef enum {\r
  EmmcCommandTypeBc,  // Broadcast commands, no response\r
  EmmcCommandTypeBcr, // Broadcast commands with response\r
  EmmcCommandTypeAc,  // Addressed(point-to-point) commands\r
  EmmcCommandTypeAdtc // Addressed(point-to-point) data transfer commands\r
} EMMC_COMMAND_TYPE;\r
\r
typedef enum {\r
  EmmcResponceTypeR1,\r
  EmmcResponceTypeR1b,\r
  EmmcResponceTypeR2,\r
  EmmcResponceTypeR3,\r
  EmmcResponceTypeR4,\r
  EmmcResponceTypeR5,\r
  EmmcResponceTypeR5b,\r
  EmmcResponceTypeR6,\r
  EmmcResponceTypeR7\r
} EMMC_RESPONSE_TYPE;\r
\r
typedef struct _EMMC_COMMAND_BLOCK {\r
  UINT16                            CommandIndex;\r
  UINT32                            CommandArgument;\r
  UINT32                            CommandType;      // One of the EMMC_COMMAND_TYPE values\r
  UINT32                            ResponseType;     // One of the EMMC_RESPONSE_TYPE values\r
} EMMC_COMMAND_BLOCK;\r
\r
typedef struct _EMMC_STATUS_BLOCK {\r
  UINT32                            Resp0;\r
  UINT32                            Resp1;\r
  UINT32                            Resp2;\r
  UINT32                            Resp3;\r
} EMMC_STATUS_BLOCK;\r
\r
typedef struct _EMMC_COMMAND_PACKET {\r
  UINT64                            Timeout;\r
  EMMC_COMMAND_BLOCK                *EmmcCmdBlk;\r
  EMMC_STATUS_BLOCK                 *EmmcStatusBlk;\r
  VOID                              *InDataBuffer;\r
  VOID                              *OutDataBuffer;\r
  UINT32                            InTransferLength;\r
  UINT32                            OutTransferLength;\r
} EMMC_COMMAND_PACKET;\r
\r
#pragma pack(1)\r
\r
typedef struct {\r
  UINT32 Valid:1;\r
  UINT32 End:1;\r
  UINT32 Int:1;\r
  UINT32 Reserved:1;\r
  UINT32 Act:2;\r
  UINT32 Reserved1:10;\r
  UINT32 Length:16;\r
  UINT32 Address;\r
} EMMC_HC_ADMA_DESC_LINE;\r
\r
typedef struct {\r
  UINT32   TimeoutFreq:6;     // bit 0:5\r
  UINT32   Reserved:1;        // bit 6\r
  UINT32   TimeoutUnit:1;     // bit 7\r
  UINT32   BaseClkFreq:8;     // bit 8:15\r
  UINT32   MaxBlkLen:2;       // bit 16:17\r
  UINT32   BusWidth8:1;       // bit 18\r
  UINT32   Adma2:1;           // bit 19\r
  UINT32   Reserved2:1;       // bit 20\r
  UINT32   HighSpeed:1;       // bit 21\r
  UINT32   Sdma:1;            // bit 22\r
  UINT32   SuspRes:1;         // bit 23\r
  UINT32   Voltage33:1;       // bit 24\r
  UINT32   Voltage30:1;       // bit 25\r
  UINT32   Voltage18:1;       // bit 26\r
  UINT32   Reserved3:1;       // bit 27\r
  UINT32   SysBus64:1;        // bit 28\r
  UINT32   AsyncInt:1;        // bit 29\r
  UINT32   SlotType:2;        // bit 30:31\r
  UINT32   Sdr50:1;           // bit 32\r
  UINT32   Sdr104:1;          // bit 33\r
  UINT32   Ddr50:1;           // bit 34\r
  UINT32   Reserved4:1;       // bit 35\r
  UINT32   DriverTypeA:1;     // bit 36\r
  UINT32   DriverTypeC:1;     // bit 37\r
  UINT32   DriverTypeD:1;     // bit 38\r
  UINT32   DriverType4:1;     // bit 39\r
  UINT32   TimerCount:4;      // bit 40:43\r
  UINT32   Reserved5:1;       // bit 44\r
  UINT32   TuningSDR50:1;     // bit 45\r
  UINT32   RetuningMod:2;     // bit 46:47\r
  UINT32   ClkMultiplier:8;   // bit 48:55\r
  UINT32   Reserved6:7;       // bit 56:62\r
  UINT32   Hs400:1;           // bit 63\r
} EMMC_HC_SLOT_CAP;\r
\r
#pragma pack()\r
\r
/**\r
  Software reset the specified EMMC host controller and enable all interrupts.\r
\r
  @param[in] Bar            The mmio base address of the slot to be accessed.\r
\r
  @retval EFI_SUCCESS       The software reset executes successfully.\r
  @retval Others            The software reset fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimHcReset (\r
  IN UINTN                  Bar\r
  );\r
\r
/**\r
  Set all interrupt status bits in Normal and Error Interrupt Status Enable\r
  register.\r
\r
  @param[in] Bar            The mmio base address of the slot to be accessed.\r
\r
  @retval EFI_SUCCESS       The operation executes successfully.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimHcEnableInterrupt (\r
  IN UINTN                  Bar\r
  );\r
\r
/**\r
  Get the capability data from the specified slot.\r
\r
  @param[in]  Bar             The mmio base address of the slot to be accessed.\r
  @param[out] Capability      The buffer to store the capability data.\r
\r
  @retval EFI_SUCCESS         The operation executes successfully.\r
  @retval Others              The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimHcGetCapability (\r
  IN     UINTN              Bar,\r
     OUT EMMC_HC_SLOT_CAP   *Capability\r
  );\r
\r
/**\r
  Detect whether there is a EMMC card attached at the specified EMMC host controller\r
  slot.\r
\r
  Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.\r
\r
  @param[in]  Bar           The mmio base address of the slot to be accessed.\r
\r
  @retval EFI_SUCCESS       There is a EMMC card attached.\r
  @retval EFI_NO_MEDIA      There is not a EMMC card attached.\r
  @retval Others            The detection fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimHcCardDetect (\r
  IN UINTN                  Bar\r
  );\r
\r
/**\r
  Initial EMMC host controller with lowest clock frequency, max power and max timeout value\r
  at initialization.\r
\r
  @param[in] Bar            The mmio base address of the slot to be accessed.\r
\r
  @retval EFI_SUCCESS       The host controller is initialized successfully.\r
  @retval Others            The host controller isn't initialized successfully.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimHcInitHost (\r
  IN UINTN                  Bar\r
  );\r
\r
/**\r
  Send command SWITCH to the EMMC device to switch the mode of operation of the\r
  selected Device or modifies the EXT_CSD registers.\r
\r
  Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r
\r
  @param[in] Slot           The slot number of the Emmc card to send the command to.\r
  @param[in] Access         The access mode of SWITCH command.\r
  @param[in] Index          The offset of the field to be access.\r
  @param[in] Value          The value to be set to the specified field of EXT_CSD register.\r
  @param[in] CmdSet         The value of CmdSet field of EXT_CSD register.\r
\r
  @retval EFI_SUCCESS       The operation is done correctly.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimSwitch (\r
  IN EMMC_PEIM_HC_SLOT                  *Slot,\r
  IN UINT8                              Access,\r
  IN UINT8                              Index,\r
  IN UINT8                              Value,\r
  IN UINT8                              CmdSet\r
  );\r
\r
/**\r
  Send command SET_BLOCK_COUNT to the addressed EMMC device to set the number of\r
  blocks for the following block read/write cmd.\r
\r
  Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r
\r
  @param[in] Slot           The slot number of the Emmc card to send the command to.\r
  @param[in] BlockCount     The number of the logical block to access.\r
\r
  @retval EFI_SUCCESS       The operation is done correctly.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimSetBlkCount (\r
  IN EMMC_PEIM_HC_SLOT              *Slot,\r
  IN UINT16                         BlockCount\r
  );\r
\r
/**\r
  Send command READ_MULTIPLE_BLOCK/WRITE_MULTIPLE_BLOCK to the addressed EMMC device\r
  to read/write the specified number of blocks.\r
\r
  Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r
\r
  @param[in] Slot           The slot number of the Emmc card to send the command to.\r
  @param[in] Lba            The logical block address of starting access.\r
  @param[in] BlockSize      The block size of specified EMMC device partition.\r
  @param[in] Buffer         The pointer to the transfer buffer.\r
  @param[in] BufferSize     The size of transfer buffer.\r
  @param[in] IsRead         Boolean to show the operation direction.\r
\r
  @retval EFI_SUCCESS       The operation is done correctly.\r
  @retval Others            The operation fails.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimRwMultiBlocks (\r
  IN EMMC_PEIM_HC_SLOT              *Slot,\r
  IN EFI_LBA                        Lba,\r
  IN UINT32                         BlockSize,\r
  IN VOID                           *Buffer,\r
  IN UINTN                          BufferSize,\r
  IN BOOLEAN                        IsRead\r
  );\r
\r
/**\r
  Execute EMMC device identification procedure.\r
\r
  Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.\r
\r
  @param[in] Slot           The slot number of the Emmc card to send the command to.\r
\r
  @retval EFI_SUCCESS       There is a EMMC card.\r
  @retval Others            There is not a EMMC card.\r
\r
**/\r
EFI_STATUS\r
EmmcPeimIdentification (\r
  IN EMMC_PEIM_HC_SLOT           *Slot\r
  );\r
\r
/**\r
  Free the resource used by the TRB.\r
\r
  @param[in] Trb        The pointer to the EMMC_TRB instance.\r
\r
**/\r
VOID\r
EmmcPeimFreeTrb (\r
  IN EMMC_TRB           *Trb\r
  );\r
\r
#endif\r
\r
Commit	Line	Data
48555339 FT	1	/** @file\r
	2	\r
	3	Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
9d510e61	4	SPDX-License-Identifier: BSD-2-Clause-Patent\r
48555339 FT	5	\r
	6	**/\r
	7	\r
	8	#ifndef _EMMC_HCI_H_\r
	9	#define _EMMC_HCI_H_\r
	10	\r
	11	//\r
	12	// EMMC Host Controller MMIO Register Offset\r
	13	//\r
	14	#define EMMC_HC_SDMA_ADDR 0x00\r
	15	#define EMMC_HC_ARG2 0x00\r
	16	#define EMMC_HC_BLK_SIZE 0x04\r
	17	#define EMMC_HC_BLK_COUNT 0x06\r
	18	#define EMMC_HC_ARG1 0x08\r
	19	#define EMMC_HC_TRANS_MOD 0x0C\r
	20	#define EMMC_HC_COMMAND 0x0E\r
	21	#define EMMC_HC_RESPONSE 0x10\r
	22	#define EMMC_HC_BUF_DAT_PORT 0x20\r
	23	#define EMMC_HC_PRESENT_STATE 0x24\r
	24	#define EMMC_HC_HOST_CTRL1 0x28\r
	25	#define EMMC_HC_POWER_CTRL 0x29\r
	26	#define EMMC_HC_BLK_GAP_CTRL 0x2A\r
	27	#define EMMC_HC_WAKEUP_CTRL 0x2B\r
	28	#define EMMC_HC_CLOCK_CTRL 0x2C\r
	29	#define EMMC_HC_TIMEOUT_CTRL 0x2E\r
	30	#define EMMC_HC_SW_RST 0x2F\r
	31	#define EMMC_HC_NOR_INT_STS 0x30\r
	32	#define EMMC_HC_ERR_INT_STS 0x32\r
	33	#define EMMC_HC_NOR_INT_STS_EN 0x34\r
	34	#define EMMC_HC_ERR_INT_STS_EN 0x36\r
	35	#define EMMC_HC_NOR_INT_SIG_EN 0x38\r
	36	#define EMMC_HC_ERR_INT_SIG_EN 0x3A\r
	37	#define EMMC_HC_AUTO_CMD_ERR_STS 0x3C\r
	38	#define EMMC_HC_HOST_CTRL2 0x3E\r
	39	#define EMMC_HC_CAP 0x40\r
	40	#define EMMC_HC_MAX_CURRENT_CAP 0x48\r
	41	#define EMMC_HC_FORCE_EVT_AUTO_CMD 0x50\r
	42	#define EMMC_HC_FORCE_EVT_ERR_INT 0x52\r
	43	#define EMMC_HC_ADMA_ERR_STS 0x54\r
	44	#define EMMC_HC_ADMA_SYS_ADDR 0x58\r
	45	#define EMMC_HC_PRESET_VAL 0x60\r
	46	#define EMMC_HC_SHARED_BUS_CTRL 0xE0\r
	47	#define EMMC_HC_SLOT_INT_STS 0xFC\r
	48	#define EMMC_HC_CTRL_VER 0xFE\r
	49	\r
	50	//\r
	51	// The transfer modes supported by SD Host Controller\r
	52	// Simplified Spec 3.0 Table 1-2\r
	53	//\r
	54	typedef enum {\r
	55	EmmcNoData,\r
	56	EmmcPioMode,\r
	57	EmmcSdmaMode,\r
	58	EmmcAdmaMode\r
	59	} EMMC_HC_TRANSFER_MODE;\r
	60	\r
	61	//\r
	62	// The maximum data length of each descriptor line\r
	63	//\r
	64	#define ADMA_MAX_DATA_PER_LINE 0x10000\r
	65	#define EMMC_SDMA_BOUNDARY 512 * 1024\r
	66	#define EMMC_SDMA_ROUND_UP(x, n) (((x) + n) & ~(n - 1))\r
	67	\r
	68	typedef enum {\r
69	EmmcCommandTypeBc, // Broadcast commands, no response\r
70	EmmcCommandTypeBcr, // Broadcast commands with response\r
71	EmmcCommandTypeAc, // Addressed(point-to-point) commands\r
72	EmmcCommandTypeAdtc // Addressed(point-to-point) data transfer commands\r
73	} EMMC_COMMAND_TYPE;\r
74	\r
75	typedef enum {\r
76	EmmcResponceTypeR1,\r
77	EmmcResponceTypeR1b,\r
78	EmmcResponceTypeR2,\r
79	EmmcResponceTypeR3,\r
80	EmmcResponceTypeR4,\r
81	EmmcResponceTypeR5,\r
82	EmmcResponceTypeR5b,\r
83	EmmcResponceTypeR6,\r
84	EmmcResponceTypeR7\r
85	} EMMC_RESPONSE_TYPE;\r
86	\r
87	typedef struct _EMMC_COMMAND_BLOCK {\r
88	UINT16 CommandIndex;\r
89	UINT32 CommandArgument;\r
90	UINT32 CommandType; // One of the EMMC_COMMAND_TYPE values\r
91	UINT32 ResponseType; // One of the EMMC_RESPONSE_TYPE values\r
92	} EMMC_COMMAND_BLOCK;\r
93	\r
94	typedef struct _EMMC_STATUS_BLOCK {\r
95	UINT32 Resp0;\r
96	UINT32 Resp1;\r
97	UINT32 Resp2;\r
98	UINT32 Resp3;\r
99	} EMMC_STATUS_BLOCK;\r
100	\r
101	typedef struct _EMMC_COMMAND_PACKET {\r
102	UINT64 Timeout;\r
103	EMMC_COMMAND_BLOCK *EmmcCmdBlk;\r
104	EMMC_STATUS_BLOCK *EmmcStatusBlk;\r
105	VOID *InDataBuffer;\r
106	VOID *OutDataBuffer;\r
107	UINT32 InTransferLength;\r
108	UINT32 OutTransferLength;\r
109	} EMMC_COMMAND_PACKET;\r
110	\r
111	#pragma pack(1)\r
112	\r
113	typedef struct {\r
114	UINT32 Valid:1;\r
115	UINT32 End:1;\r
116	UINT32 Int:1;\r
117	UINT32 Reserved:1;\r
118	UINT32 Act:2;\r
119	UINT32 Reserved1:10;\r
120	UINT32 Length:16;\r
121	UINT32 Address;\r
122	} EMMC_HC_ADMA_DESC_LINE;\r
123	\r
124	typedef struct {\r
125	UINT32 TimeoutFreq:6; // bit 0:5\r
126	UINT32 Reserved:1; // bit 6\r
127	UINT32 TimeoutUnit:1; // bit 7\r
128	UINT32 BaseClkFreq:8; // bit 8:15\r
129	UINT32 MaxBlkLen:2; // bit 16:17\r
130	UINT32 BusWidth8:1; // bit 18\r
131	UINT32 Adma2:1; // bit 19\r
132	UINT32 Reserved2:1; // bit 20\r
133	UINT32 HighSpeed:1; // bit 21\r
134	UINT32 Sdma:1; // bit 22\r
135	UINT32 SuspRes:1; // bit 23\r
136	UINT32 Voltage33:1; // bit 24\r
137	UINT32 Voltage30:1; // bit 25\r
138	UINT32 Voltage18:1; // bit 26\r
139	UINT32 Reserved3:1; // bit 27\r
140	UINT32 SysBus64:1; // bit 28\r
141	UINT32 AsyncInt:1; // bit 29\r
142	UINT32 SlotType:2; // bit 30:31\r
143	UINT32 Sdr50:1; // bit 32\r
144	UINT32 Sdr104:1; // bit 33\r
145	UINT32 Ddr50:1; // bit 34\r
146	UINT32 Reserved4:1; // bit 35\r
147	UINT32 DriverTypeA:1; // bit 36\r
148	UINT32 DriverTypeC:1; // bit 37\r
149	UINT32 DriverTypeD:1; // bit 38\r
150	UINT32 DriverType4:1; // bit 39\r
151	UINT32 TimerCount:4; // bit 40:43\r
152	UINT32 Reserved5:1; // bit 44\r
153	UINT32 TuningSDR50:1; // bit 45\r
154	UINT32 RetuningMod:2; // bit 46:47\r
155	UINT32 ClkMultiplier:8; // bit 48:55\r
156	UINT32 Reserved6:7; // bit 56:62\r
157	UINT32 Hs400:1; // bit 63\r
158	} EMMC_HC_SLOT_CAP;\r
159	\r
160	#pragma pack()\r
161	\r
162	/**\r
163	Software reset the specified EMMC host controller and enable all interrupts.\r
164	\r
165	@param[in] Bar The mmio base address of the slot to be accessed.\r
166	\r
167	@retval EFI_SUCCESS The software reset executes successfully.\r
168	@retval Others The software reset fails.\r
169	\r
170	**/\r
171	EFI_STATUS\r
172	EmmcPeimHcReset (\r
173	IN UINTN Bar\r
174	);\r
175	\r
176	/**\r
177	Set all interrupt status bits in Normal and Error Interrupt Status Enable\r
178	register.\r
179	\r
180	@param[in] Bar The mmio base address of the slot to be accessed.\r
181	\r
182	@retval EFI_SUCCESS The operation executes successfully.\r
183	@retval Others The operation fails.\r
184	\r
185	**/\r
186	EFI_STATUS\r
187	EmmcPeimHcEnableInterrupt (\r
188	IN UINTN Bar\r
189	);\r
190	\r
191	/**\r
192	Get the capability data from the specified slot.\r
193	\r
194	@param[in] Bar The mmio base address of the slot to be accessed.\r
195	@param[out] Capability The buffer to store the capability data.\r
196	\r
197	@retval EFI_SUCCESS The operation executes successfully.\r
198	@retval Others The operation fails.\r
199	\r
200	**/\r
201	EFI_STATUS\r
202	EmmcPeimHcGetCapability (\r
203	IN UINTN Bar,\r
204	OUT EMMC_HC_SLOT_CAP *Capability\r
205	);\r
206	\r
207	/**\r
208	Detect whether there is a EMMC card attached at the specified EMMC host controller\r
209	slot.\r
210	\r
211	Refer to SD Host Controller Simplified spec 3.0 Section 3.1 for details.\r
212	\r
213	@param[in] Bar The mmio base address of the slot to be accessed.\r
214	\r
215	@retval EFI_SUCCESS There is a EMMC card attached.\r
216	@retval EFI_NO_MEDIA There is not a EMMC card attached.\r
217	@retval Others The detection fails.\r
218	\r
219	**/\r
220	EFI_STATUS\r
221	EmmcPeimHcCardDetect (\r
222	IN UINTN Bar\r
223	);\r
224	\r
225	/**\r
226	Initial EMMC host controller with lowest clock frequency, max power and max timeout value\r
227	at initialization.\r
228	\r
229	@param[in] Bar The mmio base address of the slot to be accessed.\r
230	\r
231	@retval EFI_SUCCESS The host controller is initialized successfully.\r
232	@retval Others The host controller isn't initialized successfully.\r
233	\r
234	**/\r
235	EFI_STATUS\r
236	EmmcPeimHcInitHost (\r
237	IN UINTN Bar\r
238	);\r
239	\r
240	/**\r
241	Send command SWITCH to the EMMC device to switch the mode of operation of the\r
242	selected Device or modifies the EXT_CSD registers.\r
243	\r
244	Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r
245	\r
246	@param[in] Slot The slot number of the Emmc card to send the command to.\r
b854b075	247	@param[in] Access The access mode of SWITCH command.\r
48555339 FT	248	@param[in] Index The offset of the field to be access.\r
	249	@param[in] Value The value to be set to the specified field of EXT_CSD register.\r
	250	@param[in] CmdSet The value of CmdSet field of EXT_CSD register.\r
	251	\r
	252	@retval EFI_SUCCESS The operation is done correctly.\r
	253	@retval Others The operation fails.\r
	254	\r
	255	**/\r
	256	EFI_STATUS\r
	257	EmmcPeimSwitch (\r
	258	IN EMMC_PEIM_HC_SLOT *Slot,\r
	259	IN UINT8 Access,\r
	260	IN UINT8 Index,\r
	261	IN UINT8 Value,\r
	262	IN UINT8 CmdSet\r
	263	);\r
	264	\r
	265	/**\r
	266	Send command SET_BLOCK_COUNT to the addressed EMMC device to set the number of\r
	267	blocks for the following block read/write cmd.\r
	268	\r
	269	Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r
	270	\r
	271	@param[in] Slot The slot number of the Emmc card to send the command to.\r
	272	@param[in] BlockCount The number of the logical block to access.\r
	273	\r
	274	@retval EFI_SUCCESS The operation is done correctly.\r
	275	@retval Others The operation fails.\r
	276	\r
	277	**/\r
	278	EFI_STATUS\r
	279	EmmcPeimSetBlkCount (\r
	280	IN EMMC_PEIM_HC_SLOT *Slot,\r
	281	IN UINT16 BlockCount\r
	282	);\r
	283	\r
	284	/**\r
	285	Send command READ_MULTIPLE_BLOCK/WRITE_MULTIPLE_BLOCK to the addressed EMMC device\r
	286	to read/write the specified number of blocks.\r
	287	\r
	288	Refer to EMMC Electrical Standard Spec 5.1 Section 6.10.4 for details.\r
	289	\r
	290	@param[in] Slot The slot number of the Emmc card to send the command to.\r
	291	@param[in] Lba The logical block address of starting access.\r
	292	@param[in] BlockSize The block size of specified EMMC device partition.\r
	293	@param[in] Buffer The pointer to the transfer buffer.\r
	294	@param[in] BufferSize The size of transfer buffer.\r
	295	@param[in] IsRead Boolean to show the operation direction.\r
	296	\r
	297	@retval EFI_SUCCESS The operation is done correctly.\r
	298	@retval Others The operation fails.\r
	299	\r
	300	**/\r
	301	EFI_STATUS\r
	302	EmmcPeimRwMultiBlocks (\r
	303	IN EMMC_PEIM_HC_SLOT *Slot,\r
	304	IN EFI_LBA Lba,\r
	305	IN UINT32 BlockSize,\r
	306	IN VOID *Buffer,\r
	307	IN UINTN BufferSize,\r
	308	IN BOOLEAN IsRead\r
	309	);\r
	310	\r
	311	/**\r
312	Execute EMMC device identification procedure.\r
313	\r
314	Refer to EMMC Electrical Standard Spec 5.1 Section 6.4 for details.\r
315	\r
316	@param[in] Slot The slot number of the Emmc card to send the command to.\r
317	\r
318	@retval EFI_SUCCESS There is a EMMC card.\r
319	@retval Others There is not a EMMC card.\r
320	\r
321	**/\r
322	EFI_STATUS\r
323	EmmcPeimIdentification (\r
324	IN EMMC_PEIM_HC_SLOT *Slot\r
325	);\r
326	\r
327	/**\r
328	Free the resource used by the TRB.\r
329	\r
330	@param[in] Trb The pointer to the EMMC_TRB instance.\r
331	\r
332	**/\r
333	VOID\r
334	EmmcPeimFreeTrb (\r
335	IN EMMC_TRB *Trb\r
336	);\r
337	\r
338	#endif\r
339	\r