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MdeModulePkg: Replace BSD License with BSD+Patent License
[mirror_edk2.git] / MdeModulePkg / Bus / Ufs / UfsBlockIoPei / UfsHci.h
CommitLineData
0591696e
FT		 1/** @file\r
2 UfsPassThruDxe driver is used to produce EFI_EXT_SCSI_PASS_THRU protocol interface\r
3 for upper layer application to execute UFS-supported SCSI cmds.\r
4\r
d1102dba 5 Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>\r
9d510e61 6 SPDX-License-Identifier: BSD-2-Clause-Patent\r
0591696e
FT		 7\r
8**/\r
9\r
10#ifndef _UFS_PASS_THRU_HCI_H_\r
11#define _UFS_PASS_THRU_HCI_H_\r
12\r
13//\r
14// Host Capabilities Register Offsets\r
15//\r
16#define UFS_HC_CAP_OFFSET 0x0000 // Controller Capabilities\r
17#define UFS_HC_VER_OFFSET 0x0008 // Version\r
18#define UFS_HC_DDID_OFFSET 0x0010 // Device ID and Device Class\r
19#define UFS_HC_PMID_OFFSET 0x0014 // Product ID and Manufacturer ID\r
20#define UFS_HC_AHIT_OFFSET 0x0018 // Auto-Hibernate Idle Timer\r
21//\r
22// Operation and Runtime Register Offsets\r
23//\r
24#define UFS_HC_IS_OFFSET 0x0020 // Interrupt Status\r
25#define UFS_HC_IE_OFFSET 0x0024 // Interrupt Enable\r
26#define UFS_HC_STATUS_OFFSET 0x0030 // Host Controller Status\r
27#define UFS_HC_ENABLE_OFFSET 0x0034 // Host Controller Enable\r
28#define UFS_HC_UECPA_OFFSET 0x0038 // Host UIC Error Code PHY Adapter Layer\r
29#define UFS_HC_UECDL_OFFSET 0x003c // Host UIC Error Code Data Link Layer\r
30#define UFS_HC_UECN_OFFSET 0x0040 // Host UIC Error Code Network Layer\r
31#define UFS_HC_UECT_OFFSET 0x0044 // Host UIC Error Code Transport Layer\r
32#define UFS_HC_UECDME_OFFSET 0x0048 // Host UIC Error Code DME\r
33#define UFS_HC_UTRIACR_OFFSET 0x004c // UTP Transfer Request Interrupt Aggregation Control Register\r
34//\r
35// UTP Transfer Register Offsets\r
36//\r
37#define UFS_HC_UTRLBA_OFFSET 0x0050 // UTP Transfer Request List Base Address\r
38#define UFS_HC_UTRLBAU_OFFSET 0x0054 // UTP Transfer Request List Base Address Upper 32-Bits\r
39#define UFS_HC_UTRLDBR_OFFSET 0x0058 // UTP Transfer Request List Door Bell Register\r
40#define UFS_HC_UTRLCLR_OFFSET 0x005c // UTP Transfer Request List CLear Register\r
41#define UFS_HC_UTRLRSR_OFFSET 0x0060 // UTP Transfer Request Run-Stop Register\r
42//\r
43// UTP Task Management Register Offsets\r
44//\r
45#define UFS_HC_UTMRLBA_OFFSET 0x0070 // UTP Task Management Request List Base Address\r
46#define UFS_HC_UTMRLBAU_OFFSET 0x0074 // UTP Task Management Request List Base Address Upper 32-Bits\r
47#define UFS_HC_UTMRLDBR_OFFSET 0x0078 // UTP Task Management Request List Door Bell Register\r
48#define UFS_HC_UTMRLCLR_OFFSET 0x007c // UTP Task Management Request List CLear Register\r
49#define UFS_HC_UTMRLRSR_OFFSET 0x0080 // UTP Task Management Run-Stop Register\r
50//\r
51// UIC Command Register Offsets\r
52//\r
53#define UFS_HC_UIC_CMD_OFFSET 0x0090 // UIC Command Register\r
54#define UFS_HC_UCMD_ARG1_OFFSET 0x0094 // UIC Command Argument 1\r
55#define UFS_HC_UCMD_ARG2_OFFSET 0x0098 // UIC Command Argument 2\r
56#define UFS_HC_UCMD_ARG3_OFFSET 0x009c // UIC Command Argument 3\r
57//\r
58// UMA Register Offsets\r
59//\r
60#define UFS_HC_UMA_OFFSET 0x00b0 // Reserved for Unified Memory Extension\r
61\r
62#define UFS_HC_HCE_EN BIT0\r
63#define UFS_HC_HCS_DP BIT0\r
64#define UFS_HC_HCS_UCRDY BIT3\r
65#define UFS_HC_IS_ULSS BIT8\r
66#define UFS_HC_IS_UCCS BIT10\r
67#define UFS_HC_CAP_64ADDR BIT24\r
68#define UFS_HC_CAP_NUTMRS (BIT16 | BIT17 | BIT18)\r
69#define UFS_HC_CAP_NUTRS (BIT0 | BIT1 | BIT2 | BIT3 | BIT4)\r
70#define UFS_HC_UTMRLRSR BIT0\r
71#define UFS_HC_UTRLRSR BIT0\r
72\r
4d580428
HZ		 73//\r
74// The initial value of the OCS field of UTP TRD or TMRD descriptor\r
75// defined in JEDEC JESD223 specification\r
76//\r
77#define UFS_HC_TRD_OCS_INIT_VALUE 0x0F\r
78\r
0591696e
FT		 79//\r
80// A maximum of length of 256KB is supported by PRDT entry\r
81//\r
82#define UFS_MAX_DATA_LEN_PER_PRD 0x40000\r
83\r
84#define UFS_STORAGE_COMMAND_TYPE 0x01\r
85\r
86#define UFS_REGULAR_COMMAND 0x00\r
87#define UFS_INTERRUPT_COMMAND 0x01\r
88\r
89#define UFS_LUN_0 0x00\r
90#define UFS_LUN_1 0x01\r
91#define UFS_LUN_2 0x02\r
92#define UFS_LUN_3 0x03\r
93#define UFS_LUN_4 0x04\r
94#define UFS_LUN_5 0x05\r
95#define UFS_LUN_6 0x06\r
96#define UFS_LUN_7 0x07\r
97#define UFS_WLUN_REPORT_LUNS 0x81\r
98#define UFS_WLUN_UFS_DEV 0xD0\r
99#define UFS_WLUN_BOOT 0xB0\r
100#define UFS_WLUN_RPMB 0xC4\r
101\r
102#pragma pack(1)\r
103\r
104//\r
105// UFSHCI 2.0 Spec Section 5.2.1 Offset 00h: CAP - Controller Capabilities\r
106//\r
107typedef struct {\r
108 UINT8 Nutrs:4; // Number of UTP Transfer Request Slots\r
109 UINT8 Rsvd1:4;\r
110\r
111 UINT8 NoRtt; // Number of outstanding READY TO TRANSFER (RTT) requests supported\r
112\r
113 UINT8 Nutmrs:3; // Number of UTP Task Management Request Slots\r
114 UINT8 Rsvd2:4;\r
115 UINT8 AutoHs:1; // Auto-Hibernation Support\r
116\r
117 UINT8 As64:1; // 64-bit addressing supported\r
118 UINT8 Oodds:1; // Out of order data delivery supported\r
119 UINT8 UicDmetms:1; // UIC DME_TEST_MODE command supported\r
120 UINT8 Ume:1; // Reserved for Unified Memory Extension\r
121 UINT8 Rsvd4:4;\r
122} UFS_HC_CAP;\r
123\r
124//\r
125// UFSHCI 2.0 Spec Section 5.2.2 Offset 08h: VER - UFS Version\r
126//\r
127typedef struct {\r
128 UINT8 Vs:4; // Version Suffix\r
129 UINT8 Mnr:4; // Minor version number\r
130\r
131 UINT8 Mjr; // Major version number\r
132\r
133 UINT16 Rsvd1;\r
134} UFS_HC_VER;\r
135\r
136//\r
137// UFSHCI 2.0 Spec Section 5.2.3 Offset 10h: HCPID - Host Controller Product ID\r
138//\r
139#define UFS_HC_PID UINT32\r
140\r
141//\r
142// UFSHCI 2.0 Spec Section 5.2.4 Offset 14h: HCMID - Host Controller Manufacturer ID\r
143//\r
144#define UFS_HC_MID UINT32\r
145\r
146//\r
147// UFSHCI 2.0 Spec Section 5.2.5 Offset 18h: AHIT - Auto-Hibernate Idle Timer\r
148//\r
149typedef struct {\r
d1102dba 150 UINT32 Ahitv:10; // Auto-Hibernate Idle Timer Value\r
0591696e
FT		 151 UINT32 Ts:3; // Timer scale\r
152 UINT32 Rsvd1:19;\r
153} UFS_HC_AHIT;\r
154\r
155//\r
156// UFSHCI 2.0 Spec Section 5.3.1 Offset 20h: IS - Interrupt Status\r
157//\r
158typedef struct {\r
159 UINT16 Utrcs:1; // UTP Transfer Request Completion Status\r
160 UINT16 Udepri:1; // UIC DME_ENDPOINT_RESET Indication\r
161 UINT16 Ue:1; // UIC Error\r
d1102dba 162 UINT16 Utms:1; // UIC Test Mode Status\r
0591696e 163\r
d1102dba
LG		 164 UINT16 Upms:1; // UIC Power Mode Status\r
165 UINT16 Uhxs:1; // UIC Hibernate Exit Status\r
166 UINT16 Uhes:1; // UIC Hibernate Enter Status\r
167 UINT16 Ulls:1; // UIC Link Lost Status\r
0591696e 168\r
d1102dba
LG		 169 UINT16 Ulss:1; // UIC Link Startup Status\r
170 UINT16 Utmrcs:1; // UTP Task Management Request Completion Status\r
171 UINT16 Uccs:1; // UIC Command Completion Status\r
172 UINT16 Dfes:1; // Device Fatal Error Status\r
0591696e 173\r
d1102dba 174 UINT16 Utpes:1; // UTP Error Status\r
0591696e
FT		 175 UINT16 Rsvd1:3;\r
176\r
177 UINT16 Hcfes:1; // Host Controller Fatal Error Status\r
178 UINT16 Sbfes:1; // System Bus Fatal Error Status\r
179 UINT16 Rsvd2:14;\r
180} UFS_HC_IS;\r
181\r
182//\r
183// UFSHCI 2.0 Spec Section 5.3.2 Offset 24h: IE - Interrupt Enable\r
184//\r
185typedef struct {\r
186 UINT16 Utrce:1; // UTP Transfer Request Completion Enable\r
187 UINT16 Udeprie:1; // UIC DME_ENDPOINT_RESET Enable\r
188 UINT16 Uee:1; // UIC Error Enable\r
189 UINT16 Utmse:1; // UIC Test Mode Status Enable\r
190\r
d1102dba 191 UINT16 Upmse:1; // UIC Power Mode Status Enable\r
0591696e 192 UINT16 Uhxse:1; // UIC Hibernate Exit Status Enable\r
d1102dba 193 UINT16 Uhese:1; // UIC Hibernate Enter Status Enable\r
0591696e
FT		 194 UINT16 Ullse:1; // UIC Link Lost Status Enable\r
195\r
196 UINT16 Ulsse:1; // UIC Link Startup Status Enable\r
197 UINT16 Utmrce:1; // UTP Task Management Request Completion Enable\r
198 UINT16 Ucce:1; // UIC Command Completion Enable\r
199 UINT16 Dfee:1; // Device Fatal Error Enable\r
200\r
201 UINT16 Utpee:1; // UTP Error Enable\r
202 UINT16 Rsvd1:3;\r
203\r
204 UINT16 Hcfee:1; // Host Controller Fatal Error Enable\r
205 UINT16 Sbfee:1; // System Bus Fatal Error Enable\r
206 UINT16 Rsvd2:14;\r
207} UFS_HC_IE;\r
208\r
209//\r
210// UFSHCI 2.0 Spec Section 5.3.3 Offset 30h: HCS - Host Controller Status\r
211//\r
212typedef struct {\r
213 UINT8 Dp:1; // Device Present\r
214 UINT8 UtrlRdy:1; // UTP Transfer Request List Ready\r
215 UINT8 UtmrlRdy:1; // UTP Task Management Request List Ready\r
216 UINT8 UcRdy:1; // UIC COMMAND Ready\r
217 UINT8 Rsvd1:4;\r
218\r
219 UINT8 Upmcrs:3; // UIC Power Mode Change Request Status\r
220 UINT8 Rsvd2:1; // UIC Hibernate Exit Status Enable\r
221 UINT8 Utpec:4; // UTP Error Code\r
222\r
223 UINT8 TtagUtpE; // Task Tag of UTP error\r
224 UINT8 TlunUtpE; // Target LUN of UTP error\r
225} UFS_HC_STATUS;\r
226\r
227//\r
228// UFSHCI 2.0 Spec Section 5.3.4 Offset 34h: HCE - Host Controller Enable\r
229//\r
230typedef struct {\r
231 UINT32 Hce:1; // Host Controller Enable\r
232 UINT32 Rsvd1:31;\r
233} UFS_HC_ENABLE;\r
234\r
235//\r
236// UFSHCI 2.0 Spec Section 5.3.5 Offset 38h: UECPA - Host UIC Error Code PHY Adapter Layer\r
237//\r
238typedef struct {\r
239 UINT32 Ec:5; // UIC PHY Adapter Layer Error Code\r
240 UINT32 Rsvd1:26;\r
241 UINT32 Err:1; // UIC PHY Adapter Layer Error\r
242} UFS_HC_UECPA;\r
243\r
244//\r
245// UFSHCI 2.0 Spec Section 5.3.6 Offset 3ch: UECDL - Host UIC Error Code Data Link Layer\r
246//\r
247typedef struct {\r
248 UINT32 Ec:15; // UIC Data Link Layer Error Code\r
249 UINT32 Rsvd1:16;\r
250 UINT32 Err:1; // UIC Data Link Layer Error\r
251} UFS_HC_UECDL;\r
252\r
253//\r
254// UFSHCI 2.0 Spec Section 5.3.7 Offset 40h: UECN - Host UIC Error Code Network Layer\r
255//\r
256typedef struct {\r
257 UINT32 Ec:3; // UIC Network Layer Error Code\r
258 UINT32 Rsvd1:28;\r
259 UINT32 Err:1; // UIC Network Layer Error\r
260} UFS_HC_UECN;\r
261\r
262//\r
263// UFSHCI 2.0 Spec Section 5.3.8 Offset 44h: UECT - Host UIC Error Code Transport Layer\r
264//\r
265typedef struct {\r
266 UINT32 Ec:7; // UIC Transport Layer Error Code\r
267 UINT32 Rsvd1:24;\r
268 UINT32 Err:1; // UIC Transport Layer Error\r
269} UFS_HC_UECT;\r
270\r
271//\r
272// UFSHCI 2.0 Spec Section 5.3.9 Offset 48h: UECDME - Host UIC Error Code\r
273//\r
274typedef struct {\r
275 UINT32 Ec:1; // UIC DME Error Code\r
276 UINT32 Rsvd1:30;\r
277 UINT32 Err:1; // UIC DME Error\r
278} UFS_HC_UECDME;\r
279\r
280//\r
281// UFSHCI 2.0 Spec Section 5.3.10 Offset 4Ch: UTRIACR - UTP Transfer Request Interrupt Aggregation Control Register\r
282//\r
283typedef struct {\r
284 UINT8 IaToVal; // Interrupt aggregation timeout value\r
285\r
286 UINT8 IacTh:5; // Interrupt aggregation counter threshold\r
287 UINT8 Rsvd1:3;\r
288\r
289 UINT8 Ctr:1; // Counter and Timer Reset\r
290 UINT8 Rsvd2:3;\r
291 UINT8 Iasb:1; // Interrupt aggregation status bit\r
292 UINT8 Rsvd3:3;\r
293\r
294 UINT8 IapwEn:1; // Interrupt aggregation parameter write enable\r
295 UINT8 Rsvd4:6;\r
296 UINT8 IaEn:1; // Interrupt Aggregation Enable/Disable\r
297} UFS_HC_UTRIACR;\r
298\r
299//\r
300// UFSHCI 2.0 Spec Section 5.4.1 Offset 50h: UTRLBA - UTP Transfer Request List Base Address\r
301//\r
302typedef struct {\r
303 UINT32 Rsvd1:10;\r
304 UINT32 UtrlBa:22; // UTP Transfer Request List Base Address\r
305} UFS_HC_UTRLBA;\r
306\r
307//\r
308// UFSHCI 2.0 Spec Section 5.4.2 Offset 54h: UTRLBAU - UTP Transfer Request List Base Address Upper 32-bits\r
309//\r
310#define UFS_HC_UTRLBAU UINT32\r
311\r
312//\r
313// UFSHCI 2.0 Spec Section 5.4.3 Offset 58h: UTRLDBR - UTP Transfer Request List Door Bell Register\r
314//\r
315#define UFS_HC_UTRLDBR UINT32\r
316\r
317//\r
318// UFSHCI 2.0 Spec Section 5.4.4 Offset 5Ch: UTRLCLR - UTP Transfer Request List CLear Register\r
319//\r
320#define UFS_HC_UTRLCLR UINT32\r
321\r
322#if 0\r
323//\r
324// UFSHCI 2.0 Spec Section 5.4.5 Offset 60h: UTRLRSR - UTP Transfer Request List Run Stop Register\r
325//\r
326typedef struct {\r
327 UINT32 UtrlRsr:1; // UTP Transfer Request List Run-Stop Register\r
328 UINT32 Rsvd1:31;\r
329} UFS_HC_UTRLRSR;\r
330#endif\r
331\r
332//\r
333// UFSHCI 2.0 Spec Section 5.5.1 Offset 70h: UTMRLBA - UTP Task Management Request List Base Address\r
334//\r
335typedef struct {\r
336 UINT32 Rsvd1:10;\r
337 UINT32 UtmrlBa:22; // UTP Task Management Request List Base Address\r
338} UFS_HC_UTMRLBA;\r
339\r
340//\r
341// UFSHCI 2.0 Spec Section 5.5.2 Offset 74h: UTMRLBAU - UTP Task Management Request List Base Address Upper 32-bits\r
342//\r
343#define UFS_HC_UTMRLBAU UINT32\r
344\r
345//\r
346// UFSHCI 2.0 Spec Section 5.5.3 Offset 78h: UTMRLDBR - UTP Task Management Request List Door Bell Register\r
347//\r
348typedef struct {\r
349 UINT32 UtmrlDbr:8; // UTP Task Management Request List Door bell Register\r
350 UINT32 Rsvd1:24;\r
351} UFS_HC_UTMRLDBR;\r
352\r
353//\r
354// UFSHCI 2.0 Spec Section 5.5.4 Offset 7Ch: UTMRLCLR - UTP Task Management Request List CLear Register\r
355//\r
356typedef struct {\r
357 UINT32 UtmrlClr:8; // UTP Task Management List Clear Register\r
358 UINT32 Rsvd1:24;\r
359} UFS_HC_UTMRLCLR;\r
360\r
361#if 0\r
362//\r
363// UFSHCI 2.0 Spec Section 5.5.5 Offset 80h: UTMRLRSR - UTP Task Management Request List Run Stop Register\r
364//\r
365typedef struct {\r
366 UINT32 UtmrlRsr:1; // UTP Task Management Request List Run-Stop Register\r
367 UINT32 Rsvd1:31;\r
368} UFS_HC_UTMRLRSR;\r
369#endif\r
370\r
371//\r
372// UFSHCI 2.0 Spec Section 5.6.1 Offset 90h: UICCMD - UIC Command\r
373//\r
374typedef struct {\r
375 UINT32 CmdOp:8; // Command Opcode\r
376 UINT32 Rsvd1:24;\r
377} UFS_HC_UICCMD;\r
378\r
379//\r
380// UFSHCI 2.0 Spec Section 5.6.2 Offset 94h: UICCMDARG1 - UIC Command Argument 1\r
381//\r
382#define UFS_HC_UICCMD_ARG1 UINT32\r
383\r
384//\r
385// UFSHCI 2.0 Spec Section 5.6.2 Offset 98h: UICCMDARG2 - UIC Command Argument 2\r
386//\r
387#define UFS_HC_UICCMD_ARG2 UINT32\r
388\r
389//\r
390// UFSHCI 2.0 Spec Section 5.6.2 Offset 9ch: UICCMDARG3 - UIC Command Argument 3\r
391//\r
392#define UFS_HC_UICCMD_ARG3 UINT32\r
393\r
394//\r
395// UIC command opcodes\r
396//\r
397typedef enum {\r
398 UfsUicDmeGet = 0x01,\r
399 UfsUicDmeSet = 0x02,\r
400 UfsUicDmePeerGet = 0x03,\r
401 UfsUicDmePeerSet = 0x04,\r
402 UfsUicDmePwrOn = 0x10,\r
403 UfsUicDmePwrOff = 0x11,\r
404 UfsUicDmeEnable = 0x12,\r
405 UfsUicDmeReset = 0x14,\r
406 UfsUicDmeEndpointReset = 0x15,\r
407 UfsUicDmeLinkStartup = 0x16,\r
408 UfsUicDmeHibernateEnter = 0x17,\r
409 UfsUicDmeHibernateExit = 0x18,\r
410 UfsUicDmeTestMode = 0x1A\r
411} UFS_UIC_OPCODE;\r
412\r
413//\r
414// UTP Transfer Request Descriptor\r
415//\r
416typedef struct {\r
417 //\r
418 // DW0\r
419 //\r
420 UINT32 Rsvd1:24;\r
421 UINT32 Int:1; /* Interrupt */\r
422 UINT32 Dd:2; /* Data Direction */\r
423 UINT32 Rsvd2:1;\r
424 UINT32 Ct:4; /* Command Type */\r
425\r
426 //\r
427 // DW1\r
428 //\r
429 UINT32 Rsvd3;\r
430\r
431 //\r
432 // DW2\r
433 //\r
434 UINT32 Ocs:8; /* Overall Command Status */\r
435 UINT32 Rsvd4:24;\r
436\r
437 //\r
438 // DW3\r
439 //\r
440 UINT32 Rsvd5;\r
441\r
442 //\r
443 // DW4\r
444 //\r
445 UINT32 Rsvd6:7;\r
446 UINT32 UcdBa:25; /* UTP Command Descriptor Base Address */\r
d1102dba 447\r
0591696e
FT		 448 //\r
449 // DW5\r
450 //\r
451 UINT32 UcdBaU; /* UTP Command Descriptor Base Address Upper 32-bits */\r
d1102dba 452\r
0591696e
FT		 453 //\r
454 // DW6\r
455 //\r
d1102dba 456 UINT16 RuL; /* Response UPIU Length */\r
0591696e
FT		 457 UINT16 RuO; /* Response UPIU Offset */\r
458\r
459 //\r
460 // DW7\r
461 //\r
d1102dba 462 UINT16 PrdtL; /* PRDT Length */\r
0591696e
FT		 463 UINT16 PrdtO; /* PRDT Offset */\r
464} UTP_TRD;\r
465\r
466typedef struct {\r
467 //\r
468 // DW0\r
469 //\r
470 UINT32 Rsvd1:2;\r
471 UINT32 DbAddr:30; /* Data Base Address */\r
d1102dba 472\r
0591696e
FT		 473 //\r
474 // DW1\r
475 //\r
476 UINT32 DbAddrU; /* Data Base Address Upper 32-bits */\r
d1102dba 477\r
0591696e
FT		 478 //\r
479 // DW2\r
480 //\r
481 UINT32 Rsvd2;\r
482\r
483 //\r
484 // DW3\r
485 //\r
486 UINT32 DbCount:18; /* Data Byte Count */\r
487 UINT32 Rsvd3:14;\r
488} UTP_TR_PRD;\r
489\r
490//\r
491// UFS 2.0 Spec Section 10.5.3 - UTP Command UPIU\r
492//\r
493typedef struct {\r
494 //\r
495 // DW0\r
496 //\r
497 UINT8 TransCode:6; /* Transaction Type - 0x01*/\r
498 UINT8 Dd:1;\r
499 UINT8 Hd:1;\r
500 UINT8 Flags;\r
501 UINT8 Lun;\r
502 UINT8 TaskTag; /* Task Tag */\r
503\r
504 //\r
505 // DW1\r
506 //\r
507 UINT8 CmdSet:4; /* Command Set Type */\r
508 UINT8 Rsvd1:4;\r
509 UINT8 Rsvd2;\r
510 UINT8 Rsvd3;\r
511 UINT8 Rsvd4;\r
512\r
513 //\r
514 // DW2\r
515 //\r
516 UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
517 UINT8 Rsvd5;\r
518 UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */\r
519\r
520 //\r
521 // DW3\r
522 //\r
523 UINT32 ExpDataTranLen; /* Expected Data Transfer Length - Big Endian */\r
524\r
525 //\r
526 // DW4 - DW7\r
527 //\r
528 UINT8 Cdb[16];\r
529} UTP_COMMAND_UPIU;\r
530\r
531//\r
532// UFS 2.0 Spec Section 10.5.4 - UTP Response UPIU\r
533//\r
534typedef struct {\r
535 //\r
536 // DW0\r
537 //\r
538 UINT8 TransCode:6; /* Transaction Type - 0x21*/\r
539 UINT8 Dd:1;\r
540 UINT8 Hd:1;\r
541 UINT8 Flags;\r
542 UINT8 Lun;\r
543 UINT8 TaskTag; /* Task Tag */\r
544\r
545 //\r
546 // DW1\r
547 //\r
548 UINT8 CmdSet:4; /* Command Set Type */\r
549 UINT8 Rsvd1:4;\r
550 UINT8 Rsvd2;\r
551 UINT8 Response; /* Response */\r
552 UINT8 Status; /* Status */\r
553\r
554 //\r
555 // DW2\r
556 //\r
557 UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
558 UINT8 DevInfo; /* Device Information */\r
559 UINT16 DataSegLen; /* Data Segment Length - Big Endian */\r
560\r
561 //\r
562 // DW3\r
563 //\r
564 UINT32 ResTranCount; /* Residual Transfer Count - Big Endian */\r
565\r
566 //\r
567 // DW4 - DW7\r
568 //\r
569 UINT8 Rsvd3[16];\r
570\r
571 //\r
572 // Data Segment - Sense Data\r
573 //\r
574 UINT16 SenseDataLen; /* Sense Data Length - Big Endian */\r
575 UINT8 SenseData[18]; /* Sense Data */\r
576} UTP_RESPONSE_UPIU;\r
577\r
578//\r
579// UFS 2.0 Spec Section 10.5.5 - UTP Data-Out UPIU\r
580//\r
581typedef struct {\r
582 //\r
583 // DW0\r
584 //\r
585 UINT8 TransCode:6; /* Transaction Type - 0x02*/\r
586 UINT8 Dd:1;\r
587 UINT8 Hd:1;\r
588 UINT8 Flags;\r
589 UINT8 Lun;\r
590 UINT8 TaskTag; /* Task Tag */\r
591\r
592 //\r
593 // DW1\r
594 //\r
595 UINT8 Rsvd1[4];\r
596\r
597 //\r
598 // DW2\r
599 //\r
600 UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
601 UINT8 Rsvd2;\r
602 UINT16 DataSegLen; /* Data Segment Length - Big Endian */\r
603\r
604 //\r
605 // DW3\r
606 //\r
607 UINT32 DataBufOffset; /* Data Buffer Offset - Big Endian */\r
608\r
609 //\r
610 // DW4\r
611 //\r
612 UINT32 DataTranCount; /* Data Transfer Count - Big Endian */\r
613\r
614 //\r
615 // DW5 - DW7\r
616 //\r
617 UINT8 Rsvd3[12];\r
618\r
619 //\r
620 // Data Segment - Data to be sent out\r
621 //\r
622 //UINT8 Data[]; /* Data to be sent out, maximum is 65535 bytes */\r
623} UTP_DATA_OUT_UPIU;\r
624\r
625//\r
626// UFS 2.0 Spec Section 10.5.6 - UTP Data-In UPIU\r
627//\r
628typedef struct {\r
629 //\r
630 // DW0\r
631 //\r
632 UINT8 TransCode:6; /* Transaction Type - 0x22*/\r
633 UINT8 Dd:1;\r
634 UINT8 Hd:1;\r
635 UINT8 Flags;\r
636 UINT8 Lun;\r
637 UINT8 TaskTag; /* Task Tag */\r
638\r
639 //\r
640 // DW1\r
641 //\r
642 UINT8 Rsvd1[4];\r
643\r
644 //\r
645 // DW2\r
646 //\r
647 UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
648 UINT8 Rsvd2;\r
649 UINT16 DataSegLen; /* Data Segment Length - Big Endian */\r
650\r
651 //\r
652 // DW3\r
653 //\r
654 UINT32 DataBufOffset; /* Data Buffer Offset - Big Endian */\r
655\r
656 //\r
657 // DW4\r
658 //\r
659 UINT32 DataTranCount; /* Data Transfer Count - Big Endian */\r
660\r
661 //\r
662 // DW5 - DW7\r
663 //\r
664 UINT8 Rsvd3[12];\r
665\r
666 //\r
667 // Data Segment - Data to be read\r
668 //\r
669 //UINT8 Data[]; /* Data to be read, maximum is 65535 bytes */\r
670} UTP_DATA_IN_UPIU;\r
671\r
672//\r
673// UFS 2.0 Spec Section 10.5.7 - UTP Ready-To-Transfer UPIU\r
674//\r
675typedef struct {\r
676 //\r
677 // DW0\r
678 //\r
679 UINT8 TransCode:6; /* Transaction Type - 0x31*/\r
680 UINT8 Dd:1;\r
681 UINT8 Hd:1;\r
682 UINT8 Flags;\r
683 UINT8 Lun;\r
684 UINT8 TaskTag; /* Task Tag */\r
685\r
686 //\r
687 // DW1\r
688 //\r
689 UINT8 Rsvd1[4];\r
690\r
691 //\r
692 // DW2\r
693 //\r
694 UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
695 UINT8 Rsvd2;\r
696 UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */\r
697\r
698 //\r
699 // DW3\r
700 //\r
701 UINT32 DataBufOffset; /* Data Buffer Offset - Big Endian */\r
702\r
703 //\r
704 // DW4\r
705 //\r
706 UINT32 DataTranCount; /* Data Transfer Count - Big Endian */\r
707\r
708 //\r
709 // DW5 - DW7\r
710 //\r
711 UINT8 Rsvd3[12];\r
712\r
713 //\r
714 // Data Segment - Data to be read\r
715 //\r
716 //UINT8 Data[]; /* Data to be read, maximum is 65535 bytes */\r
717} UTP_RDY_TO_TRAN_UPIU;\r
718\r
719//\r
720// UFS 2.0 Spec Section 10.5.8 - UTP Task Management Request UPIU\r
721//\r
722typedef struct {\r
723 //\r
724 // DW0\r
725 //\r
726 UINT8 TransCode:6; /* Transaction Type - 0x04*/\r
727 UINT8 Dd:1;\r
728 UINT8 Hd:1;\r
729 UINT8 Flags;\r
730 UINT8 Lun;\r
731 UINT8 TaskTag; /* Task Tag */\r
732\r
733 //\r
734 // DW1\r
735 //\r
736 UINT8 Rsvd1;\r
737 UINT8 TskManFunc; /* Task Management Function */\r
738 UINT8 Rsvd2[2];\r
739\r
740 //\r
741 // DW2\r
742 //\r
743 UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
744 UINT8 Rsvd3;\r
745 UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */\r
746\r
747 //\r
748 // DW3\r
749 //\r
750 UINT32 InputParam1; /* Input Parameter 1 - Big Endian */\r
751\r
752 //\r
753 // DW4\r
754 //\r
755 UINT32 InputParam2; /* Input Parameter 2 - Big Endian */\r
756\r
757 //\r
758 // DW5\r
759 //\r
760 UINT32 InputParam3; /* Input Parameter 3 - Big Endian */\r
761\r
762 //\r
763 // DW6 - DW7\r
764 //\r
765 UINT8 Rsvd4[8];\r
766} UTP_TM_REQ_UPIU;\r
767\r
768//\r
769// UFS 2.0 Spec Section 10.5.9 - UTP Task Management Response UPIU\r
770//\r
771typedef struct {\r
772 //\r
773 // DW0\r
774 //\r
775 UINT8 TransCode:6; /* Transaction Type - 0x24*/\r
776 UINT8 Dd:1;\r
777 UINT8 Hd:1;\r
778 UINT8 Flags;\r
779 UINT8 Lun;\r
780 UINT8 TaskTag; /* Task Tag */\r
781\r
782 //\r
783 // DW1\r
784 //\r
785 UINT8 Rsvd1[2];\r
786 UINT8 Resp; /* Response */\r
787 UINT8 Rsvd2;\r
788\r
789 //\r
790 // DW2\r
791 //\r
792 UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
793 UINT8 Rsvd3;\r
794 UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */\r
795\r
796 //\r
797 // DW3\r
798 //\r
799 UINT32 OutputParam1; /* Output Parameter 1 - Big Endian */\r
800\r
801 //\r
802 // DW4\r
803 //\r
804 UINT32 OutputParam2; /* Output Parameter 2 - Big Endian */\r
805\r
806 //\r
807 // DW5 - DW7\r
808 //\r
809 UINT8 Rsvd4[12];\r
810} UTP_TM_RESP_UPIU;\r
811\r
812//\r
813// UTP Task Management Request Descriptor\r
814//\r
815typedef struct {\r
816 //\r
817 // DW0\r
818 //\r
819 UINT32 Rsvd1:24;\r
820 UINT32 Int:1; /* Interrupt */\r
821 UINT32 Rsvd2:7;\r
822\r
823 //\r
824 // DW1\r
825 //\r
826 UINT32 Rsvd3;\r
827\r
828 //\r
829 // DW2\r
830 //\r
831 UINT32 Ocs:8; /* Overall Command Status */\r
832 UINT32 Rsvd4:24;\r
833\r
834 //\r
835 // DW3\r
836 //\r
837 UINT32 Rsvd5;\r
838\r
839 //\r
840 // DW4 - DW11\r
841 //\r
842 UTP_TM_REQ_UPIU TmReq; /* Task Management Request UPIU */\r
d1102dba 843\r
0591696e
FT		 844 //\r
845 // DW12 - DW19\r
846 //\r
847 UTP_TM_RESP_UPIU TmResp; /* Task Management Response UPIU */\r
848} UTP_TMRD;\r
849\r
850\r
851typedef struct {\r
852 UINT8 Opcode;\r
853 UINT8 DescId;\r
854 UINT8 Index;\r
855 UINT8 Selector;\r
856 UINT16 Rsvd1;\r
857 UINT16 Length;\r
858 UINT32 Value;\r
859 UINT32 Rsvd2;\r
860} UTP_UPIU_TSF;\r
861\r
862//\r
863// UFS 2.0 Spec Section 10.5.10 - UTP Query Request UPIU\r
864//\r
865typedef struct {\r
866 //\r
867 // DW0\r
868 //\r
869 UINT8 TransCode:6; /* Transaction Type - 0x16*/\r
870 UINT8 Dd:1;\r
871 UINT8 Hd:1;\r
872 UINT8 Flags;\r
873 UINT8 Rsvd1;\r
874 UINT8 TaskTag; /* Task Tag */\r
875\r
876 //\r
877 // DW1\r
878 //\r
879 UINT8 Rsvd2;\r
880 UINT8 QueryFunc; /* Query Function */\r
881 UINT8 Rsvd3[2];\r
882\r
883 //\r
884 // DW2\r
885 //\r
886 UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
887 UINT8 Rsvd4;\r
888 UINT16 DataSegLen; /* Data Segment Length - Big Endian */\r
889\r
890 //\r
891 // DW3 - 6\r
892 //\r
893 UTP_UPIU_TSF Tsf; /* Transaction Specific Fields */\r
894\r
895 //\r
896 // DW7\r
897 //\r
898 UINT8 Rsvd5[4];\r
899\r
900 //\r
901 // Data Segment - Data to be transferred\r
902 //\r
903 //UINT8 Data[]; /* Data to be transferred, maximum is 65535 bytes */\r
904} UTP_QUERY_REQ_UPIU;\r
905\r
906#define QUERY_FUNC_STD_READ_REQ 0x01\r
907#define QUERY_FUNC_STD_WRITE_REQ 0x81\r
908\r
909typedef enum {\r
910 UtpQueryFuncOpcodeNop = 0x00,\r
911 UtpQueryFuncOpcodeRdDesc = 0x01,\r
912 UtpQueryFuncOpcodeWrDesc = 0x02,\r
913 UtpQueryFuncOpcodeRdAttr = 0x03,\r
914 UtpQueryFuncOpcodeWrAttr = 0x04,\r
915 UtpQueryFuncOpcodeRdFlag = 0x05,\r
916 UtpQueryFuncOpcodeSetFlag = 0x06,\r
917 UtpQueryFuncOpcodeClrFlag = 0x07,\r
918 UtpQueryFuncOpcodeTogFlag = 0x08\r
919} UTP_QUERY_FUNC_OPCODE;\r
920\r
921//\r
922// UFS 2.0 Spec Section 10.5.11 - UTP Query Response UPIU\r
923//\r
924typedef struct {\r
925 //\r
926 // DW0\r
927 //\r
928 UINT8 TransCode:6; /* Transaction Type - 0x36*/\r
929 UINT8 Dd:1;\r
930 UINT8 Hd:1;\r
931 UINT8 Flags;\r
932 UINT8 Rsvd1;\r
933 UINT8 TaskTag; /* Task Tag */\r
934\r
935 //\r
936 // DW1\r
937 //\r
938 UINT8 Rsvd2;\r
939 UINT8 QueryFunc; /* Query Function */\r
940 UINT8 QueryResp; /* Query Response */\r
941 UINT8 Rsvd3;\r
942\r
943 //\r
944 // DW2\r
945 //\r
946 UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
947 UINT8 DevInfo; /* Device Information */\r
948 UINT16 DataSegLen; /* Data Segment Length - Big Endian */\r
949\r
950 //\r
951 // DW3 - 6\r
952 //\r
953 UTP_UPIU_TSF Tsf; /* Transaction Specific Fields */\r
954\r
955 //\r
956 // DW7\r
957 //\r
958 UINT8 Rsvd4[4];\r
959\r
960 //\r
961 // Data Segment - Data to be transferred\r
962 //\r
963 //UINT8 Data[]; /* Data to be transferred, maximum is 65535 bytes */\r
964} UTP_QUERY_RESP_UPIU;\r
965\r
966typedef enum {\r
967 UfsUtpQueryResponseSuccess = 0x00,\r
968 UfsUtpQueryResponseParamNotReadable = 0xF6,\r
d1102dba 969 UfsUtpQueryResponseParamNotWriteable = 0xF7,\r
0591696e
FT		 970 UfsUtpQueryResponseParamAlreadyWritten = 0xF8,\r
971 UfsUtpQueryResponseInvalidLen = 0xF9,\r
972 UfsUtpQueryResponseInvalidVal = 0xFA,\r
973 UfsUtpQueryResponseInvalidSelector = 0xFB,\r
974 UfsUtpQueryResponseInvalidIndex = 0xFC,\r
975 UfsUtpQueryResponseInvalidIdn = 0xFD,\r
976 UfsUtpQueryResponseInvalidOpc = 0xFE,\r
977 UfsUtpQueryResponseGeneralFailure = 0xFF\r
978} UTP_QUERY_RESP_CODE;\r
979\r
980//\r
981// UFS 2.0 Spec Section 10.5.12 - UTP Reject UPIU\r
982//\r
983typedef struct {\r
984 //\r
985 // DW0\r
986 //\r
987 UINT8 TransCode:6; /* Transaction Type - 0x3F*/\r
988 UINT8 Dd:1;\r
989 UINT8 Hd:1;\r
990 UINT8 Flags;\r
991 UINT8 Lun;\r
992 UINT8 TaskTag; /* Task Tag */\r
993\r
994 //\r
995 // DW1\r
996 //\r
997 UINT8 Rsvd1[2];\r
998 UINT8 Response; /* Response - 0x01 */\r
999 UINT8 Rsvd2;\r
1000\r
1001 //\r
1002 // DW2\r
1003 //\r
1004 UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
1005 UINT8 DevInfo; /* Device Information - 0x00 */\r
1006 UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */\r
1007\r
1008 //\r
1009 // DW3\r
1010 //\r
1011 UINT8 HdrSts; /* Basic Header Status */\r
1012 UINT8 Rsvd3;\r
1013 UINT8 E2ESts; /* End-to-End Status */\r
1014 UINT8 Rsvd4;\r
1015\r
1016 //\r
1017 // DW4 - DW7\r
1018 //\r
1019 UINT8 Rsvd5[16];\r
1020} UTP_REJ_UPIU;\r
1021\r
1022//\r
1023// UFS 2.0 Spec Section 10.5.13 - UTP NOP OUT UPIU\r
1024//\r
1025typedef struct {\r
1026 //\r
1027 // DW0\r
1028 //\r
1029 UINT8 TransCode:6; /* Transaction Type - 0x00*/\r
1030 UINT8 Dd:1;\r
1031 UINT8 Hd:1;\r
1032 UINT8 Flags;\r
1033 UINT8 Rsvd1;\r
1034 UINT8 TaskTag; /* Task Tag */\r
1035\r
1036 //\r
1037 // DW1\r
1038 //\r
1039 UINT8 Rsvd2[4];\r
1040\r
1041 //\r
1042 // DW2\r
1043 //\r
1044 UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
1045 UINT8 Rsvd3;\r
1046 UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */\r
1047\r
1048 //\r
1049 // DW3 - DW7\r
1050 //\r
1051 UINT8 Rsvd4[20];\r
1052} UTP_NOP_OUT_UPIU;\r
1053\r
1054//\r
1055// UFS 2.0 Spec Section 10.5.14 - UTP NOP IN UPIU\r
1056//\r
1057typedef struct {\r
1058 //\r
1059 // DW0\r
1060 //\r
1061 UINT8 TransCode:6; /* Transaction Type - 0x20*/\r
1062 UINT8 Dd:1;\r
1063 UINT8 Hd:1;\r
1064 UINT8 Flags;\r
1065 UINT8 Rsvd1;\r
1066 UINT8 TaskTag; /* Task Tag */\r
1067\r
1068 //\r
1069 // DW1\r
1070 //\r
1071 UINT8 Rsvd2[2];\r
1072 UINT8 Resp; /* Response - 0x00 */\r
1073 UINT8 Rsvd3;\r
1074\r
1075 //\r
1076 // DW2\r
1077 //\r
1078 UINT8 EhsLen; /* Total EHS Length - 0x00 */\r
1079 UINT8 DevInfo; /* Device Information - 0x00 */\r
1080 UINT16 DataSegLen; /* Data Segment Length - Big Endian - 0x0000 */\r
1081\r
1082 //\r
1083 // DW3 - DW7\r
1084 //\r
1085 UINT8 Rsvd4[20];\r
1086} UTP_NOP_IN_UPIU;\r
1087\r
1088//\r
1089// UFS Descriptors\r
1090//\r
1091typedef enum {\r
1092 UfsDeviceDesc = 0x00,\r
1093 UfsConfigDesc = 0x01,\r
1094 UfsUnitDesc = 0x02,\r
1095 UfsInterConnDesc = 0x04,\r
1096 UfsStringDesc = 0x05,\r
1097 UfsGeometryDesc = 0x07,\r
1098 UfsPowerDesc = 0x08\r
1099} UFS_DESC_IDN;\r
1100\r
1101//\r
1102// UFS 2.0 Spec Section 14.1.6.2 - Device Descriptor\r
1103//\r
1104typedef struct {\r
1105 UINT8 Length;\r
1106 UINT8 DescType;\r
1107 UINT8 Device;\r
1108 UINT8 DevClass;\r
1109 UINT8 DevSubClass;\r
1110 UINT8 Protocol;\r
1111 UINT8 NumLun;\r
1112 UINT8 NumWLun;\r
1113 UINT8 BootEn;\r
1114 UINT8 DescAccessEn;\r
1115 UINT8 InitPowerMode;\r
1116 UINT8 HighPriorityLun;\r
1117 UINT8 SecureRemovalType;\r
1118 UINT8 SecurityLun;\r
1119 UINT8 BgOpsTermLat;\r
1120 UINT8 InitActiveIccLevel;\r
1121 UINT16 SpecVersion;\r
1122 UINT16 ManufactureDate;\r
1123 UINT8 ManufacturerName;\r
1124 UINT8 ProductName;\r
1125 UINT8 SerialName;\r
1126 UINT8 OemId;\r
1127 UINT16 ManufacturerId;\r
1128 UINT8 Ud0BaseOffset;\r
1129 UINT8 Ud0ConfParamLen;\r
1130 UINT8 DevRttCap;\r
1131 UINT16 PeriodicRtcUpdate;\r
1132 UINT8 Rsvd1[17];\r
1133 UINT8 Rsvd2[16];\r
1134} UFS_DEV_DESC;\r
1135\r
1136typedef struct {\r
1137 UINT8 Length;\r
1138 UINT8 DescType;\r
1139 UINT8 Rsvd1;\r
1140 UINT8 BootEn;\r
1141 UINT8 DescAccessEn;\r
1142 UINT8 InitPowerMode;\r
1143 UINT8 HighPriorityLun;\r
1144 UINT8 SecureRemovalType;\r
1145 UINT8 InitActiveIccLevel;\r
1146 UINT16 PeriodicRtcUpdate;\r
1147 UINT8 Rsvd2[5];\r
1148} UFS_CONFIG_DESC_GEN_HEADER;\r
1149\r
1150typedef struct {\r
1151 UINT8 LunEn;\r
1152 UINT8 BootLunId;\r
1153 UINT8 LunWriteProt;\r
1154 UINT8 MemType;\r
1155 UINT32 NumAllocUnits;\r
1156 UINT8 DataReliability;\r
1157 UINT8 LogicBlkSize;\r
1158 UINT8 ProvisionType;\r
1159 UINT16 CtxCap;\r
1160 UINT8 Rsvd1[3];\r
1161} UFS_UNIT_DESC_CONFIG_PARAMS;\r
1162\r
1163//\r
1164// UFS 2.0 Spec Section 14.1.6.3 - Configuration Descriptor\r
1165//\r
1166typedef struct {\r
1167 UFS_CONFIG_DESC_GEN_HEADER Header;\r
1168 UFS_UNIT_DESC_CONFIG_PARAMS UnitDescConfParams[8];\r
1169} UFS_CONFIG_DESC;\r
1170\r
1171//\r
1172// UFS 2.0 Spec Section 14.1.6.4 - Geometry Descriptor\r
1173//\r
1174typedef struct {\r
1175 UINT8 Length;\r
1176 UINT8 DescType;\r
1177 UINT8 MediaTech;\r
1178 UINT8 Rsvd1;\r
1179 UINT64 TotalRawDevCapacity;\r
1180 UINT8 Rsvd2;\r
1181 UINT32 SegSize;\r
1182 UINT8 AllocUnitSize;\r
1183 UINT8 MinAddrBlkSize;\r
1184 UINT8 OptReadBlkSize;\r
1185 UINT8 OptWriteBlkSize;\r
1186 UINT8 MaxInBufSize;\r
1187 UINT8 MaxOutBufSize;\r
1188 UINT8 RpmbRwSize;\r
1189 UINT8 Rsvd3;\r
1190 UINT8 DataOrder;\r
1191 UINT8 MaxCtxIdNum;\r
1192 UINT8 SysDataTagUnitSize;\r
1193 UINT8 SysDataResUnitSize;\r
1194 UINT8 SupSecRemovalTypes;\r
1195 UINT16 SupMemTypes;\r
1196 UINT32 SysCodeMaxNumAllocUnits;\r
1197 UINT16 SupCodeCapAdjFac;\r
1198 UINT32 NonPersMaxNumAllocUnits;\r
1199 UINT16 NonPersCapAdjFac;\r
1200 UINT32 Enhance1MaxNumAllocUnits;\r
1201 UINT16 Enhance1CapAdjFac;\r
1202 UINT32 Enhance2MaxNumAllocUnits;\r
1203 UINT16 Enhance2CapAdjFac;\r
1204 UINT32 Enhance3MaxNumAllocUnits;\r
1205 UINT16 Enhance3CapAdjFac;\r
1206 UINT32 Enhance4MaxNumAllocUnits;\r
1207 UINT16 Enhance4CapAdjFac;\r
1208} UFS_GEOMETRY_DESC;\r
1209\r
1210//\r
1211// UFS 2.0 Spec Section 14.1.6.5 - Unit Descriptor\r
1212//\r
1213typedef struct {\r
1214 UINT8 Length;\r
1215 UINT8 DescType;\r
1216 UINT8 UnitIdx;\r
1217 UINT8 LunEn;\r
1218 UINT8 BootLunId;\r
1219 UINT8 LunWriteProt;\r
1220 UINT8 LunQueueDep;\r
1221 UINT8 Rsvd1;\r
1222 UINT8 MemType;\r
1223 UINT8 DataReliability;\r
1224 UINT8 LogicBlkSize;\r
1225 UINT64 LogicBlkCount;\r
1226 UINT32 EraseBlkSize;\r
1227 UINT8 ProvisionType;\r
1228 UINT64 PhyMemResCount;\r
1229 UINT16 CtxCap;\r
1230 UINT8 LargeUnitGranularity;\r
1231} UFS_UNIT_DESC;\r
1232\r
1233//\r
1234// UFS 2.0 Spec Section 14.1.6.6 - RPMB Unit Descriptor\r
1235//\r
1236typedef struct {\r
1237 UINT8 Length;\r
1238 UINT8 DescType;\r
1239 UINT8 UnitIdx;\r
1240 UINT8 LunEn;\r
1241 UINT8 BootLunId;\r
1242 UINT8 LunWriteProt;\r
1243 UINT8 LunQueueDep;\r
1244 UINT8 Rsvd1;\r
1245 UINT8 MemType;\r
1246 UINT8 Rsvd2;\r
1247 UINT8 LogicBlkSize;\r
1248 UINT64 LogicBlkCount;\r
1249 UINT32 EraseBlkSize;\r
1250 UINT8 ProvisionType;\r
1251 UINT64 PhyMemResCount;\r
1252 UINT8 Rsvd3[3];\r
1253} UFS_RPMB_UNIT_DESC;\r
1254\r
1255typedef struct {\r
1256 UINT16 Value:10;\r
1257 UINT16 Rsvd1:4;\r
1258 UINT16 Unit:2;\r
1259} UFS_POWER_PARAM_ELEMENT;\r
1260\r
1261//\r
1262// UFS 2.0 Spec Section 14.1.6.7 - Power Parameter Descriptor\r
1263//\r
1264typedef struct {\r
1265 UINT8 Length;\r
1266 UINT8 DescType;\r
1267 UFS_POWER_PARAM_ELEMENT ActiveIccLevelVcc[16];\r
1268 UFS_POWER_PARAM_ELEMENT ActiveIccLevelVccQ[16];\r
1269 UFS_POWER_PARAM_ELEMENT ActiveIccLevelVccQ2[16];\r
1270} UFS_POWER_DESC;\r
1271\r
1272//\r
1273// UFS 2.0 Spec Section 14.1.6.8 - InterConnect Descriptor\r
1274//\r
1275typedef struct {\r
1276 UINT8 Length;\r
1277 UINT8 DescType;\r
1278 UINT16 UniProVer;\r
1279 UINT16 MphyVer;\r
1280} UFS_INTER_CONNECT_DESC;\r
1281\r
1282//\r
1283// UFS 2.0 Spec Section 14.1.6.9 - 14.1.6.12 - String Descriptor\r
1284//\r
1285typedef struct {\r
1286 UINT8 Length;\r
1287 UINT8 DescType;\r
1288 CHAR16 Unicode[126];\r
1289} UFS_STRING_DESC;\r
1290\r
1291//\r
1292// UFS 2.0 Spec Section 14.2 - Flags\r
1293//\r
1294typedef enum {\r
1295 UfsFlagDevInit = 0x01,\r
1296 UfsFlagPermWpEn = 0x02,\r
1297 UfsFlagPowerOnWpEn = 0x03,\r
1298 UfsFlagBgOpsEn = 0x04,\r
1299 UfsFlagPurgeEn = 0x06,\r
1300 UfsFlagPhyResRemoval = 0x08,\r
1301 UfsFlagBusyRtc = 0x09,\r
d1102dba 1302 UfsFlagPermDisFwUpdate = 0x0B\r
0591696e
FT		 1303} UFS_FLAGS_IDN;\r
1304\r
1305//\r
1306// UFS 2.0 Spec Section 14.2 - Attributes\r
1307//\r
1308typedef enum {\r
1309 UfsAttrBootLunEn = 0x00,\r
1310 UfsAttrCurPowerMode = 0x02,\r
1311 UfsAttrActiveIccLevel = 0x03,\r
1312 UfsAttrOutOfOrderDataEn = 0x04,\r
1313 UfsAttrBgOpStatus = 0x05,\r
1314 UfsAttrPurgeStatus = 0x06,\r
1315 UfsAttrMaxDataInSize = 0x07,\r
1316 UfsAttrMaxDataOutSize = 0x08,\r
1317 UfsAttrDynCapNeeded = 0x09,\r
1318 UfsAttrRefClkFreq = 0x0a,\r
1319 UfsAttrConfigDescLock = 0x0b,\r
1320 UfsAttrMaxNumOfRtt = 0x0c,\r
1321 UfsAttrExceptionEvtCtrl = 0x0d,\r
1322 UfsAttrExceptionEvtSts = 0x0e,\r
1323 UfsAttrSecondsPassed = 0x0f,\r
1324 UfsAttrContextConf = 0x10,\r
1325 UfsAttrCorrPrgBlkNum = 0x11\r
1326} UFS_ATTR_IDN;\r
1327\r
1328typedef enum {\r
1329 UfsNoData = 0,\r
1330 UfsDataOut = 1,\r
1331 UfsDataIn = 2,\r
1332 UfsDdReserved\r
1333} UFS_DATA_DIRECTION;\r
1334\r
1335\r
1336#pragma pack()\r
1337\r
1338#endif\r
1339\r
EFI Development Kit II mirror for PVE