[mirror_edk2.git] / MdeModulePkg / Core / DxeIplPeim / X64 / VirtualMemory.c

/** @file\r
  x64 Virtual Memory Management Services in the form of an IA-32 driver.  \r
  Used to establish a 1:1 Virtual to Physical Mapping that is required to\r
  enter Long Mode (x64 64-bit mode).\r
\r
  While we make a 1:1 mapping (identity mapping) for all physical pages \r
  we still need to use the MTRR's to ensure that the cachability attirbutes\r
  for all memory regions is correct.\r
\r
  The basic idea is to use 2MB page table entries where ever possible. If\r
  more granularity of cachability is required then 4K page tables are used.\r
\r
  References:\r
    1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
    2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
    3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
\r
Copyright (c) 2006 - 2008, Intel Corporation. <BR>\r
All rights reserved. This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/  \r
\r
#include "DxeIpl.h"\r
#include "VirtualMemory.h"\r
\r
/**\r
  Allocates and fills in the Page Directory and Page Table Entries to\r
  establish a 1:1 Virtual to Physical mapping.\r
\r
  @param  NumberOfProcessorPhysicalAddressBits  Number of processor address bits \r
                                                to use. Limits the number of page \r
                                                table entries  to the physical \r
                                                address space. \r
\r
  @return The address of 4 level page map.\r
\r
**/\r
UINTN\r
CreateIdentityMappingPageTables (\r
  VOID\r
  )\r
{  \r
  UINT8                                         PhysicalAddressBits;\r
  EFI_PHYSICAL_ADDRESS                          PageAddress;\r
  UINTN                                         IndexOfPml4Entries;\r
  UINTN                                         IndexOfPdpEntries;\r
  UINTN                                         IndexOfPageDirectoryEntries;\r
  UINTN                                         NumberOfPml4EntriesNeeded;\r
  UINTN                                         NumberOfPdpEntriesNeeded;\r
  PAGE_MAP_AND_DIRECTORY_POINTER                *PageMapLevel4Entry;\r
  PAGE_MAP_AND_DIRECTORY_POINTER                *PageMap;\r
  PAGE_MAP_AND_DIRECTORY_POINTER                *PageDirectoryPointerEntry;\r
  PAGE_TABLE_ENTRY                              *PageDirectoryEntry;\r
  UINTN                                         TotalPagesNum;\r
  UINTN                                         BigPageAddress;\r
  VOID                                          *Hob;\r
\r
  //\r
  // Get physical address bits supported from CPU HOB.\r
  //\r
  PhysicalAddressBits = 36;\r
  \r
  Hob = GetFirstHob (EFI_HOB_TYPE_CPU);\r
  if (Hob != NULL) {\r
    PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;\r
  }\r
\r
  //\r
  // Calculate the table entries needed.\r
  //\r
  if (PhysicalAddressBits <= 39 ) {\r
    NumberOfPml4EntriesNeeded = 1;\r
    NumberOfPdpEntriesNeeded =  LShiftU64 (1, (PhysicalAddressBits - 30));\r
  } else {\r
    NumberOfPml4EntriesNeeded = LShiftU64 (1, (PhysicalAddressBits - 39));\r
    NumberOfPdpEntriesNeeded = 512;\r
  }\r
\r
  //\r
  // Pre-allocate big pages to avoid later allocations. \r
  //\r
  TotalPagesNum = (NumberOfPdpEntriesNeeded + 1) * NumberOfPml4EntriesNeeded + 1;\r
  BigPageAddress = (UINTN) AllocatePages (TotalPagesNum);\r
  ASSERT (BigPageAddress != 0);\r
\r
  //\r
  // By architecture only one PageMapLevel4 exists - so lets allocate storage for it.\r
  //\r
  PageMap         = (VOID *) BigPageAddress;\r
  BigPageAddress += EFI_PAGE_SIZE;\r
\r
  PageMapLevel4Entry = PageMap;\r
  PageAddress        = 0;\r
  for (IndexOfPml4Entries = 0; IndexOfPml4Entries < NumberOfPml4EntriesNeeded; IndexOfPml4Entries++, PageMapLevel4Entry++) {\r
    //\r
    // Each PML4 entry points to a page of Page Directory Pointer entires.\r
    // So lets allocate space for them and fill them in in the IndexOfPdpEntries loop.\r
    //\r
    PageDirectoryPointerEntry = (VOID *) BigPageAddress;\r
    BigPageAddress += EFI_PAGE_SIZE;\r
\r
    //\r
    // Make a PML4 Entry\r
    //\r
    PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry;\r
    PageMapLevel4Entry->Bits.ReadWrite = 1;\r
    PageMapLevel4Entry->Bits.Present = 1;\r
\r
    for (IndexOfPdpEntries = 0; IndexOfPdpEntries < NumberOfPdpEntriesNeeded; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {\r
      //\r
      // Each Directory Pointer entries points to a page of Page Directory entires.\r
      // So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.\r
      //       \r
      PageDirectoryEntry = (VOID *) BigPageAddress;\r
      BigPageAddress += EFI_PAGE_SIZE;\r
\r
      //\r
      // Fill in a Page Directory Pointer Entries\r
      //\r
      PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry;\r
      PageDirectoryPointerEntry->Bits.ReadWrite = 1;\r
      PageDirectoryPointerEntry->Bits.Present = 1;\r
\r
      for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += 0x200000) {\r
        //\r
        // Fill in the Page Directory entries\r
        //\r
        PageDirectoryEntry->Uint64 = (UINT64)PageAddress;\r
        PageDirectoryEntry->Bits.ReadWrite = 1;\r
        PageDirectoryEntry->Bits.Present = 1;\r
        PageDirectoryEntry->Bits.MustBe1 = 1;\r
\r
      }\r
    }\r
  }\r
\r
  //\r
  // For the PML4 entries we are not using fill in a null entry.\r
  // For now we just copy the first entry.\r
  //\r
  for (; IndexOfPml4Entries < 512; IndexOfPml4Entries++, PageMapLevel4Entry++) {\r
     CopyMem (\r
       PageMapLevel4Entry,\r
       PageMap,\r
       sizeof (PAGE_MAP_AND_DIRECTORY_POINTER)\r
       );\r
  }\r
\r
  return (UINTN)PageMap;\r
}\r
\r
Commit	Line	Data
f3b33289	1	/** @file\r
	2	x64 Virtual Memory Management Services in the form of an IA-32 driver. \r
	3	Used to establish a 1:1 Virtual to Physical Mapping that is required to\r
	4	enter Long Mode (x64 64-bit mode).\r
	5	\r
	6	While we make a 1:1 mapping (identity mapping) for all physical pages \r
	7	we still need to use the MTRR's to ensure that the cachability attirbutes\r
	8	for all memory regions is correct.\r
	9	\r
	10	The basic idea is to use 2MB page table entries where ever possible. If\r
	11	more granularity of cachability is required then 4K page tables are used.\r
	12	\r
	13	References:\r
	14	1) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
	15	2) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
	16	3) IA-32 Intel(R) Atchitecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
	17	\r
	18	Copyright (c) 2006 - 2008, Intel Corporation. <BR>\r
	19	All rights reserved. This program and the accompanying materials\r
	20	are licensed and made available under the terms and conditions of the BSD License\r
	21	which accompanies this distribution. The full text of the license may be found at\r
	22	http://opensource.org/licenses/bsd-license.php\r
	23	\r
	24	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	25	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	26	\r
	27	**/ \r
	28	\r
	29	#include "DxeIpl.h"\r
	30	#include "VirtualMemory.h"\r
	31	\r
f3b33289	32	/**\r
	33	Allocates and fills in the Page Directory and Page Table Entries to\r
	34	establish a 1:1 Virtual to Physical mapping.\r
	35	\r
	36	@param NumberOfProcessorPhysicalAddressBits Number of processor address bits \r
	37	to use. Limits the number of page \r
	38	table entries to the physical \r
	39	address space. \r
	40	\r
48557c65	41	@return The address of 4 level page map.\r
f3b33289	42	\r
	43	**/\r
	44	UINTN\r
	45	CreateIdentityMappingPageTables (\r
	46	VOID\r
	47	)\r
	48	{ \r
	49	UINT8 PhysicalAddressBits;\r
	50	EFI_PHYSICAL_ADDRESS PageAddress;\r
	51	UINTN IndexOfPml4Entries;\r
	52	UINTN IndexOfPdpEntries;\r
	53	UINTN IndexOfPageDirectoryEntries;\r
	54	UINTN NumberOfPml4EntriesNeeded;\r
	55	UINTN NumberOfPdpEntriesNeeded;\r
	56	PAGE_MAP_AND_DIRECTORY_POINTER *PageMapLevel4Entry;\r
	57	PAGE_MAP_AND_DIRECTORY_POINTER *PageMap;\r
	58	PAGE_MAP_AND_DIRECTORY_POINTER *PageDirectoryPointerEntry;\r
	59	PAGE_TABLE_ENTRY *PageDirectoryEntry;\r
	60	UINTN TotalPagesNum;\r
	61	UINTN BigPageAddress;\r
	62	VOID *Hob;\r
	63	\r
	64	//\r
	65	// Get physical address bits supported from CPU HOB.\r
	66	//\r
	67	PhysicalAddressBits = 36;\r
	68	\r
	69	Hob = GetFirstHob (EFI_HOB_TYPE_CPU);\r
	70	if (Hob != NULL) {\r
48557c65	71	PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;\r
f3b33289	72	}\r
	73	\r
	74	//\r
	75	// Calculate the table entries needed.\r
	76	//\r
	77	if (PhysicalAddressBits <= 39 ) {\r
	78	NumberOfPml4EntriesNeeded = 1;\r
	79	NumberOfPdpEntriesNeeded = LShiftU64 (1, (PhysicalAddressBits - 30));\r
	80	} else {\r
	81	NumberOfPml4EntriesNeeded = LShiftU64 (1, (PhysicalAddressBits - 39));\r
	82	NumberOfPdpEntriesNeeded = 512;\r
	83	}\r
	84	\r
	85	//\r
	86	// Pre-allocate big pages to avoid later allocations. \r
	87	//\r
	88	TotalPagesNum = (NumberOfPdpEntriesNeeded + 1) * NumberOfPml4EntriesNeeded + 1;\r
	89	BigPageAddress = (UINTN) AllocatePages (TotalPagesNum);\r
	90	ASSERT (BigPageAddress != 0);\r
	91	\r
	92	//\r
	93	// By architecture only one PageMapLevel4 exists - so lets allocate storage for it.\r
	94	//\r
	95	PageMap = (VOID *) BigPageAddress;\r
	96	BigPageAddress += EFI_PAGE_SIZE;\r
	97	\r
	98	PageMapLevel4Entry = PageMap;\r
	99	PageAddress = 0;\r
	100	for (IndexOfPml4Entries = 0; IndexOfPml4Entries < NumberOfPml4EntriesNeeded; IndexOfPml4Entries++, PageMapLevel4Entry++) {\r
	101	//\r
	102	// Each PML4 entry points to a page of Page Directory Pointer entires.\r
	103	// So lets allocate space for them and fill them in in the IndexOfPdpEntries loop.\r
	104	//\r
	105	PageDirectoryPointerEntry = (VOID *) BigPageAddress;\r
	106	BigPageAddress += EFI_PAGE_SIZE;\r
	107	\r
	108	//\r
	109	// Make a PML4 Entry\r
	110	//\r
	111	PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry;\r
	112	PageMapLevel4Entry->Bits.ReadWrite = 1;\r
	113	PageMapLevel4Entry->Bits.Present = 1;\r
	114	\r
	115	for (IndexOfPdpEntries = 0; IndexOfPdpEntries < NumberOfPdpEntriesNeeded; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {\r
	116	//\r
	117	// Each Directory Pointer entries points to a page of Page Directory entires.\r
	118	// So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.\r
	119	// \r
	120	PageDirectoryEntry = (VOID *) BigPageAddress;\r
	121	BigPageAddress += EFI_PAGE_SIZE;\r
	122	\r
	123	//\r
	124	// Fill in a Page Directory Pointer Entries\r
	125	//\r
	126	PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry;\r
	127	PageDirectoryPointerEntry->Bits.ReadWrite = 1;\r
	128	PageDirectoryPointerEntry->Bits.Present = 1;\r
	129	\r
	130	for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += 0x200000) {\r
	131	//\r
	132	// Fill in the Page Directory entries\r
	133	//\r
	134	PageDirectoryEntry->Uint64 = (UINT64)PageAddress;\r
	135	PageDirectoryEntry->Bits.ReadWrite = 1;\r
136	PageDirectoryEntry->Bits.Present = 1;\r
137	PageDirectoryEntry->Bits.MustBe1 = 1;\r
138	\r
139	}\r
140	}\r
141	}\r
142	\r
143	//\r
144	// For the PML4 entries we are not using fill in a null entry.\r
145	// For now we just copy the first entry.\r
146	//\r
147	for (; IndexOfPml4Entries < 512; IndexOfPml4Entries++, PageMapLevel4Entry++) {\r
148	CopyMem (\r
149	PageMapLevel4Entry,\r
150	PageMap,\r
151	sizeof (PAGE_MAP_AND_DIRECTORY_POINTER)\r
152	);\r
153	}\r
154	\r
155	return (UINTN)PageMap;\r
156	}\r
157	\r