[mirror_edk2.git] / MdeModulePkg / Core / DxeIplPeim / X64 / VirtualMemory.c

/** @file\r
  x64 Virtual Memory Management Services in the form of an IA-32 driver.  \r
  Used to establish a 1:1 Virtual to Physical Mapping that is required to\r
  enter Long Mode (x64 64-bit mode).\r
\r
  While we make a 1:1 mapping (identity mapping) for all physical pages \r
  we still need to use the MTRR's to ensure that the cachability attributes\r
  for all memory regions is correct.\r
\r
  The basic idea is to use 2MB page table entries where ever possible. If\r
  more granularity of cachability is required then 4K page tables are used.\r
\r
  References:\r
    1) IA-32 Intel(R) Architecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
    2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
    3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
\r
Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
This program and the accompanying materials\r
are licensed and made available under the terms and conditions of the BSD License\r
which accompanies this distribution.  The full text of the license may be found at\r
http://opensource.org/licenses/bsd-license.php\r
\r
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/  \r
\r
#include "DxeIpl.h"\r
#include "VirtualMemory.h"\r
\r
/**\r
  Allocates and fills in the Page Directory and Page Table Entries to\r
  establish a 1:1 Virtual to Physical mapping.\r
\r
  @param  NumberOfProcessorPhysicalAddressBits  Number of processor address bits \r
                                                to use. Limits the number of page \r
                                                table entries  to the physical \r
                                                address space. \r
\r
  @return The address of 4 level page map.\r
\r
**/\r
UINTN\r
CreateIdentityMappingPageTables (\r
  VOID\r
  )\r
{  \r
  UINT32                                        RegEax;\r
  UINT32                                        RegEdx;\r
  UINT8                                         PhysicalAddressBits;\r
  EFI_PHYSICAL_ADDRESS                          PageAddress;\r
  UINTN                                         IndexOfPml4Entries;\r
  UINTN                                         IndexOfPdpEntries;\r
  UINTN                                         IndexOfPageDirectoryEntries;\r
  UINT32                                        NumberOfPml4EntriesNeeded;\r
  UINT32                                        NumberOfPdpEntriesNeeded;\r
  PAGE_MAP_AND_DIRECTORY_POINTER                *PageMapLevel4Entry;\r
  PAGE_MAP_AND_DIRECTORY_POINTER                *PageMap;\r
  PAGE_MAP_AND_DIRECTORY_POINTER                *PageDirectoryPointerEntry;\r
  PAGE_TABLE_ENTRY                              *PageDirectoryEntry;\r
  UINTN                                         TotalPagesNum;\r
  UINTN                                         BigPageAddress;\r
  VOID                                          *Hob;\r
  BOOLEAN                                       Page1GSupport;\r
  PAGE_TABLE_1G_ENTRY                           *PageDirectory1GEntry;\r
\r
  Page1GSupport = FALSE;\r
  AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
  if (RegEax >= 0x80000001) {\r
    AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);\r
    if ((RegEdx & BIT26) != 0) {\r
      Page1GSupport = TRUE;\r
    }\r
  }\r
\r
  //\r
  // Get physical address bits supported.\r
  //\r
  Hob = GetFirstHob (EFI_HOB_TYPE_CPU);\r
  if (Hob != NULL) {\r
    PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;\r
  } else {\r
    AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
    if (RegEax >= 0x80000008) {\r
      AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
      PhysicalAddressBits = (UINT8) RegEax;\r
    } else {\r
      PhysicalAddressBits = 36;\r
    }\r
  }\r
\r
  //\r
  // IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.\r
  //\r
  ASSERT (PhysicalAddressBits <= 52);\r
  if (PhysicalAddressBits > 48) {\r
    PhysicalAddressBits = 48;\r
  }\r
\r
  //\r
  // Calculate the table entries needed.\r
  //\r
  if (PhysicalAddressBits <= 39 ) {\r
    NumberOfPml4EntriesNeeded = 1;\r
    NumberOfPdpEntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 30));\r
  } else {\r
    NumberOfPml4EntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 39));\r
    NumberOfPdpEntriesNeeded = 512;\r
  }\r
\r
  //\r
  // Pre-allocate big pages to avoid later allocations. \r
  //\r
  if (!Page1GSupport) {\r
    TotalPagesNum = (NumberOfPdpEntriesNeeded + 1) * NumberOfPml4EntriesNeeded + 1;\r
  } else {\r
    TotalPagesNum = NumberOfPml4EntriesNeeded + 1;\r
  }\r
  BigPageAddress = (UINTN) AllocatePages (TotalPagesNum);\r
  ASSERT (BigPageAddress != 0);\r
\r
  //\r
  // By architecture only one PageMapLevel4 exists - so lets allocate storage for it.\r
  //\r
  PageMap         = (VOID *) BigPageAddress;\r
  BigPageAddress += SIZE_4KB;\r
\r
  PageMapLevel4Entry = PageMap;\r
  PageAddress        = 0;\r
  for (IndexOfPml4Entries = 0; IndexOfPml4Entries < NumberOfPml4EntriesNeeded; IndexOfPml4Entries++, PageMapLevel4Entry++) {\r
    //\r
    // Each PML4 entry points to a page of Page Directory Pointer entires.\r
    // So lets allocate space for them and fill them in in the IndexOfPdpEntries loop.\r
    //\r
    PageDirectoryPointerEntry = (VOID *) BigPageAddress;\r
    BigPageAddress += SIZE_4KB;\r
\r
    //\r
    // Make a PML4 Entry\r
    //\r
    PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry;\r
    PageMapLevel4Entry->Bits.ReadWrite = 1;\r
    PageMapLevel4Entry->Bits.Present = 1;\r
\r
    if (Page1GSupport) {\r
      PageDirectory1GEntry = (VOID *) BigPageAddress;\r
      BigPageAddress += SIZE_4KB;\r
    \r
      for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress += SIZE_1GB) {\r
        //\r
        // Fill in the Page Directory entries\r
        //\r
        PageDirectory1GEntry->Uint64 = (UINT64)PageAddress;\r
        PageDirectory1GEntry->Bits.ReadWrite = 1;\r
        PageDirectory1GEntry->Bits.Present = 1;\r
        PageDirectory1GEntry->Bits.MustBe1 = 1;\r
      }\r
    } else {\r
      for (IndexOfPdpEntries = 0; IndexOfPdpEntries < NumberOfPdpEntriesNeeded; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {\r
        //\r
        // Each Directory Pointer entries points to a page of Page Directory entires.\r
        // So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.\r
        //       \r
        PageDirectoryEntry = (VOID *) BigPageAddress;\r
        BigPageAddress += SIZE_4KB;\r
\r
        //\r
        // Fill in a Page Directory Pointer Entries\r
        //\r
        PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry;\r
        PageDirectoryPointerEntry->Bits.ReadWrite = 1;\r
        PageDirectoryPointerEntry->Bits.Present = 1;\r
\r
        for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += SIZE_2MB) {\r
          //\r
          // Fill in the Page Directory entries\r
          //\r
          PageDirectoryEntry->Uint64 = (UINT64)PageAddress;\r
          PageDirectoryEntry->Bits.ReadWrite = 1;\r
          PageDirectoryEntry->Bits.Present = 1;\r
          PageDirectoryEntry->Bits.MustBe1 = 1;\r
        }\r
      }\r
\r
      for (; IndexOfPdpEntries < 512; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {\r
        ZeroMem (\r
          PageDirectoryPointerEntry,\r
          sizeof(PAGE_MAP_AND_DIRECTORY_POINTER)\r
          );\r
      }\r
    }\r
  }\r
\r
  //\r
  // For the PML4 entries we are not using fill in a null entry.\r
  //\r
  for (; IndexOfPml4Entries < 512; IndexOfPml4Entries++, PageMapLevel4Entry++) {\r
    ZeroMem (\r
      PageMapLevel4Entry,\r
      sizeof (PAGE_MAP_AND_DIRECTORY_POINTER)\r
      );\r
  }\r
\r
  return (UINTN)PageMap;\r
}\r
\r
Commit	Line	Data
f3b33289	1	/** @file\r
	2	x64 Virtual Memory Management Services in the form of an IA-32 driver. \r
	3	Used to establish a 1:1 Virtual to Physical Mapping that is required to\r
	4	enter Long Mode (x64 64-bit mode).\r
	5	\r
	6	While we make a 1:1 mapping (identity mapping) for all physical pages \r
4140a663	7	we still need to use the MTRR's to ensure that the cachability attributes\r
f3b33289	8	for all memory regions is correct.\r
	9	\r
	10	The basic idea is to use 2MB page table entries where ever possible. If\r
	11	more granularity of cachability is required then 4K page tables are used.\r
	12	\r
	13	References:\r
4140a663	14	1) IA-32 Intel(R) Architecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
	15	2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
	16	3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
f3b33289	17	\r
c56b6566	18	Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
cd5ebaa0	19	This program and the accompanying materials\r
f3b33289	20	are licensed and made available under the terms and conditions of the BSD License\r
	21	which accompanies this distribution. The full text of the license may be found at\r
	22	http://opensource.org/licenses/bsd-license.php\r
	23	\r
	24	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	25	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	26	\r
	27	**/ \r
	28	\r
	29	#include "DxeIpl.h"\r
	30	#include "VirtualMemory.h"\r
	31	\r
f3b33289	32	/**\r
	33	Allocates and fills in the Page Directory and Page Table Entries to\r
	34	establish a 1:1 Virtual to Physical mapping.\r
	35	\r
	36	@param NumberOfProcessorPhysicalAddressBits Number of processor address bits \r
	37	to use. Limits the number of page \r
	38	table entries to the physical \r
	39	address space. \r
	40	\r
48557c65	41	@return The address of 4 level page map.\r
f3b33289	42	\r
	43	**/\r
	44	UINTN\r
	45	CreateIdentityMappingPageTables (\r
	46	VOID\r
	47	)\r
	48	{ \r
c56b6566 JY	49	UINT32 RegEax;\r
c56b6566 JY	50	UINT32 RegEdx;\r
f3b33289	51	UINT8 PhysicalAddressBits;\r
	52	EFI_PHYSICAL_ADDRESS PageAddress;\r
	53	UINTN IndexOfPml4Entries;\r
	54	UINTN IndexOfPdpEntries;\r
	55	UINTN IndexOfPageDirectoryEntries;\r
4140a663	56	UINT32 NumberOfPml4EntriesNeeded;\r
4140a663	57	UINT32 NumberOfPdpEntriesNeeded;\r
f3b33289	58	PAGE_MAP_AND_DIRECTORY_POINTER *PageMapLevel4Entry;\r
	59	PAGE_MAP_AND_DIRECTORY_POINTER *PageMap;\r
	60	PAGE_MAP_AND_DIRECTORY_POINTER *PageDirectoryPointerEntry;\r
	61	PAGE_TABLE_ENTRY *PageDirectoryEntry;\r
	62	UINTN TotalPagesNum;\r
	63	UINTN BigPageAddress;\r
	64	VOID *Hob;\r
c56b6566 JY	65	BOOLEAN Page1GSupport;\r
	66	PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry;\r
	67	\r
	68	Page1GSupport = FALSE;\r
	69	AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
	70	if (RegEax >= 0x80000001) {\r
	71	AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);\r
	72	if ((RegEdx & BIT26) != 0) {\r
	73	Page1GSupport = TRUE;\r
	74	}\r
	75	}\r
f3b33289	76	\r
f3b33289	77	//\r
c56b6566	78	// Get physical address bits supported.\r
f3b33289	79	//\r
f3b33289	80	Hob = GetFirstHob (EFI_HOB_TYPE_CPU);\r
f3b33289	81	if (Hob != NULL) {\r
48557c65	82	PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;\r
c56b6566 JY	83	} else {\r
	84	AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r
	85	if (RegEax >= 0x80000008) {\r
	86	AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
	87	PhysicalAddressBits = (UINT8) RegEax;\r
	88	} else {\r
	89	PhysicalAddressBits = 36;\r
	90	}\r
f3b33289	91	}\r
f3b33289	92	\r
4140a663	93	//\r
	94	// IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.\r
	95	//\r
	96	ASSERT (PhysicalAddressBits <= 52);\r
	97	if (PhysicalAddressBits > 48) {\r
	98	PhysicalAddressBits = 48;\r
	99	}\r
	100	\r
f3b33289	101	//\r
	102	// Calculate the table entries needed.\r
	103	//\r
	104	if (PhysicalAddressBits <= 39 ) {\r
	105	NumberOfPml4EntriesNeeded = 1;\r
c56b6566	106	NumberOfPdpEntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 30));\r
f3b33289	107	} else {\r
c56b6566	108	NumberOfPml4EntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 39));\r
f3b33289	109	NumberOfPdpEntriesNeeded = 512;\r
	110	}\r
	111	\r
	112	//\r
	113	// Pre-allocate big pages to avoid later allocations. \r
	114	//\r
c56b6566 JY	115	if (!Page1GSupport) {\r
	116	TotalPagesNum = (NumberOfPdpEntriesNeeded + 1) * NumberOfPml4EntriesNeeded + 1;\r
	117	} else {\r
	118	TotalPagesNum = NumberOfPml4EntriesNeeded + 1;\r
	119	}\r
f3b33289	120	BigPageAddress = (UINTN) AllocatePages (TotalPagesNum);\r
	121	ASSERT (BigPageAddress != 0);\r
	122	\r
	123	//\r
	124	// By architecture only one PageMapLevel4 exists - so lets allocate storage for it.\r
	125	//\r
	126	PageMap = (VOID *) BigPageAddress;\r
c56b6566	127	BigPageAddress += SIZE_4KB;\r
f3b33289	128	\r
	129	PageMapLevel4Entry = PageMap;\r
	130	PageAddress = 0;\r
	131	for (IndexOfPml4Entries = 0; IndexOfPml4Entries < NumberOfPml4EntriesNeeded; IndexOfPml4Entries++, PageMapLevel4Entry++) {\r
	132	//\r
	133	// Each PML4 entry points to a page of Page Directory Pointer entires.\r
	134	// So lets allocate space for them and fill them in in the IndexOfPdpEntries loop.\r
	135	//\r
	136	PageDirectoryPointerEntry = (VOID *) BigPageAddress;\r
c56b6566	137	BigPageAddress += SIZE_4KB;\r
f3b33289	138	\r
	139	//\r
	140	// Make a PML4 Entry\r
	141	//\r
	142	PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry;\r
	143	PageMapLevel4Entry->Bits.ReadWrite = 1;\r
	144	PageMapLevel4Entry->Bits.Present = 1;\r
	145	\r
c56b6566 JY	146	if (Page1GSupport) {\r
	147	PageDirectory1GEntry = (VOID *) BigPageAddress;\r
	148	BigPageAddress += SIZE_4KB;\r
	149	\r
	150	for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress += SIZE_1GB) {\r
f3b33289	151	//\r
	152	// Fill in the Page Directory entries\r
	153	//\r
c56b6566 JY	154	PageDirectory1GEntry->Uint64 = (UINT64)PageAddress;\r
	155	PageDirectory1GEntry->Bits.ReadWrite = 1;\r
	156	PageDirectory1GEntry->Bits.Present = 1;\r
	157	PageDirectory1GEntry->Bits.MustBe1 = 1;\r
	158	}\r
	159	} else {\r
	160	for (IndexOfPdpEntries = 0; IndexOfPdpEntries < NumberOfPdpEntriesNeeded; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {\r
	161	//\r
	162	// Each Directory Pointer entries points to a page of Page Directory entires.\r
	163	// So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop.\r
	164	// \r
	165	PageDirectoryEntry = (VOID *) BigPageAddress;\r
	166	BigPageAddress += SIZE_4KB;\r
	167	\r
	168	//\r
	169	// Fill in a Page Directory Pointer Entries\r
	170	//\r
	171	PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry;\r
	172	PageDirectoryPointerEntry->Bits.ReadWrite = 1;\r
	173	PageDirectoryPointerEntry->Bits.Present = 1;\r
	174	\r
	175	for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += SIZE_2MB) {\r
	176	//\r
	177	// Fill in the Page Directory entries\r
	178	//\r
	179	PageDirectoryEntry->Uint64 = (UINT64)PageAddress;\r
	180	PageDirectoryEntry->Bits.ReadWrite = 1;\r
	181	PageDirectoryEntry->Bits.Present = 1;\r
	182	PageDirectoryEntry->Bits.MustBe1 = 1;\r
	183	}\r
	184	}\r
f3b33289	185	\r
c56b6566 JY	186	for (; IndexOfPdpEntries < 512; IndexOfPdpEntries++, PageDirectoryPointerEntry++) {\r
	187	ZeroMem (\r
	188	PageDirectoryPointerEntry,\r
	189	sizeof(PAGE_MAP_AND_DIRECTORY_POINTER)\r
	190	);\r
f3b33289	191	}\r
	192	}\r
	193	}\r
	194	\r
	195	//\r
	196	// For the PML4 entries we are not using fill in a null entry.\r
f3b33289	197	//\r
f3b33289	198	for (; IndexOfPml4Entries < 512; IndexOfPml4Entries++, PageMapLevel4Entry++) {\r
c56b6566 JY	199	ZeroMem (\r
	200	PageMapLevel4Entry,\r
	201	sizeof (PAGE_MAP_AND_DIRECTORY_POINTER)\r
	202	);\r
f3b33289	203	}\r
	204	\r
	205	return (UINTN)PageMap;\r
	206	}\r
	207	\r