ArmPkg: only attempt buildin MmCommunicationDxe for AArch64
[mirror_edk2.git] / MdeModulePkg / Core / DxeIplPeim / X64 / VirtualMemory.h
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f3b33289 1/** @file\r
d1102dba 2 x64 Long Mode Virtual Memory Management Definitions\r
f3b33289 3\r
4 References:\r
48557c65 5 1) IA-32 Intel(R) Architecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r
6 2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r
7 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
f3b33289 8 4) AMD64 Architecture Programmer's Manual Volume 2: System Programming\r
9\r
d1102dba 10Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
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11Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
12\r
9d510e61 13SPDX-License-Identifier: BSD-2-Clause-Patent\r
f3b33289 14\r
d1102dba 15**/\r
f3b33289 16#ifndef _VIRTUAL_MEMORY_H_\r
17#define _VIRTUAL_MEMORY_H_\r
18\r
19\r
20#define SYS_CODE64_SEL 0x38\r
21\r
5997daf7 22\r
f3b33289 23#pragma pack(1)\r
24\r
25typedef union {\r
26 struct {\r
27 UINT32 LimitLow : 16;\r
28 UINT32 BaseLow : 16;\r
29 UINT32 BaseMid : 8;\r
30 UINT32 Type : 4;\r
31 UINT32 System : 1;\r
32 UINT32 Dpl : 2;\r
33 UINT32 Present : 1;\r
34 UINT32 LimitHigh : 4;\r
35 UINT32 Software : 1;\r
36 UINT32 Reserved : 1;\r
37 UINT32 DefaultSize : 1;\r
38 UINT32 Granularity : 1;\r
39 UINT32 BaseHigh : 8;\r
40 } Bits;\r
41 UINT64 Uint64;\r
42} IA32_GDT;\r
43\r
44typedef struct {\r
45 IA32_IDT_GATE_DESCRIPTOR Ia32IdtEntry;\r
46 UINT32 Offset32To63;\r
47 UINT32 Reserved;\r
48} X64_IDT_GATE_DESCRIPTOR;\r
49\r
50//\r
51// Page-Map Level-4 Offset (PML4) and\r
52// Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r
53//\r
54\r
55typedef union {\r
56 struct {\r
57 UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
58 UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
59 UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
60 UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
61 UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
62 UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
63 UINT64 Reserved:1; // Reserved\r
64 UINT64 MustBeZero:2; // Must Be Zero\r
65 UINT64 Available:3; // Available for use by system software\r
66 UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
67 UINT64 AvabilableHigh:11; // Available for use by system software\r
68 UINT64 Nx:1; // No Execute bit\r
69 } Bits;\r
70 UINT64 Uint64;\r
71} PAGE_MAP_AND_DIRECTORY_POINTER;\r
72\r
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73//\r
74// Page Table Entry 4KB\r
75//\r
76typedef union {\r
77 struct {\r
78 UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
79 UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
80 UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
81 UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
82 UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
83 UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
84 UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
85 UINT64 PAT:1; //\r
86 UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
87 UINT64 Available:3; // Available for use by system software\r
88 UINT64 PageTableBaseAddress:40; // Page Table Base Address\r
89 UINT64 AvabilableHigh:11; // Available for use by system software\r
90 UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
91 } Bits;\r
92 UINT64 Uint64;\r
93} PAGE_TABLE_4K_ENTRY;\r
94\r
f3b33289 95//\r
96// Page Table Entry 2MB\r
97//\r
98typedef union {\r
99 struct {\r
100 UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
101 UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
102 UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
103 UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
104 UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
105 UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
106 UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
d1102dba 107 UINT64 MustBe1:1; // Must be 1\r
f3b33289 108 UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
109 UINT64 Available:3; // Available for use by system software\r
110 UINT64 PAT:1; //\r
111 UINT64 MustBeZero:8; // Must be zero;\r
112 UINT64 PageTableBaseAddress:31; // Page Table Base Address\r
113 UINT64 AvabilableHigh:11; // Available for use by system software\r
114 UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
115 } Bits;\r
116 UINT64 Uint64;\r
117} PAGE_TABLE_ENTRY;\r
118\r
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119//\r
120// Page Table Entry 1GB\r
121//\r
122typedef union {\r
123 struct {\r
124 UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r
125 UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r
126 UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r
127 UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r
128 UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r
129 UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r
130 UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r
d1102dba 131 UINT64 MustBe1:1; // Must be 1\r
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132 UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r
133 UINT64 Available:3; // Available for use by system software\r
134 UINT64 PAT:1; //\r
135 UINT64 MustBeZero:17; // Must be zero;\r
136 UINT64 PageTableBaseAddress:22; // Page Table Base Address\r
137 UINT64 AvabilableHigh:11; // Available for use by system software\r
138 UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r
139 } Bits;\r
140 UINT64 Uint64;\r
141} PAGE_TABLE_1G_ENTRY;\r
142\r
f3b33289 143#pragma pack()\r
144\r
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145#define CR0_WP BIT16\r
146\r
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147#define IA32_PG_P BIT0\r
148#define IA32_PG_RW BIT1\r
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149#define IA32_PG_PS BIT7\r
150\r
151#define PAGING_PAE_INDEX_MASK 0x1FF\r
5630cdfe 152\r
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153#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull\r
154#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull\r
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155#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r
156\r
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157#define PAGING_L1_ADDRESS_SHIFT 12\r
158#define PAGING_L2_ADDRESS_SHIFT 21\r
159#define PAGING_L3_ADDRESS_SHIFT 30\r
160#define PAGING_L4_ADDRESS_SHIFT 39\r
161\r
162#define PAGING_PML4E_NUMBER 4\r
163\r
164#define PAGE_TABLE_POOL_ALIGNMENT BASE_2MB\r
165#define PAGE_TABLE_POOL_UNIT_SIZE SIZE_2MB\r
166#define PAGE_TABLE_POOL_UNIT_PAGES EFI_SIZE_TO_PAGES (PAGE_TABLE_POOL_UNIT_SIZE)\r
167#define PAGE_TABLE_POOL_ALIGN_MASK \\r
168 (~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1))\r
169\r
170typedef struct {\r
171 VOID *NextPool;\r
172 UINTN Offset;\r
173 UINTN FreePages;\r
174} PAGE_TABLE_POOL;\r
175\r
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176/**\r
177 Check if Execute Disable Bit (IA32_EFER.NXE) should be enabled or not.\r
178\r
179 @retval TRUE IA32_EFER.NXE should be enabled.\r
180 @retval FALSE IA32_EFER.NXE should not be enabled.\r
181\r
182**/\r
183BOOLEAN\r
184IsEnableNonExecNeeded (\r
185 VOID\r
186 );\r
187\r
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188/**\r
189 Enable Execute Disable Bit.\r
190\r
191**/\r
192VOID\r
193EnableExecuteDisableBit (\r
194 VOID\r
195 );\r
196\r
197/**\r
198 Split 2M page to 4K.\r
199\r
200 @param[in] PhysicalAddress Start physical address the 2M page covered.\r
201 @param[in, out] PageEntry2M Pointer to 2M page entry.\r
202 @param[in] StackBase Stack base address.\r
203 @param[in] StackSize Stack size.\r
204\r
205**/\r
206VOID\r
207Split2MPageTo4K (\r
208 IN EFI_PHYSICAL_ADDRESS PhysicalAddress,\r
209 IN OUT UINT64 *PageEntry2M,\r
210 IN EFI_PHYSICAL_ADDRESS StackBase,\r
211 IN UINTN StackSize\r
212 );\r
f3b33289 213\r
f3b33289 214/**\r
215 Allocates and fills in the Page Directory and Page Table Entries to\r
216 establish a 1:1 Virtual to Physical mapping.\r
217\r
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218 @param[in] StackBase Stack base address.\r
219 @param[in] StackSize Stack size.\r
f3b33289 220\r
48557c65 221 @return The address of 4 level page map.\r
f3b33289 222\r
223**/\r
224UINTN\r
225CreateIdentityMappingPageTables (\r
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226 IN EFI_PHYSICAL_ADDRESS StackBase,\r
227 IN UINTN StackSize\r
f3b33289 228 );\r
229\r
230\r
f3b33289 231/**\r
d1102dba 232\r
f3b33289 233 Fix up the vector number in the vector code.\r
d1102dba 234\r
f3b33289 235 @param VectorBase Base address of the vector handler.\r
f3b33289 236 @param VectorNum Index of vector.\r
237\r
238**/\r
239VOID\r
240EFIAPI\r
241AsmVectorFixup (\r
242 VOID *VectorBase,\r
243 UINT8 VectorNum\r
244 );\r
245\r
246\r
f3b33289 247/**\r
d1102dba 248\r
f3b33289 249 Get the information of vector template.\r
d1102dba 250\r
f3b33289 251 @param TemplateBase Base address of the template code.\r
d1102dba 252\r
f3b33289 253 @return Size of the Template code.\r
254\r
255**/\r
256UINTN\r
257EFIAPI\r
258AsmGetVectorTemplatInfo (\r
259 OUT VOID **TemplateBase\r
260 );\r
261\r
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262/**\r
263 Clear legacy memory located at the first 4K-page.\r
264\r
265 This function traverses the whole HOB list to check if memory from 0 to 4095\r
266 exists and has not been allocated, and then clear it if so.\r
267\r
268 @param HobStart The start of HobList passed to DxeCore.\r
269\r
270**/\r
271VOID\r
272ClearFirst4KPage (\r
273 IN VOID *HobStart\r
274 );\r
275\r
276/**\r
277 Return configure status of NULL pointer detection feature.\r
278\r
279 @return TRUE NULL pointer detection feature is enabled\r
280 @return FALSE NULL pointer detection feature is disabled\r
281**/\r
282BOOLEAN\r
283IsNullDetectionEnabled (\r
284 VOID\r
285 );\r
f3b33289 286\r
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287/**\r
288 Prevent the memory pages used for page table from been overwritten.\r
289\r
290 @param[in] PageTableBase Base address of page table (CR3).\r
291 @param[in] Level4Paging Level 4 paging flag.\r
292\r
293**/\r
294VOID\r
295EnablePageTableProtection (\r
296 IN UINTN PageTableBase,\r
297 IN BOOLEAN Level4Paging\r
298 );\r
299\r
300/**\r
301 This API provides a way to allocate memory for page table.\r
302\r
303 This API can be called more than once to allocate memory for page tables.\r
304\r
305 Allocates the number of 4KB pages and returns a pointer to the allocated\r
306 buffer. The buffer returned is aligned on a 4KB boundary.\r
307\r
308 If Pages is 0, then NULL is returned.\r
309 If there is not enough memory remaining to satisfy the request, then NULL is\r
310 returned.\r
311\r
312 @param Pages The number of 4 KB pages to allocate.\r
313\r
314 @return A pointer to the allocated buffer or NULL if allocation fails.\r
315\r
316**/\r
317VOID *\r
318AllocatePageTableMemory (\r
319 IN UINTN Pages\r
320 );\r
321\r
d1102dba 322#endif\r