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f3b33289 | 1 | /** @file\r |
2 | x64 Long Mode Virtual Memory Management Definitions \r | |
3 | \r | |
4 | References:\r | |
48557c65 | 5 | 1) IA-32 Intel(R) Architecture Software Developer's Manual Volume 1:Basic Architecture, Intel\r |
6 | 2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel\r | |
7 | 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r | |
f3b33289 | 8 | 4) AMD64 Architecture Programmer's Manual Volume 2: System Programming\r |
9 | \r | |
5630cdfe | 10 | Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r |
5997daf7 LD |
11 | Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r |
12 | \r | |
cd5ebaa0 | 13 | This program and the accompanying materials\r |
f3b33289 | 14 | are licensed and made available under the terms and conditions of the BSD License\r |
15 | which accompanies this distribution. The full text of the license may be found at\r | |
16 | http://opensource.org/licenses/bsd-license.php\r | |
17 | \r | |
18 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
19 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
20 | \r | |
21 | **/ \r | |
22 | #ifndef _VIRTUAL_MEMORY_H_\r | |
23 | #define _VIRTUAL_MEMORY_H_\r | |
24 | \r | |
25 | \r | |
26 | #define SYS_CODE64_SEL 0x38\r | |
27 | \r | |
5997daf7 | 28 | \r |
f3b33289 | 29 | #pragma pack(1)\r |
30 | \r | |
31 | typedef union {\r | |
32 | struct {\r | |
33 | UINT32 LimitLow : 16;\r | |
34 | UINT32 BaseLow : 16;\r | |
35 | UINT32 BaseMid : 8;\r | |
36 | UINT32 Type : 4;\r | |
37 | UINT32 System : 1;\r | |
38 | UINT32 Dpl : 2;\r | |
39 | UINT32 Present : 1;\r | |
40 | UINT32 LimitHigh : 4;\r | |
41 | UINT32 Software : 1;\r | |
42 | UINT32 Reserved : 1;\r | |
43 | UINT32 DefaultSize : 1;\r | |
44 | UINT32 Granularity : 1;\r | |
45 | UINT32 BaseHigh : 8;\r | |
46 | } Bits;\r | |
47 | UINT64 Uint64;\r | |
48 | } IA32_GDT;\r | |
49 | \r | |
50 | typedef struct {\r | |
51 | IA32_IDT_GATE_DESCRIPTOR Ia32IdtEntry;\r | |
52 | UINT32 Offset32To63;\r | |
53 | UINT32 Reserved;\r | |
54 | } X64_IDT_GATE_DESCRIPTOR;\r | |
55 | \r | |
56 | //\r | |
57 | // Page-Map Level-4 Offset (PML4) and\r | |
58 | // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r | |
59 | //\r | |
60 | \r | |
61 | typedef union {\r | |
62 | struct {\r | |
63 | UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r | |
64 | UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r | |
65 | UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r | |
66 | UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r | |
67 | UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r | |
68 | UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r | |
69 | UINT64 Reserved:1; // Reserved\r | |
70 | UINT64 MustBeZero:2; // Must Be Zero\r | |
71 | UINT64 Available:3; // Available for use by system software\r | |
72 | UINT64 PageTableBaseAddress:40; // Page Table Base Address\r | |
73 | UINT64 AvabilableHigh:11; // Available for use by system software\r | |
74 | UINT64 Nx:1; // No Execute bit\r | |
75 | } Bits;\r | |
76 | UINT64 Uint64;\r | |
77 | } PAGE_MAP_AND_DIRECTORY_POINTER;\r | |
78 | \r | |
5630cdfe SZ |
79 | //\r |
80 | // Page Table Entry 4KB\r | |
81 | //\r | |
82 | typedef union {\r | |
83 | struct {\r | |
84 | UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r | |
85 | UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r | |
86 | UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r | |
87 | UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r | |
88 | UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r | |
89 | UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r | |
90 | UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r | |
91 | UINT64 PAT:1; //\r | |
92 | UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r | |
93 | UINT64 Available:3; // Available for use by system software\r | |
94 | UINT64 PageTableBaseAddress:40; // Page Table Base Address\r | |
95 | UINT64 AvabilableHigh:11; // Available for use by system software\r | |
96 | UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r | |
97 | } Bits;\r | |
98 | UINT64 Uint64;\r | |
99 | } PAGE_TABLE_4K_ENTRY;\r | |
100 | \r | |
f3b33289 | 101 | //\r |
102 | // Page Table Entry 2MB\r | |
103 | //\r | |
104 | typedef union {\r | |
105 | struct {\r | |
106 | UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r | |
107 | UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r | |
108 | UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r | |
109 | UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r | |
110 | UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r | |
111 | UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r | |
112 | UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r | |
113 | UINT64 MustBe1:1; // Must be 1 \r | |
114 | UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r | |
115 | UINT64 Available:3; // Available for use by system software\r | |
116 | UINT64 PAT:1; //\r | |
117 | UINT64 MustBeZero:8; // Must be zero;\r | |
118 | UINT64 PageTableBaseAddress:31; // Page Table Base Address\r | |
119 | UINT64 AvabilableHigh:11; // Available for use by system software\r | |
120 | UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r | |
121 | } Bits;\r | |
122 | UINT64 Uint64;\r | |
123 | } PAGE_TABLE_ENTRY;\r | |
124 | \r | |
c56b6566 JY |
125 | //\r |
126 | // Page Table Entry 1GB\r | |
127 | //\r | |
128 | typedef union {\r | |
129 | struct {\r | |
130 | UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r | |
131 | UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r | |
132 | UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r | |
133 | UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r | |
134 | UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r | |
135 | UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r | |
136 | UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r | |
137 | UINT64 MustBe1:1; // Must be 1 \r | |
138 | UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r | |
139 | UINT64 Available:3; // Available for use by system software\r | |
140 | UINT64 PAT:1; //\r | |
141 | UINT64 MustBeZero:17; // Must be zero;\r | |
142 | UINT64 PageTableBaseAddress:22; // Page Table Base Address\r | |
143 | UINT64 AvabilableHigh:11; // Available for use by system software\r | |
144 | UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r | |
145 | } Bits;\r | |
146 | UINT64 Uint64;\r | |
147 | } PAGE_TABLE_1G_ENTRY;\r | |
148 | \r | |
f3b33289 | 149 | #pragma pack()\r |
150 | \r | |
5630cdfe SZ |
151 | #define IA32_PG_P BIT0\r |
152 | #define IA32_PG_RW BIT1\r | |
153 | \r | |
5997daf7 LD |
154 | #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r |
155 | \r | |
5630cdfe SZ |
156 | /**\r |
157 | Enable Execute Disable Bit.\r | |
158 | \r | |
159 | **/\r | |
160 | VOID\r | |
161 | EnableExecuteDisableBit (\r | |
162 | VOID\r | |
163 | );\r | |
164 | \r | |
165 | /**\r | |
166 | Split 2M page to 4K.\r | |
167 | \r | |
168 | @param[in] PhysicalAddress Start physical address the 2M page covered.\r | |
169 | @param[in, out] PageEntry2M Pointer to 2M page entry.\r | |
170 | @param[in] StackBase Stack base address.\r | |
171 | @param[in] StackSize Stack size.\r | |
172 | \r | |
173 | **/\r | |
174 | VOID\r | |
175 | Split2MPageTo4K (\r | |
176 | IN EFI_PHYSICAL_ADDRESS PhysicalAddress,\r | |
177 | IN OUT UINT64 *PageEntry2M,\r | |
178 | IN EFI_PHYSICAL_ADDRESS StackBase,\r | |
179 | IN UINTN StackSize\r | |
180 | );\r | |
f3b33289 | 181 | \r |
f3b33289 | 182 | /**\r |
183 | Allocates and fills in the Page Directory and Page Table Entries to\r | |
184 | establish a 1:1 Virtual to Physical mapping.\r | |
185 | \r | |
5630cdfe SZ |
186 | @param[in] StackBase Stack base address.\r |
187 | @param[in] StackSize Stack size.\r | |
f3b33289 | 188 | \r |
48557c65 | 189 | @return The address of 4 level page map.\r |
f3b33289 | 190 | \r |
191 | **/\r | |
192 | UINTN\r | |
193 | CreateIdentityMappingPageTables (\r | |
5630cdfe SZ |
194 | IN EFI_PHYSICAL_ADDRESS StackBase,\r |
195 | IN UINTN StackSize\r | |
f3b33289 | 196 | );\r |
197 | \r | |
198 | \r | |
f3b33289 | 199 | /**\r |
200 | \r | |
201 | Fix up the vector number in the vector code.\r | |
202 | \r | |
203 | @param VectorBase Base address of the vector handler.\r | |
f3b33289 | 204 | @param VectorNum Index of vector.\r |
205 | \r | |
206 | **/\r | |
207 | VOID\r | |
208 | EFIAPI\r | |
209 | AsmVectorFixup (\r | |
210 | VOID *VectorBase,\r | |
211 | UINT8 VectorNum\r | |
212 | );\r | |
213 | \r | |
214 | \r | |
f3b33289 | 215 | /**\r |
216 | \r | |
217 | Get the information of vector template.\r | |
218 | \r | |
219 | @param TemplateBase Base address of the template code.\r | |
220 | \r | |
221 | @return Size of the Template code.\r | |
222 | \r | |
223 | **/\r | |
224 | UINTN\r | |
225 | EFIAPI\r | |
226 | AsmGetVectorTemplatInfo (\r | |
227 | OUT VOID **TemplateBase\r | |
228 | );\r | |
229 | \r | |
230 | \r | |
231 | #endif \r |