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1 | /** @file\r |
2 | PCI Host Bridge Library consumed by PciHostBridgeDxe driver returning\r | |
3 | the platform specific information about the PCI Host Bridge.\r | |
4 | \r | |
5 | Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r | |
9d510e61 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
9e9a30bd RN |
7 | \r |
8 | **/\r | |
1436aea4 | 9 | \r |
9e9a30bd RN |
10 | #ifndef __PCI_HOST_BRIDGE_LIB_H__\r |
11 | #define __PCI_HOST_BRIDGE_LIB_H__\r | |
12 | \r | |
13 | //\r | |
14 | // (Base > Limit) indicates an aperture is not available.\r | |
15 | //\r | |
16 | typedef struct {\r | |
5bb1866e HG |
17 | //\r |
18 | // Base and Limit are the device address instead of host address when\r | |
19 | // Translation is not zero\r | |
20 | //\r | |
1436aea4 MK |
21 | UINT64 Base;\r |
22 | UINT64 Limit;\r | |
5bb1866e HG |
23 | //\r |
24 | // According to UEFI 2.7, Device Address = Host Address + Translation,\r | |
25 | // so Translation = Device Address - Host Address.\r | |
26 | // On platforms where Translation is not zero, the subtraction is probably to\r | |
27 | // be performed with UINT64 wrap-around semantics, for we may translate an\r | |
28 | // above-4G host address into a below-4G device address for legacy PCIe device\r | |
29 | // compatibility.\r | |
30 | //\r | |
31 | // NOTE: The alignment of Translation is required to be larger than any BAR\r | |
32 | // alignment in the same root bridge, so that the same alignment can be\r | |
33 | // applied to both device address and host address, which simplifies the\r | |
34 | // situation and makes the current resource allocation code in generic PCI\r | |
35 | // host bridge driver still work.\r | |
36 | //\r | |
1436aea4 | 37 | UINT64 Translation;\r |
9e9a30bd RN |
38 | } PCI_ROOT_BRIDGE_APERTURE;\r |
39 | \r | |
40 | typedef struct {\r | |
1436aea4 MK |
41 | UINT32 Segment; ///< Segment number.\r |
42 | UINT64 Supports; ///< Supported attributes.\r | |
43 | ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()\r | |
44 | ///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
45 | UINT64 Attributes; ///< Initial attributes.\r | |
46 | ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()\r | |
47 | ///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
48 | BOOLEAN DmaAbove4G; ///< DMA above 4GB memory.\r | |
49 | ///< Set to TRUE when root bridge supports DMA above 4GB memory.\r | |
50 | BOOLEAN NoExtendedConfigSpace; ///< When FALSE, the root bridge supports\r | |
51 | ///< Extended (4096-byte) Configuration Space.\r | |
52 | ///< When TRUE, the root bridge supports\r | |
53 | ///< 256-byte Configuration Space only.\r | |
54 | BOOLEAN ResourceAssigned; ///< Resource assignment status of the root bridge.\r | |
55 | ///< Set to TRUE if Bus/IO/MMIO resources for root bridge have been assigned.\r | |
56 | UINT64 AllocationAttributes; ///< Allocation attributes.\r | |
57 | ///< Refer to EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM and\r | |
58 | ///< EFI_PCI_HOST_BRIDGE_MEM64_DECODE used by GetAllocAttributes()\r | |
59 | ///< in EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r | |
60 | PCI_ROOT_BRIDGE_APERTURE Bus; ///< Bus aperture which can be used by the root bridge.\r | |
61 | PCI_ROOT_BRIDGE_APERTURE Io; ///< IO aperture which can be used by the root bridge.\r | |
62 | PCI_ROOT_BRIDGE_APERTURE Mem; ///< MMIO aperture below 4GB which can be used by the root bridge.\r | |
63 | PCI_ROOT_BRIDGE_APERTURE MemAbove4G; ///< MMIO aperture above 4GB which can be used by the root bridge.\r | |
64 | PCI_ROOT_BRIDGE_APERTURE PMem; ///< Prefetchable MMIO aperture below 4GB which can be used by the root bridge.\r | |
65 | PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; ///< Prefetchable MMIO aperture above 4GB which can be used by the root bridge.\r | |
66 | EFI_DEVICE_PATH_PROTOCOL *DevicePath; ///< Device path.\r | |
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67 | } PCI_ROOT_BRIDGE;\r |
68 | \r | |
69 | /**\r | |
70 | Return all the root bridge instances in an array.\r | |
71 | \r | |
72 | @param Count Return the count of root bridge instances.\r | |
73 | \r | |
74 | @return All the root bridge instances in an array.\r | |
75 | The array should be passed into PciHostBridgeFreeRootBridges()\r | |
76 | when it's not used.\r | |
77 | **/\r | |
78 | PCI_ROOT_BRIDGE *\r | |
79 | EFIAPI\r | |
80 | PciHostBridgeGetRootBridges (\r | |
1436aea4 | 81 | UINTN *Count\r |
9e9a30bd RN |
82 | );\r |
83 | \r | |
84 | /**\r | |
85 | Free the root bridge instances array returned from PciHostBridgeGetRootBridges().\r | |
86 | \r | |
eea222ce RN |
87 | @param Bridges The root bridge instances array.\r |
88 | @param Count The count of the array.\r | |
9e9a30bd RN |
89 | **/\r |
90 | VOID\r | |
91 | EFIAPI\r | |
92 | PciHostBridgeFreeRootBridges (\r | |
1436aea4 MK |
93 | PCI_ROOT_BRIDGE *Bridges,\r |
94 | UINTN Count\r | |
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95 | );\r |
96 | \r | |
97 | /**\r | |
98 | Inform the platform that the resource conflict happens.\r | |
99 | \r | |
100 | @param HostBridgeHandle Handle of the Host Bridge.\r | |
101 | @param Configuration Pointer to PCI I/O and PCI memory resource descriptors.\r | |
102 | The Configuration contains the resources for all the\r | |
103 | root bridges. The resource for each root bridge is\r | |
104 | terminated with END descriptor and an additional END\r | |
105 | is appended indicating the end of the entire resources.\r | |
106 | The resource descriptor field values follow the description\r | |
107 | in EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.SubmitResources().\r | |
108 | **/\r | |
109 | VOID\r | |
110 | EFIAPI\r | |
111 | PciHostBridgeResourceConflict (\r | |
1436aea4 MK |
112 | EFI_HANDLE HostBridgeHandle,\r |
113 | VOID *Configuration\r | |
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114 | );\r |
115 | \r | |
116 | #endif\r |