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e7b7db36 1/** @file\r
2 EFI SMM Access PPI definition.\r
3\r
4 This PPI is used to control the visibility of the SMRAM on the platform.\r
5 It abstracts the location and characteristics of SMRAM. The expectation is\r
6 that the north bridge or memory controller would publish this PPI.\r
7\r
d1102dba 8 The principal functionality found in the memory controller includes the following:\r
e7b7db36 9 - Exposing the SMRAM to all non-SMM agents, or the "open" state\r
10 - Shrouding the SMRAM to all but the SMM agents, or the "closed" state\r
d1102dba
LG
11 - Preserving the system integrity, or "locking" the SMRAM, such that the settings cannot be\r
12 perturbed by either boot service or runtime agents\r
e7b7db36 13\r
d1102dba 14Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR>\r
e7b7db36 15\r
16This program and the accompanying materials\r
17are licensed and made available under the terms and conditions\r
18of the BSD License which accompanies this distribution. The\r
19full text of the license may be found at\r
20http://opensource.org/licenses/bsd-license.php\r
21\r
22THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
23WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
24\r
25**/\r
26\r
27#ifndef _SMM_ACCESS_PPI_H_\r
28#define _SMM_ACCESS_PPI_H_\r
29\r
30#define PEI_SMM_ACCESS_PPI_GUID \\r
31 { 0x268f33a9, 0xcccd, 0x48be, { 0x88, 0x17, 0x86, 0x5, 0x3a, 0xc3, 0x2e, 0xd6 }}\r
32\r
33typedef struct _PEI_SMM_ACCESS_PPI PEI_SMM_ACCESS_PPI;\r
34\r
35/**\r
36 Opens the SMRAM area to be accessible by a PEIM driver.\r
37\r
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38 This function "opens" SMRAM so that it is visible while not inside of SMM. The function should\r
39 return EFI_UNSUPPORTED if the hardware does not support hiding of SMRAM. The function\r
e7b7db36 40 should return EFI_DEVICE_ERROR if the SMRAM configuration is locked.\r
41\r
42 @param PeiServices General purpose services available to every PEIM.\r
43 @param This The pointer to the SMM Access Interface.\r
44 @param DescriptorIndex The region of SMRAM to Open.\r
d1102dba 45\r
e7b7db36 46 @retval EFI_SUCCESS The region was successfully opened.\r
47 @retval EFI_DEVICE_ERROR The region could not be opened because locked by chipset.\r
48 @retval EFI_INVALID_PARAMETER The descriptor index was out of bounds.\r
d1102dba 49\r
e7b7db36 50**/\r
51typedef\r
52EFI_STATUS\r
53(EFIAPI *PEI_SMM_OPEN)(\r
54 IN EFI_PEI_SERVICES **PeiServices,\r
55 IN PEI_SMM_ACCESS_PPI *This,\r
56 IN UINTN DescriptorIndex\r
57 );\r
58\r
59/**\r
60 Inhibits access to the SMRAM.\r
61\r
d1102dba 62 This function "closes" SMRAM so that it is not visible while outside of SMM. The function should\r
e7b7db36 63 return EFI_UNSUPPORTED if the hardware does not support hiding of SMRAM.\r
64\r
65 @param PeiServices General purpose services available to every PEIM.\r
66 @param This The pointer to the SMM Access Interface.\r
67 @param DescriptorIndex The region of SMRAM to Close.\r
d1102dba 68\r
e7b7db36 69 @retval EFI_SUCCESS The region was successfully closed.\r
d1102dba 70 @retval EFI_DEVICE_ERROR The region could not be closed because locked by chipset.\r
e7b7db36 71 @retval EFI_INVALID_PARAMETER The descriptor index was out of bounds.\r
72\r
73**/\r
74typedef\r
75EFI_STATUS\r
76(EFIAPI *PEI_SMM_CLOSE)(\r
77 IN EFI_PEI_SERVICES **PeiServices,\r
78 IN PEI_SMM_ACCESS_PPI *This,\r
79 IN UINTN DescriptorIndex\r
80 );\r
81\r
82/**\r
83 Inhibits access to the SMRAM.\r
84\r
d1102dba
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85 This function prohibits access to the SMRAM region. This function is usually implemented such\r
86 that it is a write-once operation.\r
e7b7db36 87\r
88 @param PeiServices General purpose services available to every PEIM.\r
89 @param This The pointer to the SMM Access Interface.\r
90 @param DescriptorIndex The region of SMRAM to Close.\r
d1102dba 91\r
e7b7db36 92 @retval EFI_SUCCESS The region was successfully locked.\r
93 @retval EFI_DEVICE_ERROR The region could not be locked because at least\r
94 one range is still open.\r
95 @retval EFI_INVALID_PARAMETER The descriptor index was out of bounds.\r
96\r
97**/\r
98typedef\r
99EFI_STATUS\r
100(EFIAPI *PEI_SMM_LOCK)(\r
101 IN EFI_PEI_SERVICES **PeiServices,\r
102 IN PEI_SMM_ACCESS_PPI *This,\r
103 IN UINTN DescriptorIndex\r
104 );\r
105\r
106/**\r
107 Queries the memory controller for the possible regions that will support SMRAM.\r
108\r
109 @param PeiServices General purpose services available to every PEIM.\r
110 @param This The pointer to the SmmAccessPpi Interface.\r
111 @param SmramMapSize The pointer to the variable containing size of the\r
112 buffer to contain the description information.\r
113 @param SmramMap The buffer containing the data describing the Smram\r
114 region descriptors.\r
d1102dba 115\r
e7b7db36 116 @retval EFI_BUFFER_TOO_SMALL The user did not provide a sufficient buffer.\r
117 @retval EFI_SUCCESS The user provided a sufficiently-sized buffer.\r
118\r
119**/\r
120typedef\r
121EFI_STATUS\r
122(EFIAPI *PEI_SMM_CAPABILITIES)(\r
123 IN EFI_PEI_SERVICES **PeiServices,\r
124 IN PEI_SMM_ACCESS_PPI *This,\r
125 IN OUT UINTN *SmramMapSize,\r
126 IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap\r
127 );\r
128\r
129///\r
130/// EFI SMM Access PPI is used to control the visibility of the SMRAM on the platform.\r
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131/// It abstracts the location and characteristics of SMRAM. The platform should report\r
132/// all MMRAM via PEI_SMM_ACCESS_PPI. The expectation is that the north bridge or\r
381700e7 133/// memory controller would publish this PPI.\r
d1102dba 134///\r
e7b7db36 135struct _PEI_SMM_ACCESS_PPI {\r
136 PEI_SMM_OPEN Open;\r
137 PEI_SMM_CLOSE Close;\r
138 PEI_SMM_LOCK Lock;\r
139 PEI_SMM_CAPABILITIES GetCapabilities;\r
140 BOOLEAN LockState;\r
141 BOOLEAN OpenState;\r
142};\r
143\r
144extern EFI_GUID gPeiSmmAccessPpiGuid;\r
145\r
146#endif\r