projects / mirror_edk2.git / blame
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|---|---|---|
| b597b6e2 ZL |
1 | /** @file\r |
| 2 | This file defines the structure for the PCI Root Bridges.\r | |
| 3 | \r | |
| 4 | Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>\r | |
| 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
| 6 | \r | |
| 7 | @par Revision Reference:\r | |
| 8 | - Universal Payload Specification 0.75 (https://universalpayload.github.io/documentation/)\r | |
| 9 | **/\r | |
| 10 | \r | |
| 11 | #ifndef UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_H_\r | |
| 12 | #define UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_H_\r | |
| 13 | \r | |
| 14 | #include <UniversalPayload/UniversalPayload.h>\r | |
| 15 | \r | |
| 16 | #pragma pack(1)\r | |
| 17 | \r | |
| 18 | //\r | |
| 19 | // (Base > Limit) indicates an aperture is not available.\r | |
| 20 | //\r | |
| 21 | typedef struct {\r | |
| 22 | //\r | |
| 23 | // Base and Limit are the device address instead of host address when\r | |
| 24 | // Translation is not zero\r | |
| 25 | //\r | |
| 26 | UINT64 Base;\r | |
| 27 | UINT64 Limit;\r | |
| 28 | //\r | |
| 29 | // According to UEFI 2.7, Device Address = Host Address + Translation,\r | |
| 30 | // so Translation = Device Address - Host Address.\r | |
| 31 | // On platforms where Translation is not zero, the subtraction is probably to\r | |
| 32 | // be performed with UINT64 wrap-around semantics, for we may translate an\r | |
| 33 | // above-4G host address into a below-4G device address for legacy PCIe device\r | |
| 34 | // compatibility.\r | |
| 35 | //\r | |
| 36 | // NOTE: The alignment of Translation is required to be larger than any BAR\r | |
| 37 | // alignment in the same root bridge, so that the same alignment can be\r | |
| 38 | // applied to both device address and host address, which simplifies the\r | |
| 39 | // situation and makes the current resource allocation code in generic PCI\r | |
| 40 | // host bridge driver still work.\r | |
| 41 | //\r | |
| 42 | UINT64 Translation;\r | |
| 43 | } UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE;\r | |
| 44 | \r | |
| 45 | ///\r | |
| 46 | /// Payload PCI Root Bridge Information HOB\r | |
| 47 | ///\r | |
| 48 | typedef struct {\r | |
| 49 | UINT32 Segment; ///< Segment number.\r | |
| 50 | UINT64 Supports; ///< Supported attributes.\r | |
| 51 | ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()\r | |
| 52 | ///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
| 53 | UINT64 Attributes; ///< Initial attributes.\r | |
| 54 | ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes()\r | |
| 55 | ///< and SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
| 56 | BOOLEAN DmaAbove4G; ///< DMA above 4GB memory.\r | |
| 57 | ///< Set to TRUE when root bridge supports DMA above 4GB memory.\r | |
| 58 | BOOLEAN NoExtendedConfigSpace; ///< When FALSE, the root bridge supports\r | |
| 59 | ///< Extended (4096-byte) Configuration Space.\r | |
| 60 | ///< When TRUE, the root bridge supports\r | |
| 61 | ///< 256-byte Configuration Space only.\r | |
| 62 | UINT64 AllocationAttributes; ///< Allocation attributes.\r | |
| 63 | ///< Refer to EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM and\r | |
| 64 | ///< EFI_PCI_HOST_BRIDGE_MEM64_DECODE used by GetAllocAttributes()\r | |
| 65 | ///< in EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r | |
| 66 | UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Bus; ///< Bus aperture which can be used by the root bridge.\r | |
| 67 | UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Io; ///< IO aperture which can be used by the root bridge.\r | |
| 68 | UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Mem; ///< MMIO aperture below 4GB which can be used by the root bridge.\r | |
| 69 | UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE MemAbove4G; ///< MMIO aperture above 4GB which can be used by the root bridge.\r | |
| 70 | UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE PMem; ///< Prefetchable MMIO aperture below 4GB which can be used by the root bridge.\r | |
| 71 | UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; ///< Prefetchable MMIO aperture above 4GB which can be used by the root bridge.\r | |
| 72 | UINT32 HID; ///< PnP hardware ID of the root bridge. This value must match the corresponding\r | |
| 73 | ///< _HID in the ACPI name space.\r | |
| 74 | UINT32 UID; ///< Unique ID that is required by ACPI if two devices have the same _HID.\r | |
| 75 | ///< This value must also match the corresponding _UID/_HID pair in the ACPI name space.\r | |
| 76 | } UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE;\r | |
| 77 | \r | |
| 78 | typedef struct {\r | |
| 79 | UNIVERSAL_PAYLOAD_GENERIC_HEADER Header;\r | |
| 80 | BOOLEAN ResourceAssigned;\r | |
| 81 | UINT8 Count;\r | |
| 82 | UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE RootBridge[0];\r | |
| 83 | } UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES;\r | |
| 84 | \r | |
| 85 | #pragma pack()\r | |
| 86 | \r | |
| 87 | #define UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_REVISION 1\r | |
| 88 | \r | |
| 89 | extern GUID gUniversalPayloadPciRootBridgeInfoGuid;\r | |
| 90 | \r | |
| 91 | #endif // UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_H_\r |