[mirror_edk2.git] / MdeModulePkg / Library / BaseSerialPortLib16550 / BaseSerialPortLib16550.c

/** @file\r
  16550 UART Serial Port library functions\r
\r
  (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>\r
  Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include <Base.h>\r
#include <IndustryStandard/Pci.h>\r
#include <Library/SerialPortLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/PciLib.h>\r
#include <Library/PlatformHookLib.h>\r
#include <Library/BaseLib.h>\r
\r
//\r
// PCI Defintions.\r
//\r
#define PCI_BRIDGE_32_BIT_IO_SPACE              0x01\r
\r
//\r
// 16550 UART register offsets and bitfields\r
//\r
#define R_UART_RXBUF          0\r
#define R_UART_TXBUF          0\r
#define R_UART_BAUD_LOW       0\r
#define R_UART_BAUD_HIGH      1\r
#define R_UART_FCR            2\r
#define   B_UART_FCR_FIFOE    BIT0\r
#define   B_UART_FCR_FIFO64   BIT5\r
#define R_UART_LCR            3\r
#define   B_UART_LCR_DLAB     BIT7\r
#define R_UART_MCR            4\r
#define   B_UART_MCR_RTS      BIT1\r
#define R_UART_LSR            5\r
#define   B_UART_LSR_RXRDY    BIT0\r
#define   B_UART_LSR_TXRDY    BIT5\r
#define   B_UART_LSR_TEMT     BIT6\r
#define R_UART_MSR            6\r
#define   B_UART_MSR_CTS      BIT4\r
#define   B_UART_MSR_DSR      BIT5\r
\r
//\r
// 4-byte structure for each PCI node in PcdSerialPciDeviceInfo\r
//\r
typedef struct {\r
  UINT8   Device;\r
  UINT8   Function;\r
  UINT16  PowerManagementStatusAndControlRegister;\r
} PCI_UART_DEVICE_INFO;\r
\r
/**\r
  Read an 8-bit 16550 register.  If PcdSerialUseMmio is TRUE, then the value is read from \r
  MMIO space.  If PcdSerialUseMmio is FALSE, then the value is read from I/O space.  The\r
  parameter Offset is added to the base address of the 16550 registers that is specified \r
  by PcdSerialRegisterBase. \r
  \r
  @param  Base    The base address register of UART device.\r
  @param  Offset  The offset of the 16550 register to read.\r
\r
  @return The value read from the 16550 register.\r
\r
**/\r
UINT8\r
SerialPortReadRegister (\r
  UINTN  Base,\r
  UINTN  Offset\r
  )\r
{\r
  if (PcdGetBool (PcdSerialUseMmio)) {\r
    return MmioRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride));\r
  } else {\r
    return IoRead8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride));\r
  }\r
}\r
\r
/**\r
  Write an 8-bit 16550 register.  If PcdSerialUseMmio is TRUE, then the value is written to\r
  MMIO space.  If PcdSerialUseMmio is FALSE, then the value is written to I/O space.  The\r
  parameter Offset is added to the base address of the 16550 registers that is specified \r
  by PcdSerialRegisterBase. \r
  \r
  @param  Base    The base address register of UART device.\r
  @param  Offset  The offset of the 16550 register to write.\r
  @param  Value   The value to write to the 16550 register specified by Offset.\r
\r
  @return The value written to the 16550 register.\r
\r
**/\r
UINT8\r
SerialPortWriteRegister (\r
  UINTN  Base,\r
  UINTN  Offset,\r
  UINT8  Value\r
  )\r
{\r
  if (PcdGetBool (PcdSerialUseMmio)) {\r
    return MmioWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride), Value);\r
  } else {\r
    return IoWrite8 (Base + Offset * PcdGet32 (PcdSerialRegisterStride), Value);\r
  }\r
}\r
\r
/**\r
  Update the value of an 16-bit PCI configuration register in a PCI device.  If the  \r
  PCI Configuration register specified by PciAddress is already programmed with a \r
  non-zero value, then return the current value.  Otherwise update the PCI configuration \r
  register specified by PciAddress with the value specified by Value and return the\r
  value programmed into the PCI configuration register.  All values must be masked \r
  using the bitmask specified by Mask.\r
\r
  @param  PciAddress  PCI Library address of the PCI Configuration register to update.\r
  @param  Value       The value to program into the PCI Configuration Register.\r
  @param  Mask        Bitmask of the bits to check and update in the PCI configuration register.\r
\r
**/\r
UINT16\r
SerialPortLibUpdatePciRegister16 (\r
  UINTN   PciAddress,\r
  UINT16  Value,\r
  UINT16  Mask\r
  )\r
{\r
  UINT16  CurrentValue;\r
  \r
  CurrentValue = PciRead16 (PciAddress) & Mask;\r
  if (CurrentValue != 0) {\r
    return CurrentValue;\r
  }\r
  return PciWrite16 (PciAddress, Value & Mask);\r
}\r
\r
/**\r
  Update the value of an 32-bit PCI configuration register in a PCI device.  If the  \r
  PCI Configuration register specified by PciAddress is already programmed with a \r
  non-zero value, then return the current value.  Otherwise update the PCI configuration \r
  register specified by PciAddress with the value specified by Value and return the\r
  value programmed into the PCI configuration register.  All values must be masked \r
  using the bitmask specified by Mask.\r
\r
  @param  PciAddress  PCI Library address of the PCI Configuration register to update.\r
  @param  Value       The value to program into the PCI Configuration Register.\r
  @param  Mask        Bitmask of the bits to check and update in the PCI configuration register.\r
\r
  @return  The Secondary bus number that is actually programed into the PCI to PCI Bridge device.\r
\r
**/\r
UINT32\r
SerialPortLibUpdatePciRegister32 (\r
  UINTN   PciAddress,\r
  UINT32  Value,\r
  UINT32  Mask\r
  )\r
{\r
  UINT32  CurrentValue;\r
  \r
  CurrentValue = PciRead32 (PciAddress) & Mask;\r
  if (CurrentValue != 0) {\r
    return CurrentValue;\r
  }\r
  return PciWrite32 (PciAddress, Value & Mask);\r
}\r
\r
/**\r
  Retrieve the I/O or MMIO base address register for the PCI UART device. \r
  \r
  This function assumes Root Bus Numer is Zero, and enables I/O and MMIO in PCI UART \r
  Device if they are not already enabled. \r
  \r
  @return  The base address register of the UART device.\r
\r
**/\r
UINTN\r
GetSerialRegisterBase (\r
  VOID\r
  )\r
{\r
  UINTN                 PciLibAddress;\r
  UINTN                 BusNumber;\r
  UINTN                 SubordinateBusNumber;\r
  UINT32                ParentIoBase;\r
  UINT32                ParentIoLimit;\r
  UINT16                ParentMemoryBase;\r
  UINT16                ParentMemoryLimit;\r
  UINT32                IoBase;\r
  UINT32                IoLimit;\r
  UINT16                MemoryBase;\r
  UINT16                MemoryLimit;\r
  UINTN                 SerialRegisterBase;\r
  UINTN                 BarIndex;\r
  UINT32                RegisterBaseMask;\r
  PCI_UART_DEVICE_INFO  *DeviceInfo;\r
\r
  //\r
  // Get PCI Device Info\r
  //\r
  DeviceInfo = (PCI_UART_DEVICE_INFO *) PcdGetPtr (PcdSerialPciDeviceInfo);\r
  \r
  //\r
  // If PCI Device Info is empty, then assume fixed address UART and return PcdSerialRegisterBase\r
  //  \r
  if (DeviceInfo->Device == 0xff) {\r
    return (UINTN)PcdGet64 (PcdSerialRegisterBase);\r
  }\r
\r
  //\r
  // Assume PCI Bus 0 I/O window is 0-64KB and MMIO windows is 0-4GB\r
  //\r
  ParentMemoryBase  = 0 >> 16;\r
  ParentMemoryLimit = 0xfff00000 >> 16;\r
  ParentIoBase      = 0 >> 12;\r
  ParentIoLimit     = 0xf000 >> 12;\r
  \r
  //\r
  // Enable I/O and MMIO in PCI Bridge\r
  // Assume Root Bus Numer is Zero. \r
  //\r
  for (BusNumber = 0; (DeviceInfo + 1)->Device != 0xff; DeviceInfo++) {\r
    //\r
    // Compute PCI Lib Address to PCI to PCI Bridge\r
    //\r
    PciLibAddress = PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, DeviceInfo->Function, 0);\r
    \r
    //\r
    // Retrieve and verify the bus numbers in the PCI to PCI Bridge\r
    //\r
    BusNumber            = PciRead8 (PciLibAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);\r
    SubordinateBusNumber = PciRead8 (PciLibAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET);\r
    if (BusNumber == 0 || BusNumber > SubordinateBusNumber) {\r
      return 0;\r
    }\r
\r
    //\r
    // Retrieve and verify the I/O or MMIO decode window in the PCI to PCI Bridge\r
    //\r
    if (PcdGetBool (PcdSerialUseMmio)) {\r
      MemoryLimit = PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryLimit)) & 0xfff0;\r
      MemoryBase  = PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.MemoryBase))  & 0xfff0;\r
\r
      //\r
      // If PCI Bridge MMIO window is disabled, then return 0\r
      //\r
      if (MemoryLimit < MemoryBase) {\r
        return 0;\r
      }\r
      \r
      //\r
      // If PCI Bridge MMIO window is not in the address range decoded by the parent PCI Bridge, then return 0\r
      //  \r
      if (MemoryBase < ParentMemoryBase || MemoryBase > ParentMemoryLimit || MemoryLimit > ParentMemoryLimit) {\r
        return 0;\r
      }\r
      ParentMemoryBase  = MemoryBase;\r
      ParentMemoryLimit = MemoryLimit;\r
    } else {\r
      IoLimit = PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoLimit));\r
      if ((IoLimit & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) {\r
        IoLimit = IoLimit >> 4;\r
      } else {\r
        IoLimit = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoLimitUpper16)) << 4) | (IoLimit >> 4);\r
      }\r
      IoBase = PciRead8 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBase));\r
      if ((IoBase & PCI_BRIDGE_32_BIT_IO_SPACE ) == 0) {\r
        IoBase = IoBase >> 4;\r
      } else {\r
        IoBase = (PciRead16 (PciLibAddress + OFFSET_OF (PCI_TYPE01, Bridge.IoBaseUpper16)) << 4) | (IoBase >> 4);\r
      }\r
      \r
      //\r
      // If PCI Bridge I/O window is disabled, then return 0\r
      //\r
      if (IoLimit < IoBase) {\r
        return 0;\r
      }\r
      \r
      //\r
      // If PCI Bridge I/O window is not in the address range decoded by the parent PCI Bridge, then return 0\r
      //  \r
      if (IoBase < ParentIoBase || IoBase > ParentIoLimit || IoLimit > ParentIoLimit) {\r
        return 0;\r
      }\r
      ParentIoBase  = IoBase;\r
      ParentIoLimit = IoLimit;\r
    }\r
  }\r
\r
  //\r
  // Compute PCI Lib Address to PCI UART\r
  //\r
  PciLibAddress = PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, DeviceInfo->Function, 0);\r
  \r
  //\r
  // Find the first IO or MMIO BAR\r
  //\r
  RegisterBaseMask = 0xFFFFFFF0;\r
  for (BarIndex = 0; BarIndex < PCI_MAX_BAR; BarIndex ++) {\r
    SerialRegisterBase = PciRead32 (PciLibAddress + PCI_BASE_ADDRESSREG_OFFSET + BarIndex * 4);\r
    if (PcdGetBool (PcdSerialUseMmio) && ((SerialRegisterBase & BIT0) == 0)) {\r
      //\r
      // MMIO BAR is found\r
      //\r
      RegisterBaseMask = 0xFFFFFFF0;\r
      break;\r
    }\r
\r
    if ((!PcdGetBool (PcdSerialUseMmio)) && ((SerialRegisterBase & BIT0) != 0)) {\r
      //\r
      // IO BAR is found\r
      //\r
      RegisterBaseMask = 0xFFFFFFF8;\r
      break;\r
    }\r
  }\r
\r
  //\r
  // MMIO or IO BAR is not found.\r
  //\r
  if (BarIndex == PCI_MAX_BAR) {\r
    return 0;\r
  }\r
\r
  //\r
  // Program UART BAR\r
  //  \r
  SerialRegisterBase = SerialPortLibUpdatePciRegister32 (\r
                         PciLibAddress + PCI_BASE_ADDRESSREG_OFFSET + BarIndex * 4,\r
                         (UINT32)PcdGet64 (PcdSerialRegisterBase), \r
                         RegisterBaseMask\r
                         );\r
\r
  //\r
  // Verify that the UART BAR is in the address range decoded by the parent PCI Bridge\r
  //  \r
  if (PcdGetBool (PcdSerialUseMmio)) {\r
    if (((SerialRegisterBase >> 16) & 0xfff0) < ParentMemoryBase || ((SerialRegisterBase >> 16) & 0xfff0) > ParentMemoryLimit) {\r
      return 0;\r
    }\r
  } else {\r
    if ((SerialRegisterBase >> 12) < ParentIoBase || (SerialRegisterBase >> 12) > ParentIoLimit) {\r
      return 0;\r
    }\r
  }\r
  \r
  //\r
  // Enable I/O and MMIO in PCI UART Device if they are not already enabled\r
  //\r
  PciOr16 (\r
    PciLibAddress + PCI_COMMAND_OFFSET,\r
    PcdGetBool (PcdSerialUseMmio) ? EFI_PCI_COMMAND_MEMORY_SPACE : EFI_PCI_COMMAND_IO_SPACE\r
    );\r
\r
  //\r
  // Force D0 state if a Power Management and Status Register is specified\r
  //\r
  if (DeviceInfo->PowerManagementStatusAndControlRegister != 0x00) {\r
    if ((PciRead16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister) & (BIT0 | BIT1)) != 0x00) {\r
      PciAnd16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister, (UINT16)~(BIT0 | BIT1));\r
      //\r
      // If PCI UART was not in D0, then make sure FIFOs are enabled, but do not reset FIFOs\r
      //\r
      SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64)));\r
    }\r
  }\r
  \r
  //\r
  // Get PCI Device Info\r
  //\r
  DeviceInfo = (PCI_UART_DEVICE_INFO *) PcdGetPtr (PcdSerialPciDeviceInfo);\r
\r
  //\r
  // Enable I/O or MMIO in PCI Bridge\r
  // Assume Root Bus Numer is Zero. \r
  //\r
  for (BusNumber = 0; (DeviceInfo + 1)->Device != 0xff; DeviceInfo++) {\r
    //\r
    // Compute PCI Lib Address to PCI to PCI Bridge\r
    //\r
    PciLibAddress = PCI_LIB_ADDRESS (BusNumber, DeviceInfo->Device, DeviceInfo->Function, 0);\r
    \r
    //\r
    // Enable the I/O or MMIO decode windows in the PCI to PCI Bridge\r
    //\r
    PciOr16 (\r
      PciLibAddress + PCI_COMMAND_OFFSET, \r
      PcdGetBool (PcdSerialUseMmio) ? EFI_PCI_COMMAND_MEMORY_SPACE : EFI_PCI_COMMAND_IO_SPACE\r
      );\r
      \r
    //\r
    // Force D0 state if a Power Management and Status Register is specified\r
    //\r
    if (DeviceInfo->PowerManagementStatusAndControlRegister != 0x00) {\r
      if ((PciRead16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister) & (BIT0 | BIT1)) != 0x00) {\r
        PciAnd16 (PciLibAddress + DeviceInfo->PowerManagementStatusAndControlRegister, (UINT16)~(BIT0 | BIT1));\r
      }\r
    }\r
      \r
    BusNumber = PciRead8 (PciLibAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET);\r
  }\r
  \r
  return SerialRegisterBase;\r
}\r
\r
/**\r
  Return whether the hardware flow control signal allows writing.\r
\r
  @param  SerialRegisterBase The base address register of UART device.\r
\r
  @retval TRUE  The serial port is writable.\r
  @retval FALSE The serial port is not writable.\r
**/\r
BOOLEAN\r
SerialPortWritable (\r
  UINTN  SerialRegisterBase\r
  )\r
{\r
  if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {\r
    if (PcdGetBool (PcdSerialDetectCable)) {\r
      //\r
      // Wait for both DSR and CTS to be set\r
      //   DSR is set if a cable is connected.\r
      //   CTS is set if it is ok to transmit data\r
      //\r
      //   DSR  CTS  Description                               Action\r
      //   ===  ===  ========================================  ========\r
      //    0    0   No cable connected.                       Wait\r
      //    0    1   No cable connected.                       Wait\r
      //    1    0   Cable connected, but not clear to send.   Wait\r
      //    1    1   Cable connected, and clear to send.       Transmit\r
      //\r
      return (BOOLEAN) ((SerialPortReadRegister (SerialRegisterBase, R_UART_MSR) & (B_UART_MSR_DSR | B_UART_MSR_CTS)) == (B_UART_MSR_DSR | B_UART_MSR_CTS));\r
    } else {\r
      //\r
      // Wait for both DSR and CTS to be set OR for DSR to be clear.  \r
      //   DSR is set if a cable is connected.\r
      //   CTS is set if it is ok to transmit data\r
      //\r
      //   DSR  CTS  Description                               Action\r
      //   ===  ===  ========================================  ========\r
      //    0    0   No cable connected.                       Transmit\r
      //    0    1   No cable connected.                       Transmit\r
      //    1    0   Cable connected, but not clear to send.   Wait\r
      //    1    1   Cable connected, and clar to send.        Transmit\r
      //\r
      return (BOOLEAN) ((SerialPortReadRegister (SerialRegisterBase, R_UART_MSR) & (B_UART_MSR_DSR | B_UART_MSR_CTS)) != (B_UART_MSR_DSR));\r
    }\r
  }\r
\r
  return TRUE;\r
}\r
\r
/**\r
  Initialize the serial device hardware.\r
  \r
  If no initialization is required, then return RETURN_SUCCESS.\r
  If the serial device was successfully initialized, then return RETURN_SUCCESS.\r
  If the serial device could not be initialized, then return RETURN_DEVICE_ERROR.\r
  \r
  @retval RETURN_SUCCESS        The serial device was initialized.\r
  @retval RETURN_DEVICE_ERROR   The serial device could not be initialized.\r
\r
**/\r
RETURN_STATUS\r
EFIAPI\r
SerialPortInitialize (\r
  VOID\r
  )\r
{\r
  RETURN_STATUS  Status;\r
  UINTN          SerialRegisterBase;\r
  UINT32         Divisor;\r
  UINT32         CurrentDivisor;  \r
  BOOLEAN        Initialized;\r
\r
  //\r
  // Perform platform specific initialization required to enable use of the 16550 device\r
  // at the location specified by PcdSerialUseMmio and PcdSerialRegisterBase.\r
  //\r
  Status = PlatformHookSerialPortInitialize ();\r
  if (RETURN_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  //\r
  // Calculate divisor for baud generator\r
  //    Ref_Clk_Rate / Baud_Rate / 16\r
  //\r
  Divisor = PcdGet32 (PcdSerialClockRate) / (PcdGet32 (PcdSerialBaudRate) * 16);\r
  if ((PcdGet32 (PcdSerialClockRate) % (PcdGet32 (PcdSerialBaudRate) * 16)) >= PcdGet32 (PcdSerialBaudRate) * 8) {\r
    Divisor++;\r
  }\r
\r
  //\r
  // Get the base address of the serial port in either I/O or MMIO space\r
  //\r
  SerialRegisterBase = GetSerialRegisterBase ();\r
  if (SerialRegisterBase ==0) {\r
    return RETURN_DEVICE_ERROR;\r
  }\r
\r
  //\r
  // See if the serial port is already initialized\r
  //\r
  Initialized = TRUE;\r
  if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) & 0x3F) != (PcdGet8 (PcdSerialLineControl) & 0x3F)) {\r
    Initialized = FALSE;\r
  }\r
  SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) | B_UART_LCR_DLAB));\r
  CurrentDivisor =  SerialPortReadRegister (SerialRegisterBase, R_UART_BAUD_HIGH) << 8;\r
  CurrentDivisor |= (UINT32) SerialPortReadRegister (SerialRegisterBase, R_UART_BAUD_LOW);\r
  SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_LCR) & ~B_UART_LCR_DLAB));\r
  if (CurrentDivisor != Divisor) {\r
    Initialized = FALSE;\r
  }\r
  if (Initialized) {\r
    return RETURN_SUCCESS;\r
  }\r
\r
  //\r
  // Wait for the serial port to be ready.\r
  // Verify that both the transmit FIFO and the shift register are empty.\r
  //\r
  while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY));\r
  \r
  //\r
  // Configure baud rate\r
  //\r
  SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, B_UART_LCR_DLAB);\r
  SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_HIGH, (UINT8) (Divisor >> 8));\r
  SerialPortWriteRegister (SerialRegisterBase, R_UART_BAUD_LOW, (UINT8) (Divisor & 0xff));\r
\r
  //\r
  // Clear DLAB and configure Data Bits, Parity, and Stop Bits.\r
  // Strip reserved bits from PcdSerialLineControl\r
  //\r
  SerialPortWriteRegister (SerialRegisterBase, R_UART_LCR, (UINT8)(PcdGet8 (PcdSerialLineControl) & 0x3F));\r
\r
  //\r
  // Enable and reset FIFOs\r
  // Strip reserved bits from PcdSerialFifoControl\r
  //\r
  SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, 0x00);\r
  SerialPortWriteRegister (SerialRegisterBase, R_UART_FCR, (UINT8)(PcdGet8 (PcdSerialFifoControl) & (B_UART_FCR_FIFOE | B_UART_FCR_FIFO64)));\r
\r
  //\r
  // Put Modem Control Register(MCR) into its reset state of 0x00.\r
  //  \r
  SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, 0x00);\r
\r
  return RETURN_SUCCESS;\r
}\r
\r
/**\r
  Write data from buffer to serial device. \r
\r
  Writes NumberOfBytes data bytes from Buffer to the serial device.  \r
  The number of bytes actually written to the serial device is returned.\r
  If the return value is less than NumberOfBytes, then the write operation failed.\r
\r
  If Buffer is NULL, then ASSERT(). \r
\r
  If NumberOfBytes is zero, then return 0.\r
\r
  @param  Buffer           Pointer to the data buffer to be written.\r
  @param  NumberOfBytes    Number of bytes to written to the serial device.\r
\r
  @retval 0                NumberOfBytes is 0.\r
  @retval >0               The number of bytes written to the serial device.  \r
                           If this value is less than NumberOfBytes, then the read operation failed.\r
\r
**/\r
UINTN\r
EFIAPI\r
SerialPortWrite (\r
  IN UINT8     *Buffer,\r
  IN UINTN     NumberOfBytes\r
  )\r
{\r
  UINTN  SerialRegisterBase;\r
  UINTN  Result;\r
  UINTN  Index;\r
  UINTN  FifoSize;\r
\r
  if (Buffer == NULL) {\r
    return 0;\r
  }\r
\r
  SerialRegisterBase = GetSerialRegisterBase ();\r
  if (SerialRegisterBase ==0) {\r
    return 0;\r
  }\r
  \r
  if (NumberOfBytes == 0) {\r
    //\r
    // Flush the hardware\r
    //\r
\r
    //\r
    // Wait for both the transmit FIFO and shift register empty.\r
    //\r
    while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & (B_UART_LSR_TEMT | B_UART_LSR_TXRDY)) != (B_UART_LSR_TEMT | B_UART_LSR_TXRDY));\r
\r
    //\r
    // Wait for the hardware flow control signal\r
    //\r
    while (!SerialPortWritable (SerialRegisterBase));\r
    return 0;\r
  }\r
\r
  //\r
  // Compute the maximum size of the Tx FIFO\r
  //\r
  FifoSize = 1;\r
  if ((PcdGet8 (PcdSerialFifoControl) & B_UART_FCR_FIFOE) != 0) {\r
    if ((PcdGet8 (PcdSerialFifoControl) & B_UART_FCR_FIFO64) == 0) {\r
      FifoSize = 16;\r
    } else {\r
      FifoSize = PcdGet32 (PcdSerialExtendedTxFifoSize);\r
    }\r
  }\r
\r
  Result = NumberOfBytes;\r
  while (NumberOfBytes != 0) {\r
    //\r
    // Wait for the serial port to be ready, to make sure both the transmit FIFO\r
    // and shift register empty.\r
    //\r
    while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_TEMT) == 0);\r
\r
    //\r
    // Fill then entire Tx FIFO\r
    //\r
    for (Index = 0; Index < FifoSize && NumberOfBytes != 0; Index++, NumberOfBytes--, Buffer++) {\r
      //\r
      // Wait for the hardware flow control signal\r
      //\r
      while (!SerialPortWritable (SerialRegisterBase));\r
\r
      //\r
      // Write byte to the transmit buffer.\r
      //\r
      SerialPortWriteRegister (SerialRegisterBase, R_UART_TXBUF, *Buffer);\r
    }\r
  }\r
  return Result;\r
}\r
\r
/**\r
  Reads data from a serial device into a buffer.\r
\r
  @param  Buffer           Pointer to the data buffer to store the data read from the serial device.\r
  @param  NumberOfBytes    Number of bytes to read from the serial device.\r
\r
  @retval 0                NumberOfBytes is 0.\r
  @retval >0               The number of bytes read from the serial device.  \r
                           If this value is less than NumberOfBytes, then the read operation failed.\r
\r
**/\r
UINTN\r
EFIAPI\r
SerialPortRead (\r
  OUT UINT8     *Buffer,\r
  IN  UINTN     NumberOfBytes\r
  )\r
{\r
  UINTN  SerialRegisterBase;\r
  UINTN  Result;\r
  UINT8  Mcr;\r
\r
  if (NULL == Buffer) {\r
    return 0;\r
  }\r
\r
  SerialRegisterBase = GetSerialRegisterBase ();\r
  if (SerialRegisterBase ==0) {\r
    return 0;\r
  }\r
\r
  Mcr = (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) & ~B_UART_MCR_RTS);\r
  \r
  for (Result = 0; NumberOfBytes-- != 0; Result++, Buffer++) {\r
    //\r
    // Wait for the serial port to have some data.\r
    //\r
    while ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_RXRDY) == 0) {\r
      if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {\r
        //\r
        // Set RTS to let the peer send some data\r
        //\r
        SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(Mcr | B_UART_MCR_RTS));\r
      }\r
    }\r
    if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {\r
      //\r
      // Clear RTS to prevent peer from sending data\r
      //\r
      SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, Mcr);\r
    }\r
    \r
    //\r
    // Read byte from the receive buffer.\r
    //\r
    *Buffer = SerialPortReadRegister (SerialRegisterBase, R_UART_RXBUF);\r
  }\r
  \r
  return Result;\r
}\r
\r
\r
/**\r
  Polls a serial device to see if there is any data waiting to be read.\r
\r
  Polls aserial device to see if there is any data waiting to be read.\r
  If there is data waiting to be read from the serial device, then TRUE is returned.\r
  If there is no data waiting to be read from the serial device, then FALSE is returned.\r
\r
  @retval TRUE             Data is waiting to be read from the serial device.\r
  @retval FALSE            There is no data waiting to be read from the serial device.\r
\r
**/\r
BOOLEAN\r
EFIAPI\r
SerialPortPoll (\r
  VOID\r
  )\r
{\r
  UINTN  SerialRegisterBase;\r
  \r
  SerialRegisterBase = GetSerialRegisterBase ();\r
  if (SerialRegisterBase ==0) {\r
    return FALSE;\r
  }\r
\r
  //\r
  // Read the serial port status\r
  //\r
  if ((SerialPortReadRegister (SerialRegisterBase, R_UART_LSR) & B_UART_LSR_RXRDY) != 0) {\r
    if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {\r
      //\r
      // Clear RTS to prevent peer from sending data\r
      //\r
      SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) & ~B_UART_MCR_RTS));\r
    }\r
    return TRUE;\r
  }    \r
  \r
  if (PcdGetBool (PcdSerialUseHardwareFlowControl)) {\r
    //\r
    // Set RTS to let the peer send some data\r
    //\r
    SerialPortWriteRegister (SerialRegisterBase, R_UART_MCR, (UINT8)(SerialPortReadRegister (SerialRegisterBase, R_UART_MCR) | B_UART_MCR_RTS));\r
  }\r
  \r
  return FALSE;\r
}\r