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da58b0db | 1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r | |
4 | \r | |
5 | This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions\r | |
7 | of the BSD License which accompanies this distribution. The\r | |
8 | full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #ifndef _CAPSULE_PEIM_H_\r | |
17 | #define _CAPSULE_PEIM_H_\r | |
18 | \r | |
19 | #include <PiPei.h>\r | |
20 | #include <Uefi/UefiSpec.h>\r | |
21 | \r | |
22 | #include <Ppi/Capsule.h>\r | |
ab7017fe | 23 | #include <Ppi/LoadFile.h>\r |
da58b0db | 24 | #include <Ppi/ReadOnlyVariable2.h>\r |
25 | #include <Guid/CapsuleVendor.h>\r | |
26 | \r | |
27 | #include <Library/DebugLib.h>\r | |
28 | #include <Library/PeimEntryPoint.h>\r | |
29 | #include <Library/PeiServicesLib.h>\r | |
30 | #include <Library/BaseMemoryLib.h>\r | |
31 | #include <Library/HobLib.h>\r | |
32 | #include <Library/PeiServicesTablePointerLib.h>\r | |
33 | #include <Library/PrintLib.h>\r | |
ab7017fe | 34 | #include <Library/PeCoffLib.h>\r |
35 | #include <Library/PeCoffGetEntryPointLib.h>\r | |
36 | #include <Library/PcdLib.h>\r | |
37 | #include <Library/ReportStatusCodeLib.h>\r | |
38 | #include <IndustryStandard/PeImage.h>\r | |
39 | #include "Common/CommonHeader.h"\r | |
40 | \r | |
4e4f13d2 | 41 | #ifdef MDE_CPU_IA32 \r |
42 | \r | |
ab7017fe | 43 | #pragma pack(1)\r |
da58b0db | 44 | \r |
45 | //\r | |
ab7017fe | 46 | // Page-Map Level-4 Offset (PML4) and\r |
47 | // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r | |
da58b0db | 48 | //\r |
ab7017fe | 49 | \r |
50 | typedef union {\r | |
51 | struct {\r | |
52 | UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r | |
53 | UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r | |
54 | UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r | |
55 | UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r | |
56 | UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r | |
57 | UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r | |
58 | UINT64 Reserved:1; // Reserved\r | |
59 | UINT64 MustBeZero:2; // Must Be Zero\r | |
60 | UINT64 Available:3; // Available for use by system software\r | |
61 | UINT64 PageTableBaseAddress:40; // Page Table Base Address\r | |
62 | UINT64 AvabilableHigh:11; // Available for use by system software\r | |
63 | UINT64 Nx:1; // No Execute bit\r | |
64 | } Bits;\r | |
65 | UINT64 Uint64;\r | |
66 | } PAGE_MAP_AND_DIRECTORY_POINTER;\r | |
da58b0db | 67 | \r |
68 | //\r | |
ab7017fe | 69 | // Page Table Entry 2MB\r |
da58b0db | 70 | //\r |
ab7017fe | 71 | typedef union {\r |
72 | struct {\r | |
73 | UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r | |
74 | UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r | |
75 | UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r | |
76 | UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r | |
77 | UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r | |
78 | UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r | |
79 | UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r | |
80 | UINT64 MustBe1:1; // Must be 1 \r | |
81 | UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r | |
82 | UINT64 Available:3; // Available for use by system software\r | |
83 | UINT64 PAT:1; //\r | |
84 | UINT64 MustBeZero:8; // Must be zero;\r | |
85 | UINT64 PageTableBaseAddress:31; // Page Table Base Address\r | |
86 | UINT64 AvabilableHigh:11; // Available for use by system software\r | |
87 | UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r | |
88 | } Bits;\r | |
89 | UINT64 Uint64;\r | |
90 | } PAGE_TABLE_ENTRY;\r | |
da58b0db | 91 | \r |
c56b6566 JY |
92 | //\r |
93 | // Page Table Entry 1GB\r | |
94 | //\r | |
95 | typedef union {\r | |
96 | struct {\r | |
97 | UINT64 Present:1; // 0 = Not present in memory, 1 = Present in memory\r | |
98 | UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r | |
99 | UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r | |
100 | UINT64 WriteThrough:1; // 0 = Write-Back caching, 1=Write-Through caching\r | |
101 | UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r | |
102 | UINT64 Accessed:1; // 0 = Not accessed, 1 = Accessed (set by CPU)\r | |
103 | UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by processor on access to page\r | |
104 | UINT64 MustBe1:1; // Must be 1 \r | |
105 | UINT64 Global:1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write\r | |
106 | UINT64 Available:3; // Available for use by system software\r | |
107 | UINT64 PAT:1; //\r | |
108 | UINT64 MustBeZero:17; // Must be zero;\r | |
109 | UINT64 PageTableBaseAddress:22; // Page Table Base Address\r | |
110 | UINT64 AvabilableHigh:11; // Available for use by system software\r | |
111 | UINT64 Nx:1; // 0 = Execute Code, 1 = No Code Execution\r | |
112 | } Bits;\r | |
113 | UINT64 Uint64;\r | |
114 | } PAGE_TABLE_1G_ENTRY;\r | |
115 | \r | |
ab7017fe | 116 | #pragma pack()\r |
da58b0db | 117 | \r |
ab7017fe | 118 | typedef\r |
119 | EFI_STATUS\r | |
120 | (*COALESCE_ENTRY) (\r | |
121 | IN EFI_PEI_SERVICES **PeiServices,\r | |
122 | IN EFI_CAPSULE_BLOCK_DESCRIPTOR *BlockList,\r | |
123 | IN OUT VOID **MemoryBase,\r | |
124 | IN OUT UINTN *MemorySize\r | |
125 | );\r | |
da58b0db | 126 | \r |
127 | #endif\r | |
4e4f13d2 | 128 | \r |
129 | #endif\r |