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8bdadcc8 1/** @file\r
2\r
3This file contains just some basic definitions that are needed by drivers\r
4that dealing with ATA/ATAPI interface.\r
5\r
6\r
7Copyright (c) 2007, Intel Corporation\r
8All rights reserved. This program and the accompanying materials\r
9are licensed and made available under the terms and conditions of the BSD License\r
10which accompanies this distribution. The full text of the license may be found at\r
11http://opensource.org/licenses/bsd-license.php\r
12\r
13THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
14WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
15\r
16**/\r
17\r
18#ifndef _ATAPI_H\r
19#define _ATAPI_H\r
20\r
373b5cf9 21#pragma pack(1)\r
8bdadcc8 22\r
23//\r
24// ATA_IDENTIFY_DATA is defined in ATA-5\r
25//\r
26typedef struct {\r
27 UINT16 config; /* General Configuration */\r
28 UINT16 cylinders; /* Number of Cylinders */\r
29 UINT16 reserved_2;\r
30 UINT16 heads; /* Number of logical heads */\r
31 UINT16 vendor_data1;\r
32 UINT16 vendoe_data2;\r
33 UINT16 sectors_per_track;\r
34 UINT16 vendor_specific_7_9[3];\r
35 CHAR8 SerialNo[20]; /* ASCII */\r
36 UINT16 vendor_specific_20_21[2];\r
37 UINT16 ecc_bytes_available;\r
38 CHAR8 FirmwareVer[8]; /* ASCII */\r
39 CHAR8 ModelName[40]; /* ASCII */\r
40 UINT16 multi_sector_cmd_max_sct_cnt;\r
41 UINT16 reserved_48;\r
42 UINT16 capabilities;\r
43 UINT16 reserved_50;\r
44 UINT16 pio_cycle_timing;\r
45 UINT16 reserved_52;\r
46 UINT16 field_validity;\r
47 UINT16 current_cylinders;\r
48 UINT16 current_heads;\r
49 UINT16 current_sectors;\r
50 UINT16 CurrentCapacityLsb;\r
51 UINT16 CurrentCapacityMsb;\r
52 UINT16 reserved_59;\r
53 UINT16 user_addressable_sectors_lo;\r
54 UINT16 user_addressable_sectors_hi;\r
55 UINT16 reserved_62;\r
56 UINT16 multi_word_dma_mode;\r
57 UINT16 advanced_pio_modes;\r
58 UINT16 min_multi_word_dma_cycle_time;\r
59 UINT16 rec_multi_word_dma_cycle_time;\r
60 UINT16 min_pio_cycle_time_without_flow_control;\r
61 UINT16 min_pio_cycle_time_with_flow_control;\r
62 UINT16 reserved_69_79[11];\r
63 UINT16 major_version_no;\r
64 UINT16 minor_version_no;\r
65 UINT16 command_set_supported_82; // word 82\r
66 UINT16 command_set_supported_83; // word 83\r
67 UINT16 command_set_feature_extn; // word 84\r
68 UINT16 command_set_feature_enb_85; // word 85\r
69 UINT16 command_set_feature_enb_86; // word 86\r
70 UINT16 command_set_feature_default; // word 87\r
71 UINT16 ultra_dma_mode; // word 88\r
72 UINT16 reserved_89_127[39];\r
73 UINT16 security_status;\r
74 UINT16 vendor_data_129_159[31];\r
75 UINT16 reserved_160_255[96];\r
76} ATA_IDENTIFY_DATA;\r
77\r
78//\r
79// ATAPI_IDENTIFY_DATA is defined in ATA-6\r
80//\r
81typedef struct {\r
82 UINT16 config; // General Configuration\r
83 UINT16 obsolete_1;\r
84 UINT16 specific_config;\r
85 UINT16 obsolete_3;\r
86 UINT16 retired_4_5[2];\r
87 UINT16 obsolete_6;\r
88 UINT16 cfa_reserved_7_8[2];\r
89 UINT16 retired_9;\r
90 CHAR8 SerialNo[20]; // ASCII\r
91 UINT16 retired_20_21[2];\r
92 UINT16 obsolete_22;\r
93 CHAR8 FirmwareVer[8]; // ASCII\r
94 CHAR8 ModelName[40]; // ASCII\r
95 UINT16 multi_sector_cmd_max_sct_cnt;\r
96 UINT16 reserved_48;\r
97 UINT16 capabilities_49;\r
98 UINT16 capabilities_50;\r
99 UINT16 obsolete_51_52[2];\r
100 UINT16 field_validity;\r
101 UINT16 obsolete_54_58[5];\r
102 UINT16 mutil_sector_setting;\r
103 UINT16 user_addressable_sectors_lo;\r
104 UINT16 user_addressable_sectors_hi;\r
105 UINT16 obsolete_62;\r
106 UINT16 multi_word_dma_mode;\r
107 UINT16 advanced_pio_modes;\r
108 UINT16 min_multi_word_dma_cycle_time;\r
109 UINT16 rec_multi_word_dma_cycle_time;\r
110 UINT16 min_pio_cycle_time_without_flow_control;\r
111 UINT16 min_pio_cycle_time_with_flow_control;\r
112 UINT16 reserved_69_74[6];\r
113 UINT16 queue_depth;\r
114 UINT16 reserved_76_79[4];\r
115 UINT16 major_version_no;\r
116 UINT16 minor_version_no;\r
117 UINT16 cmd_set_support_82;\r
118 UINT16 cmd_set_support_83;\r
119 UINT16 cmd_feature_support;\r
120 UINT16 cmd_feature_enable_85;\r
121 UINT16 cmd_feature_enable_86;\r
122 UINT16 cmd_feature_default;\r
123 UINT16 ultra_dma_select;\r
124 UINT16 time_required_for_sec_erase;\r
125 UINT16 time_required_for_enhanced_sec_erase;\r
126 UINT16 current_advanced_power_mgmt_value;\r
127 UINT16 master_pwd_revison_code;\r
128 UINT16 hardware_reset_result;\r
129 UINT16 current_auto_acoustic_mgmt_value;\r
130 UINT16 reserved_95_99[5];\r
131 UINT16 max_user_lba_for_48bit_addr[4];\r
132 UINT16 reserved_104_126[23];\r
133 UINT16 removable_media_status_notification_support;\r
134 UINT16 security_status;\r
135 UINT16 vendor_data_129_159[31];\r
136 UINT16 cfa_power_mode;\r
137 UINT16 cfa_reserved_161_175[15];\r
138 UINT16 current_media_serial_no[30];\r
139 UINT16 reserved_206_254[49];\r
140 UINT16 integrity_word;\r
141} ATAPI_IDENTIFY_DATA;\r
142\r
143\r
144typedef struct {\r
145 UINT8 peripheral_type;\r
146 UINT8 RMB;\r
147 UINT8 version;\r
148 UINT8 response_data_format;\r
149 UINT8 addnl_length;\r
150 UINT8 reserved_5;\r
151 UINT8 reserved_6;\r
152 UINT8 reserved_7;\r
153 UINT8 vendor_info[8];\r
154 UINT8 product_id[12];\r
155 UINT8 eeprom_product_code[4];\r
156 UINT8 firmware_rev_level[4];\r
157 UINT8 firmware_sub_rev_level[1];\r
158 UINT8 reserved_37;\r
159 UINT8 reserved_38;\r
160 UINT8 reserved_39;\r
161 UINT8 max_capacity_hi;\r
162 UINT8 max_capacity_mid;\r
163 UINT8 max_capacity_lo;\r
164 UINT8 reserved_43_95[95 - 43 + 1];\r
165 //\r
166 // Some more fields\r
167 //\r
168 UINT8 vendor_id[20];\r
169 UINT8 eeprom_drive_sno[12];\r
170} ATAPI_INQUIRY_DATA;\r
171\r
172typedef struct {\r
173 UINT8 peripheral_type;\r
174 UINT8 RMB;\r
175 UINT8 version;\r
176 UINT8 response_data_format;\r
177 UINT8 addnl_length;\r
178 UINT8 reserved_5;\r
179 UINT8 reserved_6;\r
180 UINT8 reserved_7;\r
181 UINT8 vendor_info[8];\r
182 UINT8 product_id[16];\r
183 UINT8 product_revision_level[4];\r
184 UINT8 vendor_specific[20];\r
185 UINT8 reserved_56_95[40];\r
186} ATAPI_CDROM_INQUIRY_DATA;\r
187\r
188\r
189typedef struct {\r
190 UINT8 error_code : 7;\r
191 UINT8 valid : 1;\r
192 UINT8 reserved_1;\r
193 UINT8 sense_key : 4;\r
194 UINT8 reserved_21 : 1;\r
195 UINT8 ILI : 1;\r
196 UINT8 reserved_22 : 2;\r
197 UINT8 vendor_specific_3;\r
198 UINT8 vendor_specific_4;\r
199 UINT8 vendor_specific_5;\r
200 UINT8 vendor_specific_6;\r
201 UINT8 addnl_sense_length; // n - 7\r
202 UINT8 vendor_specific_8;\r
203 UINT8 vendor_specific_9;\r
204 UINT8 vendor_specific_10;\r
205 UINT8 vendor_specific_11;\r
206 UINT8 addnl_sense_code; // mandatory\r
207 UINT8 addnl_sense_code_qualifier; // mandatory\r
208 UINT8 field_replaceable_unit_code; // optional\r
209 UINT8 reserved_15;\r
210 UINT8 reserved_16;\r
211 UINT8 reserved_17;\r
212 //\r
213 // Followed by additional sense bytes.\r
214 //\r
215} ATAPI_REQUEST_SENSE_DATA;\r
216\r
217typedef struct {\r
218 UINT8 LastLba3;\r
219 UINT8 LastLba2;\r
220 UINT8 LastLba1;\r
221 UINT8 LastLba0;\r
222 UINT8 BlockSize3;\r
223 UINT8 BlockSize2;\r
224 UINT8 BlockSize1;\r
225 UINT8 BlockSize0;\r
226} ATAPI_READ_CAPACITY_DATA;\r
227\r
228typedef struct {\r
229 UINT8 reserved_0;\r
230 UINT8 reserved_1;\r
231 UINT8 reserved_2;\r
232 UINT8 Capacity_Length;\r
233 UINT8 LastLba3;\r
234 UINT8 LastLba2;\r
235 UINT8 LastLba1;\r
236 UINT8 LastLba0;\r
237 UINT8 DesCode : 2;\r
238 UINT8 reserved_9 : 6;\r
239 UINT8 BlockSize2;\r
240 UINT8 BlockSize1;\r
241 UINT8 BlockSize0;\r
242} ATAPI_READ_FORMAT_CAPACITY_DATA;\r
243\r
244//\r
245// ATAPI Packet Command\r
246//\r
247\r
248typedef struct {\r
249 UINT8 opcode;\r
250 UINT8 reserved_1;\r
251 UINT8 reserved_2;\r
252 UINT8 reserved_3;\r
253 UINT8 reserved_4;\r
254 UINT8 reserved_5;\r
255 UINT8 reserved_6;\r
256 UINT8 reserved_7;\r
257 UINT8 reserved_8;\r
258 UINT8 reserved_9;\r
259 UINT8 reserved_10;\r
260 UINT8 reserved_11;\r
261} ATAPI_TEST_UNIT_READY_CMD;\r
262\r
263typedef struct {\r
264 UINT8 opcode;\r
265 UINT8 reserved_1 : 4;\r
266 UINT8 lun : 4;\r
267 UINT8 page_code;\r
268 UINT8 reserved_3;\r
269 UINT8 allocation_length;\r
270 UINT8 reserved_5;\r
271 UINT8 reserved_6;\r
272 UINT8 reserved_7;\r
273 UINT8 reserved_8;\r
274 UINT8 reserved_9;\r
275 UINT8 reserved_10;\r
276 UINT8 reserved_11;\r
277} ATAPI_INQUIRY_CMD;\r
278\r
279typedef struct {\r
280 UINT8 opcode;\r
281 UINT8 reserved_1 : 4;\r
282 UINT8 lun : 4;\r
283 UINT8 reserved_2;\r
284 UINT8 reserved_3;\r
285 UINT8 allocation_length;\r
286 UINT8 reserved_5;\r
287 UINT8 reserved_6;\r
288 UINT8 reserved_7;\r
289 UINT8 reserved_8;\r
290 UINT8 reserved_9;\r
291 UINT8 reserved_10;\r
292 UINT8 reserved_11;\r
293} ATAPI_REQUEST_SENSE_CMD;\r
294\r
295typedef struct {\r
296 UINT8 opcode;\r
297 UINT8 reserved_1 : 5;\r
298 UINT8 lun : 3;\r
299 UINT8 Lba0;\r
300 UINT8 Lba1;\r
301 UINT8 Lba2;\r
302 UINT8 Lba3;\r
303 UINT8 reserved_6;\r
304 UINT8 TranLen0;\r
305 UINT8 TranLen1;\r
306 UINT8 reserved_9;\r
307 UINT8 reserved_10;\r
308 UINT8 reserved_11;\r
309} ATAPI_READ10_CMD;\r
310\r
311typedef struct {\r
312 UINT8 opcode;\r
313 UINT8 reserved_1;\r
314 UINT8 reserved_2;\r
315 UINT8 reserved_3;\r
316 UINT8 reserved_4;\r
317 UINT8 reserved_5;\r
318 UINT8 reserved_6;\r
319 UINT8 allocation_length_hi;\r
320 UINT8 allocation_length_lo;\r
321 UINT8 reserved_9;\r
322 UINT8 reserved_10;\r
323 UINT8 reserved_11;\r
324} ATAPI_READ_FORMAT_CAP_CMD;\r
325\r
326typedef struct {\r
327 UINT8 peripheral_type;\r
328 UINT8 RMB;\r
329 UINT8 version;\r
330 UINT8 response_data_format;\r
331 UINT8 addnl_length;\r
332 UINT8 reserved_5;\r
333 UINT8 reserved_6;\r
334 UINT8 reserved_7;\r
335 UINT8 vendor_info[8];\r
336 UINT8 product_id[12];\r
337 UINT8 eeprom_product_code[4];\r
338 UINT8 firmware_rev_level[4];\r
339} ATAPI_USB_INQUIRY_DATA;\r
340\r
341typedef struct {\r
342 UINT8 opcode;\r
343 UINT8 reserved_1 : 4;\r
344 UINT8 lun : 4;\r
345 UINT8 page_code : 4;\r
346 UINT8 page_control : 4;\r
347 UINT8 reserved_3;\r
348 UINT8 reserved_4;\r
349 UINT8 reserved_5;\r
350 UINT8 reserved_6;\r
351 UINT8 parameter_list_length_hi;\r
352 UINT8 parameter_list_length_lo;\r
353 UINT8 reserved_9;\r
354 UINT8 reserved_10;\r
355 UINT8 reserved_11;\r
356} ATAPI_MODE_SENSE_CMD;\r
357\r
358//\r
359// ATAPI_PACKET_COMMAND is not defined in ATA specification.\r
360// We add it here for the convenience for ATA/ATAPI module writer. \r
361//\r
362typedef union {\r
363 UINT16 Data16[6];\r
364 ATAPI_TEST_UNIT_READY_CMD TestUnitReady;\r
365 ATAPI_READ10_CMD Read10;\r
366 ATAPI_REQUEST_SENSE_CMD RequestSence;\r
367 ATAPI_INQUIRY_CMD Inquiry;\r
368 ATAPI_MODE_SENSE_CMD ModeSense;\r
369 ATAPI_READ_FORMAT_CAP_CMD ReadFormatCapacity;\r
370} ATAPI_PACKET_COMMAND;\r
371\r
373b5cf9 372#pragma pack()\r
8bdadcc8 373\r
374\r
375#define ATAPI_MAX_DMA_EXT_CMD_SECTORS 0x10000\r
376#define ATAPI_MAX_DMA_CMD_SECTORS 0x100\r
377\r
378//\r
379// ATA Packet Command Code\r
380//\r
381#define ATA_CMD_SOFT_RESET 0x08\r
382#define ATA_CMD_PACKET 0xA0\r
383#define ATA_CMD_IDENTIFY_DEVICE 0xA1\r
384#define ATA_CMD_SERVICE 0xA2\r
385#define ATA_CMD_TEST_UNIT_READY 0x00\r
386#define ATA_CMD_REQUEST_SENSE 0x03\r
387#define ATA_CMD_INQUIRY 0x12\r
388#define ATA_CMD_READ_FORMAT_CAPACITY 0x23\r
389#define ATA_CMD_READ_CAPACITY 0x25\r
390#define ATA_CMD_READ_10 0x28\r
391#define ATA_CMD_WRITE_10 0x2A\r
392\r
393//\r
394// ATA Commands Code\r
395//\r
396\r
397//\r
398// Class 1: PIO Data-In Commands\r
399//\r
400#define ATA_CMD_IDENTIFY_DRIVE 0xec\r
401#define ATA_CMD_READ_BUFFER 0xe4\r
402#define ATA_CMD_READ_SECTORS 0x20\r
403#define ATA_CMD_READ_SECTORS_WITH_RETRY 0x21\r
404#define ATA_CMD_READ_LONG 0x22\r
405#define ATA_CMD_READ_LONG_WITH_RETRY 0x23\r
406//\r
407// Atapi6 enhanced commands\r
408//\r
409#define ATA_CMD_READ_SECTORS_EXT 0x24\r
410\r
411\r
412//\r
413// Class 2: PIO Data-Out Commands\r
414//\r
415#define ATA_CMD_FORMAT_TRACK 0x50\r
416#define ATA_CMD_WRITE_BUFFER 0xe8\r
417#define ATA_CMD_WRITE_SECTORS 0x30\r
418#define ATA_CMD_WRITE_SECTORS_WITH_RETRY 0x31\r
419#define ATA_CMD_WRITE_LONG 0x32\r
420#define ATA_CMD_WRITE_LONG_WITH_RETRY 0x33\r
421#define ATA_CMD_WRITE_VERIFY 0x3c\r
422//\r
423// Class 2 - Atapi6 enhanced commands\r
424//\r
425#define ATA_CMD_WRITE_SECTORS_EXT 0x34\r
426\r
427//\r
428// Class 3 No Data Command\r
429//\r
430#define ATA_CMD_ACK_MEDIA_CHANGE 0xdb\r
431#define ATA_CMD_BOOT_POST_BOOT 0xdc\r
432#define ATA_CMD_BOOT_PRE_BOOT 0xdd\r
433#define ATA_CMD_CHECK_POWER_MODE 0x98\r
434#define ATA_CMD_CHECK_POWER_MODE_ALIAS 0xe5\r
435#define ATA_CMD_DOOR_LOCK 0xde\r
436#define ATA_CMD_DOOR_UNLOCK 0xdf\r
437#define ATA_CMD_EXEC_DRIVE_DIAG 0x90\r
438#define ATA_CMD_IDLE_ALIAS 0x97\r
439#define ATA_CMD_IDLE 0xe3\r
440#define ATA_CMD_IDLE_IMMEDIATE 0x95\r
441#define ATA_CMD_IDLE_IMMEDIATE_ALIAS 0xe1\r
442#define ATA_CMD_INIT_DRIVE_PARAM 0x91\r
443#define ATA_CMD_RECALIBRATE 0x10 /* aliased to 1x */\r
444#define ATA_CMD_READ_DRIVE_STATE 0xe9\r
445#define ATA_CMD_SET_MULTIPLE_MODE 0xC6\r
446#define ATA_CMD_READ_VERIFY 0x40\r
447#define ATA_CMD_READ_VERIFY_WITH_RETRY 0x41\r
448#define ATA_CMD_SEEK 0x70 /* aliased to 7x */\r
449#define ATA_CMD_SET_FEATURES 0xef\r
450#define ATA_CMD_STANDBY 0x96\r
451#define ATA_CMD_STANDBY_ALIAS 0xe2\r
452#define ATA_CMD_STANDBY_IMMEDIATE 0x94\r
453#define ATA_CMD_STANDBY_IMMEDIATE_ALIAS 0xe0\r
454//\r
455// S.M.A.R.T\r
456//\r
457#define ATA_CMD_SMART 0xb0\r
458#define ATA_CONSTANT_C2 0xc2\r
459#define ATA_CONSTANT_4F 0x4f\r
460#define ATA_SMART_ENABLE_OPERATION 0xd8\r
461#define ATA_SMART_RETURN_STATUS 0xda\r
462\r
463\r
464//\r
465// Class 4: DMA Command\r
466//\r
467#define ATA_CMD_READ_DMA 0xc8\r
468#define ATA_CMD_READ_DMA_WITH_RETRY 0xc9\r
469#define ATA_CMD_READ_DMA_EXT 0x25\r
470#define ATA_CMD_WRITE_DMA 0xca\r
471#define ATA_CMD_WRITE_DMA_WITH_RETRY 0xcb\r
472#define ATA_CMD_WRITE_DMA_EXT 0x35\r
473\r
474\r
475\r
476//\r
477// default content of device control register, disable INT\r
478//\r
479#define ATA_DEFAULT_CTL (0x0a) // default content of device control register, disable INT\r
480#define ATA_DEFAULT_CMD (0xa0)\r
481\r
482#define ATAPI_MAX_BYTE_COUNT (0xfffe)\r
483\r
484//\r
485// Sense Key\r
486//\r
487#define ATA_REQUEST_SENSE_ERROR (0x70)\r
488#define ATA_SK_NO_SENSE (0x0)\r
489#define ATA_SK_RECOVERY_ERROR (0x1)\r
490#define ATA_SK_NOT_READY (0x2)\r
491#define ATA_SK_MEDIUM_ERROR (0x3)\r
492#define ATA_SK_HARDWARE_ERROR (0x4)\r
493#define ATA_SK_ILLEGAL_REQUEST (0x5)\r
494#define ATA_SK_UNIT_ATTENTION (0x6)\r
495#define ATA_SK_DATA_PROTECT (0x7)\r
496#define ATA_SK_BLANK_CHECK (0x8)\r
497#define ATA_SK_VENDOR_SPECIFIC (0x9)\r
498#define ATA_SK_RESERVED_A (0xA)\r
499#define ATA_SK_ABORT (0xB)\r
500#define ATA_SK_RESERVED_C (0xC)\r
501#define ATA_SK_OVERFLOW (0xD)\r
502#define ATA_SK_MISCOMPARE (0xE)\r
503#define ATA_SK_RESERVED_F (0xF)\r
504\r
505//\r
506// Additional Sense Codes\r
507//\r
508#define ATA_ASC_NOT_READY (0x04)\r
509#define ATA_ASC_MEDIA_ERR1 (0x10)\r
510#define ATA_ASC_MEDIA_ERR2 (0x11)\r
511#define ATA_ASC_MEDIA_ERR3 (0x14)\r
512#define ATA_ASC_MEDIA_ERR4 (0x30)\r
513#define ATA_ASC_MEDIA_UPSIDE_DOWN (0x06)\r
514#define ATA_ASC_INVALID_CMD (0x20)\r
515#define ATA_ASC_LBA_OUT_OF_RANGE (0x21)\r
516#define ATA_ASC_INVALID_FIELD (0x24)\r
517#define ATA_ASC_WRITE_PROTECTED (0x27)\r
518#define ATA_ASC_MEDIA_CHANGE (0x28)\r
519#define ATA_ASC_RESET (0x29) /* Power On Reset or Bus Reset occurred */\r
520#define ATA_ASC_ILLEGAL_FIELD (0x26)\r
521#define ATA_ASC_NO_MEDIA (0x3A)\r
522#define ATA_ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)\r
523\r
524//\r
525// Additional Sense Code Qualifier\r
526//\r
527#define ATA_ASCQ_IN_PROGRESS (0x01)\r
528\r
529//\r
530// Err Reg\r
531//\r
532#define ATA_ERRREG_BBK BIT7 /* Bad block detected */\r
533#define ATA_ERRREG_UNC BIT6 /* Uncorrectable Data */\r
534#define ATA_ERRREG_MC BIT5 /* Media Change */\r
535#define ATA_ERRREG_IDNF BIT4 /* ID Not Found */\r
536#define ATA_ERRREG_MCR BIT3 /* Media Change Requested */\r
537#define ATA_ERRREG_ABRT BIT2 /* Aborted Command */\r
538#define ATA_ERRREG_TK0NF BIT1 /* Track 0 Not Found */\r
539#define ATA_ERRREG_AMNF BIT0 /* Address Mark Not Found */\r
540\r
541//\r
542// Status Reg\r
543//\r
544#define ATA_STSREG_BSY BIT7 /* Controller Busy */\r
545#define ATA_STSREG_DRDY BIT6 /* Drive Ready */\r
546#define ATA_STSREG_DWF BIT5 /* Drive Write Fault */\r
547#define ATA_STSREG_DSC BIT4 /* Disk Seek Complete */\r
548#define ATA_STSREG_DRQ BIT3 /* Data Request */\r
549#define ATA_STSREG_CORR BIT2 /* Corrected Data */\r
550#define ATA_STSREG_IDX BIT1 /* Index */\r
551#define ATA_STSREG_ERR BIT0 /* Error */\r
552\r
553//\r
554// Device Control Reg\r
555//\r
556#define ATA_CTLREG_SRST BIT2 /* Software Reset */\r
557#define ATA_CTLREG_IEN_L BIT1 /* Interrupt Enable #*/\r
558\r
559#endif\r
560\r
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