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c25f146d
JA		 1/** @file\r
2 CXL 1.1 Register definitions\r
3\r
4 This file contains the register definitions based on the Compute Express Link\r
5 (CXL) Specification Revision 1.1.\r
6\r
7Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>\r
8SPDX-License-Identifier: BSD-2-Clause-Patent\r
9\r
10**/\r
11\r
12#ifndef _CXL11_H_\r
13#define _CXL11_H_\r
14\r
15#include <IndustryStandard/Pci.h>\r
16//\r
17// DVSEC Vendor ID\r
18// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1 - Table 58\r
19// (subject to change as per CXL assigned Vendor ID)\r
20//\r
21#define INTEL_CXL_DVSEC_VENDOR_ID 0x8086\r
22\r
23//\r
24// CXL Flex Bus Device default device and function number\r
25// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1\r
26//\r
27#define CXL_DEV_DEV 0\r
28#define CXL_DEV_FUNC 0\r
29\r
30//\r
31// Ensure proper structure formats\r
32//\r
33#pragma pack(1)\r
34\r
29d59baa
MK		 35/**\r
36 Macro used to verify the size of a data type at compile time and trigger a\r
37 STATIC_ASSERT() with an error message if the size of the data type does not\r
38 match the expected size.\r
39\r
40 @param TypeName Type name of data type to verify.\r
41 @param ExpectedSize The expected size, in bytes, of the data type specified\r
42 by TypeName.\r
43**/\r
44#define CXL_11_SIZE_ASSERT(TypeName, ExpectedSize) \\r
45 STATIC_ASSERT ( \\r
46 sizeof (TypeName) == ExpectedSize, \\r
47 "Size of " #TypeName \\r
48 " does not meet CXL 1.1 Specification requirements." \\r
49 )\r
50\r
51/**\r
52 Macro used to verify the offset of a field in a data type at compile time and\r
53 trigger a STATIC_ASSERT() with an error message if the offset of the field in\r
54 the data type does not match the expected offset.\r
55\r
56 @param TypeName Type name of data type to verify.\r
57 @param FieldName Field name in the data type specified by TypeName to\r
58 verify.\r
59 @param ExpectedOffset The expected offset, in bytes, of the field specified\r
60 by TypeName and FieldName.\r
61**/\r
62#define CXL_11_OFFSET_ASSERT(TypeName, FieldName, ExpectedOffset) \\r
63 STATIC_ASSERT ( \\r
64 OFFSET_OF (TypeName, FieldName) == ExpectedOffset, \\r
65 "Offset of " #TypeName "." #FieldName \\r
66 " does not meet CXL 1.1 Specification requirements." \\r
67 )\r
68\r
c25f146d
JA		 69///\r
70/// The PCIe DVSEC for Flex Bus Device\r
71///@{\r
72typedef union {\r
73 struct {\r
74 UINT16 CacheCapable : 1; // bit 0\r
75 UINT16 IoCapable : 1; // bit 1\r
76 UINT16 MemCapable : 1; // bit 2\r
77 UINT16 MemHwInitMode : 1; // bit 3\r
78 UINT16 HdmCount : 2; // bit 4..5\r
79 UINT16 Reserved1 : 8; // bit 6..13\r
80 UINT16 ViralCapable : 1; // bit 14\r
81 UINT16 Reserved2 : 1; // bit 15\r
82 } Bits;\r
83 UINT16 Uint16;\r
84} CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY;\r
85\r
86typedef union {\r
87 struct {\r
88 UINT16 CacheEnable : 1; // bit 0\r
89 UINT16 IoEnable : 1; // bit 1\r
90 UINT16 MemEnable : 1; // bit 2\r
91 UINT16 CacheSfCoverage : 5; // bit 3..7\r
92 UINT16 CacheSfGranularity : 3; // bit 8..10\r
93 UINT16 CacheCleanEviction : 1; // bit 11\r
94 UINT16 Reserved1 : 2; // bit 12..13\r
95 UINT16 ViralEnable : 1; // bit 14\r
96 UINT16 Reserved2 : 1; // bit 15\r
97 } Bits;\r
98 UINT16 Uint16;\r
99} CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL;\r
100\r
101typedef union {\r
102 struct {\r
103 UINT16 Reserved1 : 14; // bit 0..13\r
104 UINT16 ViralStatus : 1; // bit 14\r
105 UINT16 Reserved2 : 1; // bit 15\r
106 } Bits;\r
107 UINT16 Uint16;\r
108} CXL_DVSEC_FLEX_BUS_DEVICE_STATUS;\r
109\r
110typedef union {\r
111 struct {\r
112 UINT16 Reserved1 : 1; // bit 0\r
113 UINT16 Reserved2 : 1; // bit 1\r
114 UINT16 Reserved3 : 1; // bit 2\r
115 UINT16 Reserved4 : 13; // bit 3..15\r
116 } Bits;\r
117 UINT16 Uint16;\r
118} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2;\r
119\r
120typedef union {\r
121 struct {\r
122 UINT16 Reserved1 : 1; // bit 0\r
123 UINT16 Reserved2 : 1; // bit 1\r
124 UINT16 Reserved3 : 14; // bit 2..15\r
125 } Bits;\r
126 UINT16 Uint16;\r
127} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2;\r
128\r
129typedef union {\r
130 struct {\r
131 UINT16 ConfigLock : 1; // bit 0\r
132 UINT16 Reserved1 : 15; // bit 1..15\r
133 } Bits;\r
134 UINT16 Uint16;\r
135} CXL_DVSEC_FLEX_BUS_DEVICE_LOCK;\r
136\r
137typedef union {\r
138 struct {\r
139 UINT32 MemorySizeHigh : 32; // bit 0..31\r
140 } Bits;\r
141 UINT32 Uint32;\r
142} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH;\r
143\r
144typedef union {\r
145 struct {\r
146 UINT32 MemoryInfoValid : 1; // bit 0\r
147 UINT32 MemoryActive : 1; // bit 1\r
148 UINT32 MediaType : 3; // bit 2..4\r
149 UINT32 MemoryClass : 3; // bit 5..7\r
150 UINT32 DesiredInterleave : 3; // bit 8..10\r
151 UINT32 Reserved : 17; // bit 11..27\r
152 UINT32 MemorySizeLow : 4; // bit 28..31\r
153 } Bits;\r
154 UINT32 Uint32;\r
155} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW;\r
156\r
157typedef union {\r
158 struct {\r
159 UINT32 MemoryBaseHigh : 32; // bit 0..31\r
160 } Bits;\r
161 UINT32 Uint32;\r
162} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH;\r
163\r
164typedef union {\r
165 struct {\r
166 UINT32 Reserved : 28; // bit 0..27\r
167 UINT32 MemoryBaseLow : 4; // bit 28..31\r
168 } Bits;\r
169 UINT32 Uint32;\r
170} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW;\r
171\r
172\r
173typedef union {\r
174 struct {\r
175 UINT32 MemorySizeHigh : 32; // bit 0..31\r
176 } Bits;\r
177 UINT32 Uint32;\r
178} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH;\r
179\r
180typedef union {\r
181 struct {\r
182 UINT32 MemoryInfoValid : 1; // bit 0\r
183 UINT32 MemoryActive : 1; // bit 1\r
184 UINT32 MediaType : 3; // bit 2..4\r
185 UINT32 MemoryClass : 3; // bit 5..7\r
186 UINT32 DesiredInterleave : 3; // bit 8..10\r
187 UINT32 Reserved : 17; // bit 11..27\r
188 UINT32 MemorySizeLow : 4; // bit 28..31\r
189 } Bits;\r
190 UINT32 Uint32;\r
191} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW;\r
192\r
193typedef union {\r
194 struct {\r
195 UINT32 MemoryBaseHigh : 32; // bit 0..31\r
196 } Bits;\r
197 UINT32 Uint32;\r
198} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH;\r
199\r
200typedef union {\r
201 struct {\r
202 UINT32 Reserved : 28; // bit 0..27\r
203 UINT32 MemoryBaseLow : 4; // bit 28..31\r
204 } Bits;\r
205 UINT32 Uint32;\r
206} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW;\r
207\r
208//\r
209// Flex Bus Device DVSEC ID\r
210// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1, Table 58\r
211//\r
212#define FLEX_BUS_DEVICE_DVSEC_ID 0\r
213\r
214//\r
215// PCIe DVSEC for Flex Bus Device\r
216// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1, Figure 95\r
217//\r
218typedef struct {\r
219 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0\r
220 PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; // offset 4\r
221 PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; // offset 8\r
222 CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY DeviceCapability; // offset 10\r
223 CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL DeviceControl; // offset 12\r
224 CXL_DVSEC_FLEX_BUS_DEVICE_STATUS DeviceStatus; // offset 14\r
225 CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2 DeviceControl2; // offset 16\r
226 CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2 DeviceStatus2; // offset 18\r
227 CXL_DVSEC_FLEX_BUS_DEVICE_LOCK DeviceLock; // offset 20\r
228 UINT16 Reserved; // offset 22\r
229 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH DeviceRange1SizeHigh; // offset 24\r
230 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW DeviceRange1SizeLow; // offset 28\r
231 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH DeviceRange1BaseHigh; // offset 32\r
232 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW DeviceRange1BaseLow; // offset 36\r
233 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH DeviceRange2SizeHigh; // offset 40\r
234 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW DeviceRange2SizeLow; // offset 44\r
235 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH DeviceRange2BaseHigh; // offset 48\r
236 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW DeviceRange2BaseLow; // offset 52\r
237} CXL_1_1_DVSEC_FLEX_BUS_DEVICE;\r
29d59baa
MK		 238\r
239CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, Header , 0x00);\r
240CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DesignatedVendorSpecificHeader1, 0x04);\r
241CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DesignatedVendorSpecificHeader2, 0x08);\r
242CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceCapability , 0x0A);\r
243CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceControl , 0x0C);\r
244CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceStatus , 0x0E);\r
245CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceControl2 , 0x10);\r
246CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceStatus2 , 0x12);\r
247CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceLock , 0x14);\r
248CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1SizeHigh , 0x18);\r
249CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1SizeLow , 0x1C);\r
250CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1BaseHigh , 0x20);\r
251CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1BaseLow , 0x24);\r
252CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2SizeHigh , 0x28);\r
253CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2SizeLow , 0x2C);\r
254CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2BaseHigh , 0x30);\r
255CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2BaseLow , 0x34);\r
256CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE , 0x38);\r
c25f146d
JA		 257///@}\r
258\r
259///\r
260/// PCIe DVSEC for FLex Bus Port\r
261///@{\r
262typedef union {\r
263 struct {\r
264 UINT16 CacheCapable : 1; // bit 0\r
265 UINT16 IoCapable : 1; // bit 1\r
266 UINT16 MemCapable : 1; // bit 2\r
267 UINT16 Reserved : 13; // bit 3..15\r
268 } Bits;\r
269 UINT16 Uint16;\r
270} CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY;\r
271\r
272typedef union {\r
273 struct {\r
274 UINT16 CacheEnable : 1; // bit 0\r
275 UINT16 IoEnable : 1; // bit 1\r
276 UINT16 MemEnable : 1; // bit 2\r
277 UINT16 CxlSyncBypassEnable : 1; // bit 3\r
278 UINT16 DriftBufferEnable : 1; // bit 4\r
279 UINT16 Reserved : 3; // bit 5..7\r
280 UINT16 Retimer1Present : 1; // bit 8\r
281 UINT16 Retimer2Present : 1; // bit 9\r
282 UINT16 Reserved2 : 6; // bit 10..15\r
283 } Bits;\r
284 UINT16 Uint16;\r
285} CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL;\r
286\r
287typedef union {\r
288 struct {\r
289 UINT16 CacheEnable : 1; // bit 0\r
290 UINT16 IoEnable : 1; // bit 1\r
291 UINT16 MemEnable : 1; // bit 2\r
292 UINT16 CxlSyncBypassEnable : 1; // bit 3\r
293 UINT16 DriftBufferEnable : 1; // bit 4\r
294 UINT16 Reserved : 3; // bit 5..7\r
295 UINT16 CxlCorrectableProtocolIdFramingError : 1; // bit 8\r
296 UINT16 CxlUncorrectableProtocolIdFramingError : 1; // bit 9\r
297 UINT16 CxlUnexpectedProtocolIdDropped : 1; // bit 10\r
298 UINT16 Reserved2 : 5; // bit 11..15\r
299 } Bits;\r
300 UINT16 Uint16;\r
301} CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS;\r
302\r
303//\r
304// Flex Bus Port DVSEC ID\r
305// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3, Table 62\r
306//\r
307#define FLEX_BUS_PORT_DVSEC_ID 7\r
308\r
309//\r
310// PCIe DVSEC for Flex Bus Port\r
311// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3, Figure 99\r
312//\r
313typedef struct {\r
314 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0\r
315 PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; // offset 4\r
316 PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; // offset 8\r
317 CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY PortCapability; // offset 10\r
318 CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL PortControl; // offset 12\r
319 CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS PortStatus; // offset 14\r
320} CXL_1_1_DVSEC_FLEX_BUS_PORT;\r
29d59baa
MK		 321\r
322CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, Header , 0x00);\r
323CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, DesignatedVendorSpecificHeader1, 0x04);\r
324CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, DesignatedVendorSpecificHeader2, 0x08);\r
325CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortCapability , 0x0A);\r
326CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortControl , 0x0C);\r
327CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortStatus , 0x0E);\r
328CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT , 0x10);\r
c25f146d
JA		 329///@}\r
330\r
331///\r
332/// CXL 1.1 Upstream and Downstream Port Subsystem Component registers\r
333///\r
334\r
335/// The CXL.Cache and CXL.Memory Architectural register definitions\r
336/// Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1\r
337///@{\r
338\r
339#define CXL_CAPABILITY_HEADER_OFFSET 0\r
340typedef union {\r
341 struct {\r
342 UINT32 CxlCapabilityId : 16; // bit 0..15\r
343 UINT32 CxlCapabilityVersion : 4; // bit 16..19\r
344 UINT32 CxlCacheMemVersion : 4; // bit 20..23\r
345 UINT32 ArraySize : 8; // bit 24..31\r
346 } Bits;\r
347 UINT32 Uint32;\r
348} CXL_CAPABILITY_HEADER;\r
349\r
350#define CXL_RAS_CAPABILITY_HEADER_OFFSET 4\r
351typedef union {\r
352 struct {\r
353 UINT32 CxlCapabilityId : 16; // bit 0..15\r
354 UINT32 CxlCapabilityVersion : 4; // bit 16..19\r
355 UINT32 CxlRasCapabilityPointer : 12; // bit 20..31\r
356 } Bits;\r
357 UINT32 Uint32;\r
358} CXL_RAS_CAPABILITY_HEADER;\r
359\r
360#define CXL_SECURITY_CAPABILITY_HEADER_OFFSET 8\r
361typedef union {\r
362 struct {\r
363 UINT32 CxlCapabilityId : 16; // bit 0..15\r
364 UINT32 CxlCapabilityVersion : 4; // bit 16..19\r
365 UINT32 CxlSecurityCapabilityPointer : 12; // bit 20..31\r
366 } Bits;\r
367 UINT32 Uint32;\r
368} CXL_SECURITY_CAPABILITY_HEADER;\r
369\r
370#define CXL_LINK_CAPABILITY_HEADER_OFFSET 0xC\r
371typedef union {\r
372 struct {\r
373 UINT32 CxlCapabilityId : 16; // bit 0..15\r
374 UINT32 CxlCapabilityVersion : 4; // bit 16..19\r
375 UINT32 CxlLinkCapabilityPointer : 12; // bit 20..31\r
376 } Bits;\r
377 UINT32 Uint32;\r
378} CXL_LINK_CAPABILITY_HEADER;\r
379\r
380typedef union {\r
381 struct {\r
382 UINT32 CacheDataParity : 1; // bit 0..0\r
383 UINT32 CacheAddressParity : 1; // bit 1..1\r
384 UINT32 CacheByteEnableParity : 1; // bit 2..2\r
385 UINT32 CacheDataEcc : 1; // bit 3..3\r
386 UINT32 MemDataParity : 1; // bit 4..4\r
387 UINT32 MemAddressParity : 1; // bit 5..5\r
388 UINT32 MemByteEnableParity : 1; // bit 6..6\r
389 UINT32 MemDataEcc : 1; // bit 7..7\r
390 UINT32 ReInitThreshold : 1; // bit 8..8\r
391 UINT32 RsvdEncodingViolation : 1; // bit 9..9\r
392 UINT32 PoisonReceived : 1; // bit 10..10\r
393 UINT32 ReceiverOverflow : 1; // bit 11..11\r
394 UINT32 Reserved : 20; // bit 12..31\r
395 } Bits;\r
396 UINT32 Uint32;\r
397} CXL_1_1_UNCORRECTABLE_ERROR_STATUS;\r
398\r
399typedef union {\r
400 struct {\r
401 UINT32 CacheDataParityMask : 1; // bit 0..0\r
402 UINT32 CacheAddressParityMask : 1; // bit 1..1\r
403 UINT32 CacheByteEnableParityMask : 1; // bit 2..2\r
404 UINT32 CacheDataEccMask : 1; // bit 3..3\r
405 UINT32 MemDataParityMask : 1; // bit 4..4\r
406 UINT32 MemAddressParityMask : 1; // bit 5..5\r
407 UINT32 MemByteEnableParityMask : 1; // bit 6..6\r
408 UINT32 MemDataEccMask : 1; // bit 7..7\r
409 UINT32 ReInitThresholdMask : 1; // bit 8..8\r
410 UINT32 RsvdEncodingViolationMask : 1; // bit 9..9\r
411 UINT32 PoisonReceivedMask : 1; // bit 10..10\r
412 UINT32 ReceiverOverflowMask : 1; // bit 11..11\r
413 UINT32 Reserved : 20; // bit 12..31\r
414 } Bits;\r
415 UINT32 Uint32;\r
416} CXL_1_1_UNCORRECTABLE_ERROR_MASK;\r
417\r
418typedef union {\r
419 struct {\r
420 UINT32 CacheDataParitySeverity : 1; // bit 0..0\r
421 UINT32 CacheAddressParitySeverity : 1; // bit 1..1\r
422 UINT32 CacheByteEnableParitySeverity : 1; // bit 2..2\r
423 UINT32 CacheDataEccSeverity : 1; // bit 3..3\r
424 UINT32 MemDataParitySeverity : 1; // bit 4..4\r
425 UINT32 MemAddressParitySeverity : 1; // bit 5..5\r
426 UINT32 MemByteEnableParitySeverity : 1; // bit 6..6\r
427 UINT32 MemDataEccSeverity : 1; // bit 7..7\r
428 UINT32 ReInitThresholdSeverity : 1; // bit 8..8\r
429 UINT32 RsvdEncodingViolationSeverity : 1; // bit 9..9\r
430 UINT32 PoisonReceivedSeverity : 1; // bit 10..10\r
431 UINT32 ReceiverOverflowSeverity : 1; // bit 11..11\r
432 UINT32 Reserved : 20; // bit 12..31\r
433 } Bits;\r
434 UINT32 Uint32;\r
435} CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY;\r
436\r
437typedef union {\r
438 struct {\r
439 UINT32 CacheDataEcc : 1; // bit 0..0\r
440 UINT32 MemoryDataEcc : 1; // bit 1..1\r
441 UINT32 CrcThreshold : 1; // bit 2..2\r
442 UINT32 RetryThreshold : 1; // bit 3..3\r
443 UINT32 CachePoisonReceived : 1; // bit 4..4\r
444 UINT32 MemoryPoisonReceived : 1; // bit 5..5\r
445 UINT32 PhysicalLayerError : 1; // bit 6..6\r
446 UINT32 Reserved : 25; // bit 7..31\r
447 } Bits;\r
448 UINT32 Uint32;\r
449} CXL_CORRECTABLE_ERROR_STATUS;\r
450\r
451typedef union {\r
452 struct {\r
453 UINT32 CacheDataEccMask : 1; // bit 0..0\r
454 UINT32 MemoryDataEccMask : 1; // bit 1..1\r
455 UINT32 CrcThresholdMask : 1; // bit 2..2\r
456 UINT32 RetryThresholdMask : 1; // bit 3..3\r
457 UINT32 CachePoisonReceivedMask : 1; // bit 4..4\r
458 UINT32 MemoryPoisonReceivedMask : 1; // bit 5..5\r
459 UINT32 PhysicalLayerErrorMask : 1; // bit 6..6\r
460 UINT32 Reserved : 25; // bit 7..31\r
461 } Bits;\r
462 UINT32 Uint32;\r
463} CXL_CORRECTABLE_ERROR_MASK;\r
464\r
465typedef union {\r
466 struct {\r
467 UINT32 FirstErrorPointer : 4; // bit 0..3\r
468 UINT32 Reserved1 : 5; // bit 4..8\r
469 UINT32 MultipleHeaderRecordingCapability : 1; // bit 9..9\r
470 UINT32 Reserved2 : 3; // bit 10..12\r
471 UINT32 PoisonEnabled : 1; // bit 13..13\r
472 UINT32 Reserved3 : 18; // bit 14..31\r
473 } Bits;\r
474 UINT32 Uint32;\r
475} CXL_ERROR_CAPABILITIES_AND_CONTROL;\r
476\r
477typedef struct {\r
478 CXL_1_1_UNCORRECTABLE_ERROR_STATUS UncorrectableErrorStatus;\r
479 CXL_1_1_UNCORRECTABLE_ERROR_MASK UncorrectableErrorMask;\r
480 CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY UncorrectableErrorSeverity;\r
481 CXL_CORRECTABLE_ERROR_STATUS CorrectableErrorStatus;\r
482 CXL_CORRECTABLE_ERROR_MASK CorrectableErrorMask;\r
483 CXL_ERROR_CAPABILITIES_AND_CONTROL ErrorCapabilitiesAndControl;\r
484 UINT32 HeaderLog[16];\r
485} CXL_1_1_RAS_CAPABILITY_STRUCTURE;\r
486\r
29d59baa
MK		 487CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorStatus , 0x00);\r
488CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorMask , 0x04);\r
489CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorSeverity , 0x08);\r
490CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, CorrectableErrorStatus , 0x0C);\r
491CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, CorrectableErrorMask , 0x10);\r
492CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, ErrorCapabilitiesAndControl, 0x14);\r
493CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, HeaderLog , 0x18);\r
494CXL_11_SIZE_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE , 0x58);\r
495\r
c25f146d
JA		 496typedef union {\r
497 struct {\r
498 UINT32 DeviceTrustLevel : 2; // bit 0..1\r
499 UINT32 Reserved : 30; // bit 2..31\r
500 } Bits;\r
501 UINT32 Uint32;\r
502} CXL_1_1_SECURITY_POLICY;\r
503\r
504typedef struct {\r
505 CXL_1_1_SECURITY_POLICY SecurityPolicy;\r
506} CXL_1_1_SECURITY_CAPABILITY_STRUCTURE;\r
507\r
29d59baa
MK		 508CXL_11_OFFSET_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE, SecurityPolicy, 0x0);\r
509CXL_11_SIZE_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE, 0x4);\r
510\r
c25f146d
JA		 511typedef union {\r
512 struct {\r
513 UINT64 CxlLinkVersionSupported : 4; // bit 0..3\r
514 UINT64 CxlLinkVersionReceived : 4; // bit 4..7\r
515 UINT64 LlrWrapValueSupported : 8; // bit 8..15\r
516 UINT64 LlrWrapValueReceived : 8; // bit 16..23\r
517 UINT64 NumRetryReceived : 5; // bit 24..28\r
518 UINT64 NumPhyReinitReceived : 5; // bit 29..33\r
519 UINT64 WrPtrReceived : 8; // bit 34..41\r
520 UINT64 EchoEseqReceived : 8; // bit 42..49\r
521 UINT64 NumFreeBufReceived : 8; // bit 50..57\r
522 UINT64 Reserved : 6; // bit 58..63\r
523 } Bits;\r
524 UINT64 Uint64;\r
525} CXL_LINK_LAYER_CAPABILITY;\r
526\r
527typedef union {\r
528 struct {\r
529 UINT16 LlReset : 1; // bit 0..0\r
530 UINT16 LlInitStall : 1; // bit 1..1\r
531 UINT16 LlCrdStall : 1; // bit 2..2\r
532 UINT16 InitState : 2; // bit 3..4\r
533 UINT16 LlRetryBufferConsumed : 8; // bit 5..12\r
534 UINT16 Reserved : 3; // bit 13..15\r
535 } Bits;\r
29d59baa 536 UINT64 Uint64;\r
c25f146d
JA		 537} CXL_LINK_LAYER_CONTROL_AND_STATUS;\r
538\r
539typedef union {\r
540 struct {\r
541 UINT64 CacheReqCredits : 10; // bit 0..9\r
542 UINT64 CacheRspCredits : 10; // bit 10..19\r
543 UINT64 CacheDataCredits : 10; // bit 20..29\r
544 UINT64 MemReqRspCredits : 10; // bit 30..39\r
545 UINT64 MemDataCredits : 10; // bit 40..49\r
546 } Bits;\r
547 UINT64 Uint64;\r
548} CXL_LINK_LAYER_RX_CREDIT_CONTROL;\r
549\r
550typedef union {\r
551 struct {\r
552 UINT64 CacheReqCredits : 10; // bit 0..9\r
553 UINT64 CacheRspCredits : 10; // bit 10..19\r
554 UINT64 CacheDataCredits : 10; // bit 20..29\r
555 UINT64 MemReqRspCredits : 10; // bit 30..39\r
556 UINT64 MemDataCredits : 10; // bit 40..49\r
557 } Bits;\r
558 UINT64 Uint64;\r
559} CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS;\r
560\r
561typedef union {\r
562 struct {\r
563 UINT64 CacheReqCredits : 10; // bit 0..9\r
564 UINT64 CacheRspCredits : 10; // bit 10..19\r
565 UINT64 CacheDataCredits : 10; // bit 20..29\r
566 UINT64 MemReqRspCredits : 10; // bit 30..39\r
567 UINT64 MemDataCredits : 10; // bit 40..49\r
568 } Bits;\r
569 UINT64 Uint64;\r
570} CXL_LINK_LAYER_TX_CREDIT_STATUS;\r
571\r
572typedef union {\r
573 struct {\r
574 UINT32 AckForceThreshold : 8; // bit 0..7\r
575 UINT32 AckFLushRetimer : 10; // bit 8..17\r
576 } Bits;\r
29d59baa 577 UINT64 Uint64;\r
c25f146d
JA		 578} CXL_LINK_LAYER_ACK_TIMER_CONTROL;\r
579\r
580typedef union {\r
581 struct {\r
582 UINT32 MdhDisable : 1; // bit 0..0\r
583 UINT32 Reserved : 31; // bit 1..31\r
584 } Bits;\r
29d59baa 585 UINT64 Uint64;\r
c25f146d
JA		 586} CXL_LINK_LAYER_DEFEATURE;\r
587\r
588typedef struct {\r
589 CXL_LINK_LAYER_CAPABILITY LinkLayerCapability;\r
590 CXL_LINK_LAYER_CONTROL_AND_STATUS LinkLayerControlStatus;\r
591 CXL_LINK_LAYER_RX_CREDIT_CONTROL LinkLayerRxCreditControl;\r
592 CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS LinkLayerRxCreditReturnStatus;\r
593 CXL_LINK_LAYER_TX_CREDIT_STATUS LinkLayerTxCreditStatus;\r
594 CXL_LINK_LAYER_ACK_TIMER_CONTROL LinkLayerAckTimerControl;\r
595 CXL_LINK_LAYER_DEFEATURE LinkLayerDefeature;\r
596} CXL_1_1_LINK_CAPABILITY_STRUCTURE;\r
597\r
29d59baa
MK		 598CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerCapability , 0x00);\r
599CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerControlStatus , 0x08);\r
600CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerRxCreditControl , 0x10);\r
601CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerRxCreditReturnStatus, 0x18);\r
602CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerTxCreditStatus , 0x20);\r
603CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerAckTimerControl , 0x28);\r
604CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerDefeature , 0x30);\r
605CXL_11_SIZE_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE , 0x38);\r
606\r
c25f146d
JA		 607#define CXL_IO_ARBITRATION_CONTROL_OFFSET 0x180\r
608typedef union {\r
609 struct {\r
610 UINT32 Reserved1 : 4; // bit 0..3\r
611 UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7\r
612 UINT32 Reserved2 : 24; // bit 8..31\r
613 } Bits;\r
614 UINT32 Uint32;\r
615} CXL_IO_ARBITRATION_CONTROL;\r
616\r
29d59baa
MK		 617CXL_11_SIZE_ASSERT (CXL_IO_ARBITRATION_CONTROL, 0x4);\r
618\r
c25f146d
JA		 619#define CXL_CACHE_MEMORY_ARBITRATION_CONTROL_OFFSET 0x1C0\r
620typedef union {\r
621 struct {\r
622 UINT32 Reserved1 : 4; // bit 0..3\r
623 UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7\r
624 UINT32 Reserved2 : 24; // bit 8..31\r
625 } Bits;\r
626 UINT32 Uint32;\r
627} CXL_CACHE_MEMORY_ARBITRATION_CONTROL;\r
29d59baa
MK		 628\r
629CXL_11_SIZE_ASSERT (CXL_CACHE_MEMORY_ARBITRATION_CONTROL, 0x4);\r
630\r
c25f146d
JA		 631///@}\r
632\r
633/// The CXL.RCRB base register definition\r
634/// Based on chapter 7.3 of Compute Express Link Specification Revision: 1.1\r
635///@{\r
636typedef union {\r
637 struct {\r
638 UINT64 RcrbEnable : 1; // bit 0..0\r
639 UINT64 Reserved : 12; // bit 1..12\r
640 UINT64 RcrbBaseAddress : 51; // bit 13..63\r
641 } Bits;\r
642 UINT64 Uint64;\r
643} CXL_RCRB_BASE;\r
29d59baa
MK		 644\r
645CXL_11_SIZE_ASSERT (CXL_RCRB_BASE, 0x8);\r
646\r
c25f146d
JA		 647///@}\r
648\r
649#pragma pack()\r
650\r
651//\r
652// CXL Downstream / Upstream Port RCRB space register offsets\r
653// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.1 - Figure 97\r
654//\r
655#define CXL_PORT_RCRB_MEMBAR0_LOW_OFFSET 0x010\r
656#define CXL_PORT_RCRB_MEMBAR0_HIGH_OFFSET 0x014\r
657#define CXL_PORT_RCRB_EXTENDED_CAPABILITY_BASE_OFFSET 0x100\r
658\r
659#endif\r
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