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846ea5f5 GM |
1 | /** @file\r |
2 | DMA Remapping Reporting (DMAR) ACPI table definition from Intel(R)\r | |
3 | Virtualization Technology for Directed I/O (VT-D) Architecture Specification.\r | |
4 | \r | |
12dd064a | 5 | Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.<BR>\r |
9344f092 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
846ea5f5 GM |
7 | \r |
8 | @par Revision Reference:\r | |
9 | - Intel(R) Virtualization Technology for Directed I/O (VT-D) Architecture\r | |
12dd064a | 10 | Specification v4.0, Dated June 2022.\r |
5c3cdebf | 11 | https://software.intel.com/content/dam/develop/external/us/en/documents/vt-directed-io-spec.pdf\r |
846ea5f5 GM |
12 | \r |
13 | @par Glossary:\r | |
14 | - HPET - High Precision Event Timer\r | |
15 | - NUMA - Non-uniform Memory Access\r | |
16 | **/\r | |
2f88bd3a | 17 | \r |
846ea5f5 GM |
18 | #ifndef _DMA_REMAPPING_REPORTING_TABLE_H_\r |
19 | #define _DMA_REMAPPING_REPORTING_TABLE_H_\r | |
20 | \r | |
83a45784 JY |
21 | #include <IndustryStandard/Acpi.h>\r |
22 | \r | |
846ea5f5 GM |
23 | #pragma pack(1)\r |
24 | \r | |
25 | ///\r | |
26 | /// DMA-Remapping Reporting Structure definitions from section 8.1\r | |
27 | ///@{\r | |
2f88bd3a | 28 | #define EFI_ACPI_DMAR_REVISION 0x01\r |
846ea5f5 | 29 | \r |
8ab0bd23 HW |
30 | #define EFI_ACPI_DMAR_FLAGS_INTR_REMAP BIT0\r |
31 | #define EFI_ACPI_DMAR_FLAGS_X2APIC_OPT_OUT BIT1\r | |
32 | #define EFI_ACPI_DMAR_FLAGS_DMA_CTRL_PLATFORM_OPT_IN_FLAG BIT2\r | |
846ea5f5 GM |
33 | ///@}\r |
34 | \r | |
35 | ///\r | |
36 | /// Remapping Structure Types definitions from section 8.2\r | |
37 | ///@{\r | |
2f88bd3a MK |
38 | #define EFI_ACPI_DMAR_TYPE_DRHD 0x00\r |
39 | #define EFI_ACPI_DMAR_TYPE_RMRR 0x01\r | |
40 | #define EFI_ACPI_DMAR_TYPE_ATSR 0x02\r | |
41 | #define EFI_ACPI_DMAR_TYPE_RHSA 0x03\r | |
42 | #define EFI_ACPI_DMAR_TYPE_ANDD 0x04\r | |
43 | #define EFI_ACPI_DMAR_TYPE_SATC 0x05\r | |
12dd064a | 44 | #define EFI_ACPI_DMAR_TYPE_SIDP 0x06\r |
846ea5f5 GM |
45 | ///@}\r |
46 | \r | |
47 | ///\r | |
48 | /// DMA-Remapping Hardware Unit definitions from section 8.3\r | |
49 | ///\r | |
50 | #define EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL BIT0\r | |
51 | \r | |
52 | ///\r | |
53 | /// DMA-Remapping Device Scope Entry Structure definitions from section 8.3.1\r | |
54 | ///@{\r | |
55 | #define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT 0x01\r | |
56 | #define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_BRIDGE 0x02\r | |
57 | #define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_IOAPIC 0x03\r | |
58 | #define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_MSI_CAPABLE_HPET 0x04\r | |
59 | #define EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_ACPI_NAMESPACE_DEVICE 0x05\r | |
12dd064a RK |
60 | \r |
61 | #define EFI_ACPI_DEVICE_SCOPE_REQ_WO_PASID_NESTED_NOTALLOWED BIT0\r | |
62 | #define EFI_ACPI_DEVICE_SCOPE_REQ_WO_PASID_PWSNP_NOTALLOWED BIT1\r | |
63 | #define EFI_ACPI_DEVICE_SCOPE_REQ_WO_PASID_PGSNP_NOTALLOWED BIT2\r | |
64 | #define EFI_ACPI_DEVICE_SCOPE_REQ_WO_PASID_ATC_HARDENED BIT3\r | |
65 | #define EFI_ACPI_DEVICE_SCOPE_REQ_WO_PASID_ATC_REQUIRED BIT4\r | |
846ea5f5 GM |
66 | ///@}\r |
67 | \r | |
68 | ///\r | |
69 | /// Root Port ATS Capability Reporting Structure definitions from section 8.5\r | |
70 | ///\r | |
2f88bd3a | 71 | #define EFI_ACPI_DMAR_ATSR_FLAGS_ALL_PORTS BIT0\r |
846ea5f5 GM |
72 | \r |
73 | ///\r | |
74 | /// Definition for DMA Remapping Structure Header\r | |
75 | ///\r | |
76 | typedef struct {\r | |
2f88bd3a MK |
77 | UINT16 Type;\r |
78 | UINT16 Length;\r | |
846ea5f5 GM |
79 | } EFI_ACPI_DMAR_STRUCTURE_HEADER;\r |
80 | \r | |
81 | ///\r | |
82 | /// Definition for DMA-Remapping PCI Path\r | |
83 | ///\r | |
84 | typedef struct {\r | |
2f88bd3a MK |
85 | UINT8 Device;\r |
86 | UINT8 Function;\r | |
846ea5f5 GM |
87 | } EFI_ACPI_DMAR_PCI_PATH;\r |
88 | \r | |
89 | ///\r | |
90 | /// Device Scope Structure is defined in section 8.3.1\r | |
91 | ///\r | |
92 | typedef struct {\r | |
12dd064a RK |
93 | UINT8 Type;\r |
94 | UINT8 Length;\r | |
95 | UINT8 Flags;\r | |
96 | UINT8 Reserved;\r | |
97 | UINT8 EnumerationId;\r | |
98 | UINT8 StartBusNumber;\r | |
846ea5f5 GM |
99 | } EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER;\r |
100 | \r | |
101 | /**\r | |
102 | DMA-remapping hardware unit definition (DRHD) structure is defined in\r | |
103 | section 8.3. This uniquely represents a remapping hardware unit present\r | |
104 | in the platform. There must be at least one instance of this structure\r | |
105 | for each PCI segment in the platform.\r | |
106 | **/\r | |
107 | typedef struct {\r | |
2f88bd3a MK |
108 | EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r |
109 | \r | |
846ea5f5 GM |
110 | /**\r |
111 | - Bit[0]: INCLUDE_PCI_ALL\r | |
112 | - If Set, this remapping hardware unit has under its scope all\r | |
113 | PCI compatible devices in the specified Segment, except devices\r | |
114 | reported under the scope of other remapping hardware units for\r | |
115 | the same Segment.\r | |
116 | - If Clear, this remapping hardware unit has under its scope only\r | |
117 | devices in the specified Segment that are explicitly identified\r | |
118 | through the DeviceScope field.\r | |
119 | - Bits[7:1] Reserved.\r | |
120 | **/\r | |
2f88bd3a | 121 | UINT8 Flags;\r |
12dd064a RK |
122 | \r |
123 | /**\r | |
124 | - Bits[3:0]: Indicates the size of the remapping hardware register set for\r | |
125 | this remapping unit. If the value in this field is N, the size\r | |
126 | of the register set is 2^N 4 KB pages\r | |
127 | - Bits[7:4]: Reserved.\r | |
128 | **/\r | |
129 | UINT8 Size;\r | |
846ea5f5 GM |
130 | ///\r |
131 | /// The PCI Segment associated with this unit.\r | |
132 | ///\r | |
2f88bd3a | 133 | UINT16 SegmentNumber;\r |
846ea5f5 GM |
134 | ///\r |
135 | /// Base address of remapping hardware register-set for this unit.\r | |
136 | ///\r | |
2f88bd3a | 137 | UINT64 RegisterBaseAddress;\r |
846ea5f5 GM |
138 | } EFI_ACPI_DMAR_DRHD_HEADER;\r |
139 | \r | |
140 | /**\r | |
141 | Reserved Memory Region Reporting Structure (RMRR) is described in section 8.4\r | |
142 | Reserved memory ranges that may be DMA targets may be reported through the\r | |
143 | RMRR structures, along with the devices that requires access to the specified\r | |
144 | reserved memory region.\r | |
145 | **/\r | |
146 | typedef struct {\r | |
2f88bd3a MK |
147 | EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r |
148 | UINT8 Reserved[2];\r | |
846ea5f5 GM |
149 | ///\r |
150 | /// PCI Segment Number associated with devices identified through\r | |
151 | /// the Device Scope field.\r | |
152 | ///\r | |
2f88bd3a | 153 | UINT16 SegmentNumber;\r |
846ea5f5 GM |
154 | ///\r |
155 | /// Base address of 4KB-aligned reserved memory region\r | |
156 | ///\r | |
2f88bd3a MK |
157 | UINT64 ReservedMemoryRegionBaseAddress;\r |
158 | \r | |
846ea5f5 GM |
159 | /**\r |
160 | Last address of the reserved memory region. Value in this field must be\r | |
161 | greater than the value in Reserved Memory Region Base Address field.\r | |
162 | The reserved memory region size (Limit - Base + 1) must be an integer\r | |
163 | multiple of 4KB.\r | |
164 | **/\r | |
2f88bd3a | 165 | UINT64 ReservedMemoryRegionLimitAddress;\r |
846ea5f5 GM |
166 | } EFI_ACPI_DMAR_RMRR_HEADER;\r |
167 | \r | |
168 | /**\r | |
169 | Root Port ATS Capability Reporting (ATSR) structure is defined in section 8.5.\r | |
170 | This structure is applicable only for platforms supporting Device-TLBs as\r | |
171 | reported through the Extended Capability Register. For each PCI Segment in\r | |
172 | the platform that supports Device-TLBs, BIOS provides an ATSR structure. The\r | |
173 | ATSR structures identifies PCI-Express Root-Ports supporting Address\r | |
174 | Translation Services (ATS) transactions. Software must enable ATS on endpoint\r | |
175 | devices behind a Root Port only if the Root Port is reported as supporting\r | |
176 | ATS transactions.\r | |
177 | **/\r | |
178 | typedef struct {\r | |
2f88bd3a MK |
179 | EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r |
180 | \r | |
846ea5f5 GM |
181 | /**\r |
182 | - Bit[0]: ALL_PORTS:\r | |
183 | - If Set, indicates all PCI Express Root Ports in the specified\r | |
184 | PCI Segment supports ATS transactions.\r | |
185 | - If Clear, indicates ATS transactions are supported only on\r | |
186 | Root Ports identified through the Device Scope field.\r | |
187 | - Bits[7:1] Reserved.\r | |
188 | **/\r | |
2f88bd3a MK |
189 | UINT8 Flags;\r |
190 | UINT8 Reserved;\r | |
846ea5f5 GM |
191 | ///\r |
192 | /// The PCI Segment associated with this ATSR structure\r | |
193 | ///\r | |
2f88bd3a | 194 | UINT16 SegmentNumber;\r |
846ea5f5 GM |
195 | } EFI_ACPI_DMAR_ATSR_HEADER;\r |
196 | \r | |
197 | /**\r | |
198 | Remapping Hardware Static Affinity (RHSA) is an optional structure defined\r | |
199 | in section 8.6. This is intended to be used only on NUMA platforms with\r | |
200 | Remapping hardware units and memory spanned across multiple nodes.\r | |
201 | When used, there must be a RHSA structure for each Remapping hardware unit\r | |
202 | reported through DRHD structure.\r | |
203 | **/\r | |
204 | typedef struct {\r | |
2f88bd3a MK |
205 | EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r |
206 | UINT8 Reserved[4];\r | |
846ea5f5 GM |
207 | ///\r |
208 | /// Register Base Address of this Remap hardware unit reported in the\r | |
209 | /// corresponding DRHD structure.\r | |
210 | ///\r | |
2f88bd3a | 211 | UINT64 RegisterBaseAddress;\r |
846ea5f5 GM |
212 | ///\r |
213 | /// Proximity Domain to which the Remap hardware unit identified by the\r | |
214 | /// Register Base Address field belongs.\r | |
215 | ///\r | |
2f88bd3a | 216 | UINT32 ProximityDomain;\r |
846ea5f5 GM |
217 | } EFI_ACPI_DMAR_RHSA_HEADER;\r |
218 | \r | |
219 | /**\r | |
220 | An ACPI Name-space Device Declaration (ANDD) structure is defined in section\r | |
221 | 8.7 and uniquely represents an ACPI name-space enumerated device capable of\r | |
222 | issuing DMA requests in the platform. ANDD structures are used in conjunction\r | |
223 | with Device-Scope entries of type ACPI_NAMESPACE_DEVICE.\r | |
224 | **/\r | |
225 | typedef struct {\r | |
2f88bd3a MK |
226 | EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r |
227 | UINT8 Reserved[3];\r | |
228 | \r | |
846ea5f5 GM |
229 | /**\r |
230 | Each ACPI device enumerated through an ANDD structure must have a unique\r | |
231 | value for this field. To report an ACPI device with ACPI Device Number\r | |
232 | value of X, under the scope of a DRHD unit, a Device-Scope entry of type\r | |
233 | ACPI_NAMESPACE_DEVICE is used with value of X in the Enumeration ID field.\r | |
234 | The Start Bus Number and Path fields in the Device-Scope together\r | |
235 | provides the 16-bit source-id allocated by platform for the ACPI device.\r | |
236 | **/\r | |
2f88bd3a | 237 | UINT8 AcpiDeviceNumber;\r |
846ea5f5 GM |
238 | } EFI_ACPI_DMAR_ANDD_HEADER;\r |
239 | \r | |
5c3cdebf SW |
240 | /**\r |
241 | An SoC Integrated Address Translation Cache (SATC) reporting structure is\r | |
242 | defined in section 8.8.\r | |
243 | **/\r | |
244 | typedef struct {\r | |
2f88bd3a MK |
245 | EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r |
246 | \r | |
5c3cdebf SW |
247 | /**\r |
248 | - Bit[0]: ATC_REQUIRED:\r | |
249 | - If Set, indicates that every SoC integrated device enumerated\r | |
250 | in this table has a functional requirement to enable its ATC\r | |
251 | (via the ATS capability) for device operation.\r | |
252 | - If Clear, any device enumerated in this table can operate when\r | |
253 | its respective ATC is not enabled (albeit with reduced\r | |
254 | performance or functionality).\r | |
255 | - Bits[7:1] Reserved.\r | |
256 | **/\r | |
2f88bd3a MK |
257 | UINT8 Flags;\r |
258 | UINT8 Reserved;\r | |
5c3cdebf SW |
259 | ///\r |
260 | /// The PCI Segment associated with this SATC structure. All SoC integrated\r | |
261 | /// devices within a PCI segment with same value for Flags field must be\r | |
262 | /// enumerated in the same SATC structure.\r | |
263 | ///\r | |
2f88bd3a | 264 | UINT16 SegmentNumber;\r |
5c3cdebf SW |
265 | } EFI_ACPI_DMAR_SATC_HEADER;\r |
266 | \r | |
12dd064a RK |
267 | /**\r |
268 | SoC Integrated Device Property (SIDP) Reporting Structure is defined in\r | |
269 | section 8.9.\r | |
270 | **/\r | |
271 | typedef struct {\r | |
272 | EFI_ACPI_DMAR_STRUCTURE_HEADER Header;\r | |
273 | \r | |
274 | UINT16 Reserved;\r | |
275 | ///\r | |
276 | /// The PCI Segment associated with this SIDP structure.\r | |
277 | ///\r | |
278 | UINT16 SegmentNumber;\r | |
279 | } EFI_ACPI_DMAR_SIDP_HEADER;\r | |
280 | \r | |
846ea5f5 GM |
281 | /**\r |
282 | DMA Remapping Reporting Structure Header as defined in section 8.1\r | |
283 | This header will be followed by list of Remapping Structures listed below\r | |
284 | - DMA Remapping Hardware Unit Definition (DRHD)\r | |
285 | - Reserved Memory Region Reporting (RMRR)\r | |
286 | - Root Port ATS Capability Reporting (ATSR)\r | |
287 | - Remapping Hardware Static Affinity (RHSA)\r | |
288 | - ACPI Name-space Device Declaration (ANDD)\r | |
5c3cdebf | 289 | - SoC Integrated Address Translation Cache reporting (SATC)\r |
12dd064a | 290 | - SoC Integrated Device Property reporting (SIDP)\r |
846ea5f5 GM |
291 | These structure types must by reported in numerical order.\r |
292 | i.e., All remapping structures of type 0 (DRHD) enumerated before remapping\r | |
293 | structures of type 1 (RMRR), and so forth.\r | |
294 | **/\r | |
295 | typedef struct {\r | |
2f88bd3a MK |
296 | EFI_ACPI_DESCRIPTION_HEADER Header;\r |
297 | \r | |
846ea5f5 GM |
298 | /**\r |
299 | This field indicates the maximum DMA physical addressability supported by\r | |
300 | this platform. The system address map reported by the BIOS indicates what\r | |
301 | portions of this addresses are populated. The Host Address Width (HAW) of\r | |
302 | the platform is computed as (N+1), where N is the value reported in this\r | |
303 | field.\r | |
304 | For example, for a platform supporting 40 bits of physical addressability,\r | |
305 | the value of 100111b is reported in this field.\r | |
306 | **/\r | |
2f88bd3a MK |
307 | UINT8 HostAddressWidth;\r |
308 | \r | |
846ea5f5 GM |
309 | /**\r |
310 | - Bit[0]: INTR_REMAP - If Clear, the platform does not support interrupt\r | |
311 | remapping. If Set, the platform supports interrupt remapping.\r | |
312 | - Bit[1]: X2APIC_OPT_OUT - For firmware compatibility reasons, platform\r | |
313 | firmware may Set this field to request system software to opt\r | |
314 | out of enabling Extended xAPIC (X2APIC) mode. This field is\r | |
315 | valid only when the INTR_REMAP field (bit 0) is Set.\r | |
8ab0bd23 HW |
316 | - Bit[2]: DMA_CTRL_PLATFORM_OPT_IN_FLAG - Platform firmware is\r |
317 | recommended to Set this field to report any platform initiated\r | |
318 | DMA is restricted to only reserved memory regions (reported in\r | |
319 | RMRR structures) when transferring control to system software\r | |
320 | such as on ExitBootServices().\r | |
321 | - Bits[7:3] Reserved.\r | |
846ea5f5 | 322 | **/\r |
2f88bd3a MK |
323 | UINT8 Flags;\r |
324 | UINT8 Reserved[10];\r | |
846ea5f5 GM |
325 | } EFI_ACPI_DMAR_HEADER;\r |
326 | \r | |
327 | #pragma pack()\r | |
328 | \r | |
329 | #endif\r |