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Add PCD Library instance mapping for GraphicsConsole driver.
[mirror_edk2.git] / MdePkg / Include / IndustryStandard / LegacyBiosMpTable.h
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LG		 1/*++\r
2 Defives data structures per MultiProcessor Specification Ver 1.4.\r
3 \r
4 The MultiProcessor Specification defines an enhancement to the standard \r
5 to which PC manufacturers design DOS-compatible systems.\r
6\r
7Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>\r
8This program and the accompanying materials \r
9are licensed and made available under the terms and conditions of the BSD License \r
10which accompanies this distribution. The full text of the license may be found at \r
11http://opensource.org/licenses/bsd-license.php \r
12 \r
13THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
14WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
15\r
16--*/\r
17\r
18#ifndef _LEGACY_BIOS_MPTABLE_H_\r
19#define _LEGACY_BIOS_MPTABLE_H_\r
20\r
21#define EFI_LEGACY_MP_TABLE_REV_1_4 0x04\r
22\r
23//\r
24// Define MP table structures. All are packed.\r
25//\r
26#pragma pack(1)\r
27\r
28#define EFI_LEGACY_MP_TABLE_FLOATING_POINTER_SIGNATURE SIGNATURE_32 ('_', 'M', 'P', '_')\r
29typedef struct {\r
30 UINT32 Signature;\r
31 UINT32 PhysicalAddress;\r
32 UINT8 Length;\r
33 UINT8 SpecRev;\r
34 UINT8 Checksum;\r
35 UINT8 FeatureByte1;\r
36 struct {\r
37 UINT32 Reserved1 : 6;\r
38 UINT32 MutipleClk : 1;\r
39 UINT32 Imcr : 1;\r
40 UINT32 Reserved2 : 24;\r
41 } FeatureByte2_5;\r
42} EFI_LEGACY_MP_TABLE_FLOATING_POINTER;\r
43\r
44#define EFI_LEGACY_MP_TABLE_HEADER_SIGNATURE SIGNATURE_32 ('P', 'C', 'M', 'P')\r
45typedef struct {\r
46 UINT32 Signature;\r
47 UINT16 BaseTableLength;\r
48 UINT8 SpecRev;\r
49 UINT8 Checksum;\r
50 CHAR8 OemId[8];\r
51 CHAR8 OemProductId[12];\r
52 UINT32 OemTablePointer;\r
53 UINT16 OemTableSize;\r
54 UINT16 EntryCount;\r
55 UINT32 LocalApicAddress;\r
56 UINT16 ExtendedTableLength;\r
57 UINT8 ExtendedChecksum;\r
58 UINT8 Reserved;\r
59} EFI_LEGACY_MP_TABLE_HEADER;\r
60\r
61typedef struct {\r
62 UINT8 EntryType;\r
63} EFI_LEGACY_MP_TABLE_ENTRY_TYPE;\r
64\r
65//\r
66// Entry Type 0: Processor.\r
67//\r
68#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_PROCESSOR 0x00\r
69typedef struct {\r
70 UINT8 EntryType;\r
71 UINT8 Id;\r
72 UINT8 Ver;\r
73 struct {\r
74 UINT8 Enabled : 1;\r
75 UINT8 Bsp : 1;\r
76 UINT8 Reserved : 6;\r
77 } Flags;\r
78 struct {\r
79 UINT32 Stepping : 4;\r
80 UINT32 Model : 4;\r
81 UINT32 Family : 4;\r
82 UINT32 Reserved : 20;\r
83 } Signature;\r
84 struct {\r
85 UINT32 Fpu : 1;\r
86 UINT32 Reserved1 : 6;\r
87 UINT32 Mce : 1;\r
88 UINT32 Cx8 : 1;\r
89 UINT32 Apic : 1;\r
90 UINT32 Reserved2 : 22;\r
91 } Features;\r
92 UINT32 Reserved1;\r
93 UINT32 Reserved2;\r
94} EFI_LEGACY_MP_TABLE_ENTRY_PROCESSOR;\r
95\r
96//\r
97// Entry Type 1: Bus.\r
98//\r
99#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_BUS 0x01\r
100typedef struct {\r
101 UINT8 EntryType;\r
102 UINT8 Id;\r
103 CHAR8 TypeString[6];\r
104} EFI_LEGACY_MP_TABLE_ENTRY_BUS;\r
105\r
106#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_CBUS "CBUS " // Corollary CBus\r
107#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_CBUSII "CBUSII" // Corollary CBUS II\r
108#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_EISA "EISA " // Extended ISA\r
109#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_FUTURE "FUTURE" // IEEE FutureBus\r
110#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_INTERN "INTERN" // Internal bus\r
111#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_ISA "ISA " // Industry Standard Architecture\r
112#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MBI "MBI " // Multibus I\r
113#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MBII "MBII " // Multibus II\r
114#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MCA "MCA " // Micro Channel Architecture\r
115#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MPI "MPI " // MPI\r
116#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_MPSA "MPSA " // MPSA\r
117#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_NUBUS "NUBUS " // Apple Macintosh NuBus\r
118#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_PCI "PCI " // Peripheral Component Interconnect\r
119#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_PCMCIA "PCMCIA" // PC Memory Card International Assoc.\r
120#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_TC "TC " // DEC TurboChannel\r
121#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_VL "VL " // VESA Local Bus\r
122#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_VME "VME " // VMEbus\r
123#define EFI_LEGACY_MP_TABLE_ENTRY_BUS_STRING_XPRESS "XPRESS" // Express System Bus\r
124//\r
125// Entry Type 2: I/O APIC.\r
126//\r
127#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_IOAPIC 0x02\r
128typedef struct {\r
129 UINT8 EntryType;\r
130 UINT8 Id;\r
131 UINT8 Ver;\r
132 struct {\r
133 UINT8 Enabled : 1;\r
134 UINT8 Reserved : 7;\r
135 } Flags;\r
136 UINT32 Address;\r
137} EFI_LEGACY_MP_TABLE_ENTRY_IOAPIC;\r
138\r
139//\r
140// Entry Type 3: I/O Interrupt Assignment.\r
141//\r
142#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_IO_INT 0x03\r
143typedef struct {\r
144 UINT8 EntryType;\r
145 UINT8 IntType;\r
146 struct {\r
147 UINT16 Polarity : 2;\r
148 UINT16 Trigger : 2;\r
149 UINT16 Reserved : 12;\r
150 } Flags;\r
151 UINT8 SourceBusId;\r
152 union {\r
153 struct {\r
154 UINT8 IntNo : 2;\r
155 UINT8 Dev : 5;\r
156 UINT8 Reserved : 1;\r
157 } fields;\r
158 UINT8 byte;\r
159 } SourceBusIrq;\r
160 UINT8 DestApicId;\r
161 UINT8 DestApicIntIn;\r
162} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT;\r
163\r
164typedef enum {\r
165 EfiLegacyMpTableEntryIoIntTypeInt = 0,\r
166 EfiLegacyMpTableEntryIoIntTypeNmi = 1,\r
167 EfiLegacyMpTableEntryIoIntTypeSmi = 2,\r
168 EfiLegacyMpTableEntryIoIntTypeExtInt= 3,\r
169} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_TYPE;\r
170\r
171typedef enum {\r
172 EfiLegacyMpTableEntryIoIntFlagsPolaritySpec = 0x0,\r
173 EfiLegacyMpTableEntryIoIntFlagsPolarityActiveHigh = 0x1,\r
174 EfiLegacyMpTableEntryIoIntFlagsPolarityReserved = 0x2,\r
175 EfiLegacyMpTableEntryIoIntFlagsPolarityActiveLow = 0x3,\r
176} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_FLAGS_POLARITY;\r
177\r
178typedef enum {\r
179 EfiLegacyMpTableEntryIoIntFlagsTriggerSpec = 0x0,\r
180 EfiLegacyMpTableEntryIoIntFlagsTriggerEdge = 0x1,\r
181 EfiLegacyMpTableEntryIoIntFlagsTriggerReserved = 0x2,\r
182 EfiLegacyMpTableEntryIoIntFlagsTriggerLevel = 0x3,\r
183} EFI_LEGACY_MP_TABLE_ENTRY_IO_INT_FLAGS_TRIGGER;\r
184\r
185//\r
186// Entry Type 4: Local Interrupt Assignment.\r
187//\r
188#define EFI_LEGACY_MP_TABLE_ENTRY_TYPE_LOCAL_INT 0x04\r
189typedef struct {\r
190 UINT8 EntryType;\r
191 UINT8 IntType;\r
192 struct {\r
193 UINT16 Polarity : 2;\r
194 UINT16 Trigger : 2;\r
195 UINT16 Reserved : 12;\r
196 } Flags;\r
197 UINT8 SourceBusId;\r
198 union {\r
199 struct {\r
200 UINT8 IntNo : 2;\r
201 UINT8 Dev : 5;\r
202 UINT8 Reserved : 1;\r
203 } fields;\r
204 UINT8 byte;\r
205 } SourceBusIrq;\r
206 UINT8 DestApicId;\r
207 UINT8 DestApicIntIn;\r
208} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT;\r
209\r
210typedef enum {\r
211 EfiLegacyMpTableEntryLocalIntTypeInt = 0,\r
212 EfiLegacyMpTableEntryLocalIntTypeNmi = 1,\r
213 EfiLegacyMpTableEntryLocalIntTypeSmi = 2,\r
214 EfiLegacyMpTableEntryLocalIntTypeExtInt = 3,\r
215} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_TYPE;\r
216\r
217typedef enum {\r
218 EfiLegacyMpTableEntryLocalIntFlagsPolaritySpec = 0x0,\r
219 EfiLegacyMpTableEntryLocalIntFlagsPolarityActiveHigh= 0x1,\r
220 EfiLegacyMpTableEntryLocalIntFlagsPolarityReserved = 0x2,\r
221 EfiLegacyMpTableEntryLocalIntFlagsPolarityActiveLow = 0x3,\r
222} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_FLAGS_POLARITY;\r
223\r
224typedef enum {\r
225 EfiLegacyMpTableEntryLocalIntFlagsTriggerSpec = 0x0,\r
226 EfiLegacyMpTableEntryLocalIntFlagsTriggerEdge = 0x1,\r
227 EfiLegacyMpTableEntryLocalIntFlagsTriggerReserved = 0x2,\r
228 EfiLegacyMpTableEntryLocalIntFlagsTriggerLevel = 0x3,\r
229} EFI_LEGACY_MP_TABLE_ENTRY_LOCAL_INT_FLAGS_TRIGGER;\r
230\r
231//\r
232// Entry Type 128: System Address Space Mapping.\r
233//\r
234#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_SYS_ADDR_SPACE_MAPPING 0x80\r
235typedef struct {\r
236 UINT8 EntryType;\r
237 UINT8 Length;\r
238 UINT8 BusId;\r
239 UINT8 AddressType;\r
240 UINT64 AddressBase;\r
241 UINT64 AddressLength;\r
242} EFI_LEGACY_MP_TABLE_ENTRY_EXT_SYS_ADDR_SPACE_MAPPING;\r
243\r
244typedef enum {\r
245 EfiLegacyMpTableEntryExtSysAddrSpaceMappingIo = 0,\r
246 EfiLegacyMpTableEntryExtSysAddrSpaceMappingMemory = 1,\r
247 EfiLegacyMpTableEntryExtSysAddrSpaceMappingPrefetch = 2,\r
248} EFI_LEGACY_MP_TABLE_ENTRY_EXT_SYS_ADDR_SPACE_MAPPING_TYPE;\r
249\r
250//\r
251// Entry Type 129: Bus Hierarchy.\r
252//\r
253#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_BUS_HIERARCHY 0x81\r
254typedef struct {\r
255 UINT8 EntryType;\r
256 UINT8 Length;\r
257 UINT8 BusId;\r
258 struct {\r
259 UINT8 SubtractiveDecode : 1;\r
260 UINT8 Reserved : 7;\r
261 } BusInfo;\r
262 UINT8 ParentBus;\r
263 UINT8 Reserved1;\r
264 UINT8 Reserved2;\r
265 UINT8 Reserved3;\r
266} EFI_LEGACY_MP_TABLE_ENTRY_EXT_BUS_HIERARCHY;\r
267\r
268//\r
269// Entry Type 130: Compatibility Bus Address Space Modifier.\r
270//\r
271#define EFI_LEGACY_MP_TABLE_ENTRY_EXT_TYPE_COMPAT_BUS_ADDR_SPACE_MODIFIER 0x82\r
272typedef struct {\r
273 UINT8 EntryType;\r
274 UINT8 Length;\r
275 UINT8 BusId;\r
276 struct {\r
277 UINT8 RangeMode : 1;\r
278 UINT8 Reserved : 7;\r
279 } AddrMode;\r
280 UINT32 PredefinedRangeList;\r
281} EFI_LEGACY_MP_TABLE_ENTRY_EXT_COMPAT_BUS_ADDR_SPACE_MODIFIER;\r
282\r
283#pragma pack()\r
284\r
285#endif\r
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