[mirror_edk2.git] / MdePkg / Include / IndustryStandard / Pal.h

/** @file\r
  Main PAL API's defined in IPF PAL Spec.\r
\r
  Copyright (c) 2006 - 2007, Intel Corporation\r
  All rights reserved. This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef __PAL_API_H__\r
#define __PAL_API_H__\r
\r
\r
//\r
// CacheType of PAL_CACHE_FLUSH.\r
//\r
#define PAL_CACHE_FLUSH_INSTRUCTION_ALL 	1\r
#define PAL_CACHE_FLUSH_DATA_ALL 					2\r
#define PAL_CACHE_FLUSH_ALL								3\r
#define PAL_CACHE_FLUSH_SYNC_TO_DATA   		4\r
\r
\r
//\r
// Bitmask of Opearation of PAL_CACHE_FLUSH.\r
// \r
#define PAL_CACHE_FLUSH_INVIDED_LINES			BIT0\r
#define PAL_CACHE_FLUSH_PROBE_INTERRUPT		BIT1\r
\r
/**\r
   \r
  Flush the instruction or data caches. It is required by IPF.\r
  The PAL procedure supports the Static Registers calling\r
  convention. It could be called at virtual mode and physical\r
  mode.\r
\r
  @param Index 							Index of PAL_CACHE_FLUSH within the\r
														list of PAL procedures.\r
  \r
  @param CacheType					Unsigned 64-bit integer indicating\r
														which cache to flush.\r
\r
  @param Operation 					Formatted bit vector indicating the\r
														operation of this call.\r
\r
  @param ProgressIndicator  Unsigned 64-bit integer specifying\r
                            the starting position of the flush\r
                            operation.\r
  \r
  @return R9			Unsigned 64-bit integer specifying the vector\r
									number of the pending interrupt.\r
  \r
  @return R10			Unsigned 64-bit integer specifying the\r
                  starting position of the flush operation.\r
  \r
  @return R11			Unsigned 64-bit integer specifying the vector\r
									number of the pending interrupt.\r
  \r
  @return Status	2 - Call completed without error, but a PMI\r
                  was taken during the execution of this\r
                  procedure.\r
\r
  @return Status	1 - Call has not completed flushing due to\r
                  a pending interrupt.\r
\r
  @return Status  0 - Call completed without error\r
\r
  @return Status  -2 - Invalid argument\r
\r
  @return Status  -3 - Call completed with error\r
   \r
**/\r
#define PAL_CACHE_FLUSH 	1\r
\r
\r
//\r
// Attributes of PAL_CACHE_CONFIG_INFO1\r
// \r
#define PAL_CACHE_ATTR_WT 	0\r
#define PAL_CACHE_ATTR_WB		1\r
\r
//\r
// PAL_CACHE_CONFIG_INFO1.StoreHint\r
// \r
#define PAL_CACHE_STORE_TEMPORAL			0\r
#define PAL_CACHE_STORE_NONE_TEMPORAL	3\r
\r
//\r
// PAL_CACHE_CONFIG_INFO1.StoreHint\r
// \r
#define PAL_CACHE_STORE_TEMPORAL_LVL_1				0\r
#define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL	3\r
\r
//\r
// PAL_CACHE_CONFIG_INFO1.StoreHint\r
// \r
#define PAL_CACHE_LOAD_TEMPORAL_LVL_1					0\r
#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1		1\r
#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL	3\r
\r
//\r
// Detail the characteristics of a given processor controlled\r
// cache in the cache hierarchy.\r
// \r
typedef struct {\r
	UINT64	IsUnified 	: 1;\r
	UINT64	Attributes	:	2;\r
	UINT64	Associativity:8;\r
	UINT64	LineSize:8;\r
	UINT64	Stride:8;\r
	UINT64	StoreLatency:8;\r
	UINT64	StoreHint:8;\r
	UINT64	LoadHint:8;\r
} PAL_CACHE_INFO_RETURN1;\r
\r
//\r
// Detail the characteristics of a given processor controlled\r
// cache in the cache hierarchy.\r
// \r
typedef struct {\r
	UINT64	CacheSize:32;\r
	UINT64	AliasBoundary:8;\r
	UINT64	TagLsBits:8;\r
	UINT64	TagMsBits:8;\r
} PAL_CACHE_INFO_RETURN2;\r
\r
/**\r
   \r
  Return detailed instruction or data cache information. It is\r
  required by IPF. The PAL procedure supports the Static\r
  Registers calling convention. It could be called at virtual\r
  mode and physical mode.\r
  \r
  @param Index 				Index of PAL_CACHE_INFO within the list of\r
											PAL procedures.\r
  \r
  @param CacheLevel		Unsigned 64-bit integer specifying the\r
                      level in the cache hierarchy for which\r
                      information is requested. This value must\r
                      be between 0 and one less than the value\r
                      returned in the cache_levels return value\r
                      from PAL_CACHE_SUMMARY.\r
  \r
  @param CacheType    Unsigned 64-bit integer with a value of 1\r
                      for instruction cache and 2 for data or\r
                      unified cache. All other values are\r
                      reserved.\r
  \r
  @param Reserved 		Should be 0.\r
  \r
  \r
  @return R9			Detail the characteristics of a given\r
                  processor controlled cache in the cache\r
                  hierarchy. See PAL_CACHE_INFO_RETURN1.\r
  \r
  @return R10			Detail the characteristics of a given\r
                  processor controlled cache in the cache\r
                  hierarchy. See PAL_CACHE_INFO_RETURN2.\r
  \r
  @return R11			Reserved with 0.\r
  \r
  \r
  @return Status  0 - Call completed without error\r
\r
  @return Status  -2 - Invalid argument\r
\r
  @return Status  -3 - Call completed with error\r
   \r
**/\r
#define PAL_CACHE_INFO 		2\r
\r
\r
\r
//\r
// Level of PAL_CACHE_INIT.\r
// \r
#define PAL_CACHE_INIT_ALL	0xffffffffffffffffULL\r
\r
//\r
// Restrict of PAL_CACHE_INIT.\r
// \r
#define PAL_CACHE_INIT_NO_RESTRICT	0\r
#define PAL_CACHE_INIT_RESTRICTED		1\r
\r
/**\r
   \r
  Initialize the instruction or data caches. It is required by\r
  IPF. The PAL procedure supports the Static Registers calling\r
  convention. It could be called at physical mode.\r
\r
  @param Index 	Index of PAL_CACHE_INIT within the list of PAL\r
                procedures.\r
  \r
  @param Level 	Unsigned 64-bit integer containing the level of\r
                cache to initialize. If the cache level can be\r
                initialized independently, only that level will\r
                be initialized. Otherwise\r
                implementation-dependent side-effects will\r
                occur.\r
  \r
  @param CacheType 	Unsigned 64-bit integer with a value of 1 to\r
                    initialize the instruction cache, 2 to\r
                    initialize the data cache, or 3 to\r
                    initialize both. All other values are\r
                    reserved.\r
\r
  @param Restrict 	Unsigned 64-bit integer with a value of 0 or\r
                    1. All other values are reserved. If\r
                    restrict is 1 and initializing the specified\r
                    level and cache_type of the cache would\r
                    cause side-effects, PAL_CACHE_INIT will\r
                    return -4 instead of initializing the cache.\r
 \r
  \r
  @return Status  0 - Call completed without error\r
\r
  @return Status  -2 - Invalid argument\r
\r
  @return Status  -3 - Call completed with error.\r
  \r
  @return Status  -4 - Call could not initialize the specified\r
                  level and cache_type of the cache without\r
									side-effects and restrict was 1.  \r
   \r
**/\r
#define PAL_CACHE_INIT 		3 \r
\r
\r
//\r
// PAL_CACHE_PROTECTION.Method.\r
// \r
#define PAL_CACHE_PROTECTION_NONE_PROTECT		0\r
#define PAL_CACHE_PROTECTION_ODD_PROTECT		1\r
#define PAL_CACHE_PROTECTION_EVEN_PROTECT		2\r
#define PAL_CACHE_PROTECTION_ECC_PROTECT		3\r
\r
\r
\r
//\r
// PAL_CACHE_PROTECTION.TagOrData.\r
// \r
#define PAL_CACHE_PROTECTION_PROTECT_DATA		0\r
#define PAL_CACHE_PROTECTION_PROTECT_TAG		1\r
#define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA		2\r
#define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG		3\r
\r
//\r
// 32-bit protection information structures.\r
// \r
typedef struct {\r
	UINT32 	DataBits:8;\r
	UINT32 	TagProtLsb:6;\r
	UINT32	TagProtMsb:6;\r
	UINT32	ProtBits:6;\r
	UINT32	Method:4;\r
	UINT32	TagOrData:2;\r
} PAL_CACHE_PROTECTION;\r
\r
/**\r
   \r
  Return instruction or data cache protection information. It is\r
  required by IPF. The PAL procedure supports the Static\r
  Registers calling convention. It could be called at physical\r
  mode and Virtual mode.\r
\r
  @param Index 	Index of PAL_CACHE_PROT_INFO within the list of\r
                PAL procedures.\r
\r
  @param CacheLevel	Unsigned 64-bit integer specifying the level\r
                    in the cache hierarchy for which information\r
                    is requested. This value must be between 0\r
                    and one less than the value returned in the\r
                    cache_levels return value from\r
                    PAL_CACHE_SUMMARY.\r
\r
  @param CacheType	Unsigned 64-bit integer with a value of 1\r
                    for instruction cache and 2 for data or\r
                    unified cache. All other values are\r
                    reserved.\r
  \r
  @return R9			Detail the characteristics of a given\r
                  processor controlled cache in the cache\r
                  hierarchy. See PAL_CACHE_PROTECTION[0..1].\r
  \r
  @return R10			Detail the characteristics of a given\r
                  processor controlled cache in the cache\r
                  hierarchy. See PAL_CACHE_PROTECTION[2..3].\r
  \r
  @return R11			Detail the characteristics of a given\r
                  processor controlled cache in the cache\r
                  hierarchy. See PAL_CACHE_PROTECTION[4..5].\r
  \r
  \r
  @return Status  0 - Call completed without error\r
\r
  @return Status  -2 - Invalid argument\r
\r
  @return Status  -3 - Call completed with error.\r
   \r
**/\r
#define PAL_CACHE_PROT_INFO 		38\r
\r
\r
\r
\r
\r
\r
\r
///\r
// ?????????\r
\r
\r
\r
/**\r
   \r
  Returns information on which logical processors share caches.\r
  It is optional.\r
\r
  @param CallingConvention  Static Registers\r
\r
  @param Mode               Physical/Virtual\r
   \r
**/\r
#define PAL_CACHE_SHARED_INFO 	43\r
\r
\r
/**\r
   \r
  Return a summary of the cache hierarchy. It is required by\r
  IPF.\r
\r
  @param CallingConvention  Static Registers\r
\r
  @param Mode               Physical/Virtual\r
   \r
**/\r
#define PAL_CACHE_SUMMARY		4\r
\r
/**\r
   \r
  Return a list of supported memory attributes.. It is required\r
  by IPF.\r
\r
  @param CallingConvention  Static Registers\r
\r
  @param Mode               Physical/Virtual\r
   \r
**/\r
#define PAL_MEM_ATTRIB 			5\r
\r
/**\r
   \r
  Used in architected sequence to transition pages from a\r
  cacheable, speculative attribute to an uncacheable attribute.\r
  It is required by IPF.\r
\r
  @param CallingConvention  Static Registers\r
\r
  @param Mode               Physical/Virtual\r
   \r
**/\r
#define PAL_PREFETCH_VISIBILITY 	41\r
\r
/**\r
   \r
  Return information needed for ptc.e instruction to purge\r
  entire TC. It is required by IPF.\r
\r
  @param CallingConvention  Static Registers\r
\r
  @param Mode               Physical/Virtual\r
   \r
**/\r
#define PAL_PTCE_INFO 		6\r
\r
/**\r
   \r
  Return detailed information about virtual memory features\r
  supported in the processor. It is required by IPF.\r
\r
  @param CallingConvention  Static Registers\r
\r
  @param Mode               Physical/Virtual\r
   \r
**/\r
#define PAL_VM_INFO 			7\r
\r
\r
/**\r
   \r
  Return virtual memory TC and hardware walker page sizes\r
  supported in the processor. It is required by IPF.\r
\r
  @param CallingConvention  Static Registers\r
\r
  @param Mode               Physical\r
   \r
**/\r
#define PAL_VM_PAGE_SIZE 34\r
\r
/**\r
   \r
  Return summary information about virtual memory features\r
  supported in the processor. It is required by IPF.\r
\r
  @param CallingConvention  Static Registers\r
\r
  @param Mode               Physical/Virtual\r
   \r
**/\r
#define PAL_VM_SUMMARY 	8\r
\r
/**\r
   \r
  Read contents of a translation register. It is required by\r
  IPF.\r
\r
  @param CallingConvention  Stacked Register\r
\r
  @param Mode               Physical\r
   \r
**/\r
#define PAL_VM_TR_READ 	261 \r
\r
/**\r
   \r
  Return configurable processor bus interface features and their\r
  current settings. It is required by IPF.\r
\r
  @param CallingConvention  Static Registers\r
\r
  @param Mode               Physical\r
   \r
**/\r
#define PAL_BUS_GET_FEATURES 9\r
\r
\r
/**\r
   \r
  Enable or disable configurable features in processor bus\r
  interface. It is required by IPF.\r
\r
  @param CallingConvention  Static Registers\r
\r
  @param Mode               Physical\r
   \r
**/\r
#define PAL_BUS_SET_FEATURES 10\r
\r
\r
/**\r
   \r
  Return the number of instruction and data breakpoint\r
  registers. It is required by IPF.\r
\r
  @param CallingConvention  Static Registers\r
\r
  @param Mode               Physical/Virtual\r
   \r
**/\r
#define PAL_DEBUG_INFO 	11\r
\r
/**\r
   \r
Commit	Line	Data
540dfc26	1	/** @file\r
	2	Main PAL API's defined in IPF PAL Spec.\r
	3	\r
	4	Copyright (c) 2006 - 2007, Intel Corporation\r
	5	All rights reserved. This program and the accompanying materials\r
	6	are licensed and made available under the terms and conditions of the BSD License\r
	7	which accompanies this distribution. The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php\r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	\r
540dfc26	13	**/\r
	14	\r
	15	#ifndef __PAL_API_H__\r
	16	#define __PAL_API_H__\r
	17	\r
540dfc26	18	\r
	19	//\r
	20	// CacheType of PAL_CACHE_FLUSH.\r
	21	//\r
	22	#define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1\r
	23	#define PAL_CACHE_FLUSH_DATA_ALL 2\r
	24	#define PAL_CACHE_FLUSH_ALL 3\r
	25	#define PAL_CACHE_FLUSH_SYNC_TO_DATA 4\r
	26	\r
	27	\r
	28	//\r
	29	// Bitmask of Opearation of PAL_CACHE_FLUSH.\r
	30	// \r
	31	#define PAL_CACHE_FLUSH_INVIDED_LINES BIT0\r
	32	#define PAL_CACHE_FLUSH_PROBE_INTERRUPT BIT1\r
	33	\r
	34	/**\r
	35	\r
	36	Flush the instruction or data caches. It is required by IPF.\r
	37	The PAL procedure supports the Static Registers calling\r
	38	convention. It could be called at virtual mode and physical\r
	39	mode.\r
	40	\r
	41	@param Index Index of PAL_CACHE_FLUSH within the\r
	42	list of PAL procedures.\r
	43	\r
	44	@param CacheType Unsigned 64-bit integer indicating\r
	45	which cache to flush.\r
	46	\r
	47	@param Operation Formatted bit vector indicating the\r
	48	operation of this call.\r
	49	\r
	50	@param ProgressIndicator Unsigned 64-bit integer specifying\r
	51	the starting position of the flush\r
	52	operation.\r
	53	\r
	54	@return R9 Unsigned 64-bit integer specifying the vector\r
	55	number of the pending interrupt.\r
	56	\r
	57	@return R10 Unsigned 64-bit integer specifying the\r
	58	starting position of the flush operation.\r
	59	\r
	60	@return R11 Unsigned 64-bit integer specifying the vector\r
	61	number of the pending interrupt.\r
	62	\r
	63	@return Status 2 - Call completed without error, but a PMI\r
	64	was taken during the execution of this\r
	65	procedure.\r
	66	\r
	67	@return Status 1 - Call has not completed flushing due to\r
	68	a pending interrupt.\r
	69	\r
	70	@return Status 0 - Call completed without error\r
	71	\r
	72	@return Status -2 - Invalid argument\r
	73	\r
	74	@return Status -3 - Call completed with error\r
	75	\r
	76	**/\r
	77	#define PAL_CACHE_FLUSH 1\r
	78	\r
	79	\r
	80	//\r
	81	// Attributes of PAL_CACHE_CONFIG_INFO1\r
82	// \r
83	#define PAL_CACHE_ATTR_WT 0\r
84	#define PAL_CACHE_ATTR_WB 1\r
85	\r
86	//\r
87	// PAL_CACHE_CONFIG_INFO1.StoreHint\r
88	// \r
89	#define PAL_CACHE_STORE_TEMPORAL 0\r
90	#define PAL_CACHE_STORE_NONE_TEMPORAL 3\r
91	\r
92	//\r
93	// PAL_CACHE_CONFIG_INFO1.StoreHint\r
94	// \r
95	#define PAL_CACHE_STORE_TEMPORAL_LVL_1 0\r
96	#define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3\r
97	\r
98	//\r
99	// PAL_CACHE_CONFIG_INFO1.StoreHint\r
100	// \r
101	#define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0\r
102	#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1\r
103	#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3\r
104	\r
105	//\r
106	// Detail the characteristics of a given processor controlled\r
107	// cache in the cache hierarchy.\r
108	// \r
109	typedef struct {\r
110	UINT64 IsUnified : 1;\r
111	UINT64 Attributes : 2;\r
112	UINT64 Associativity:8;\r
113	UINT64 LineSize:8;\r
114	UINT64 Stride:8;\r
115	UINT64 StoreLatency:8;\r
116	UINT64 StoreHint:8;\r
117	UINT64 LoadHint:8;\r
118	} PAL_CACHE_INFO_RETURN1;\r
119	\r
120	//\r
121	// Detail the characteristics of a given processor controlled\r
122	// cache in the cache hierarchy.\r
123	// \r
124	typedef struct {\r
125	UINT64 CacheSize:32;\r
126	UINT64 AliasBoundary:8;\r
127	UINT64 TagLsBits:8;\r
128	UINT64 TagMsBits:8;\r
129	} PAL_CACHE_INFO_RETURN2;\r
130	\r
131	/**\r
132	\r
133	Return detailed instruction or data cache information. It is\r
134	required by IPF. The PAL procedure supports the Static\r
135	Registers calling convention. It could be called at virtual\r
136	mode and physical mode.\r
137	\r
138	@param Index Index of PAL_CACHE_INFO within the list of\r
139	PAL procedures.\r
140	\r
141	@param CacheLevel Unsigned 64-bit integer specifying the\r
142	level in the cache hierarchy for which\r
143	information is requested. This value must\r
144	be between 0 and one less than the value\r
145	returned in the cache_levels return value\r
146	from PAL_CACHE_SUMMARY.\r
147	\r
148	@param CacheType Unsigned 64-bit integer with a value of 1\r
149	for instruction cache and 2 for data or\r
150	unified cache. All other values are\r
151	reserved.\r
152	\r
153	@param Reserved Should be 0.\r
154	\r
155	\r
156	@return R9 Detail the characteristics of a given\r
157	processor controlled cache in the cache\r
158	hierarchy. See PAL_CACHE_INFO_RETURN1.\r
159	\r
160	@return R10 Detail the characteristics of a given\r
161	processor controlled cache in the cache\r
162	hierarchy. See PAL_CACHE_INFO_RETURN2.\r
163	\r
164	@return R11 Reserved with 0.\r
165	\r
166	\r
167	@return Status 0 - Call completed without error\r
168	\r
169	@return Status -2 - Invalid argument\r
170	\r
171	@return Status -3 - Call completed with error\r
172	\r
173	**/\r
174	#define PAL_CACHE_INFO 2\r
175	\r
176	\r
177	\r
178	//\r
179	// Level of PAL_CACHE_INIT.\r
180	// \r
181	#define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL\r
182	\r
183	//\r
184	// Restrict of PAL_CACHE_INIT.\r
185	// \r
186	#define PAL_CACHE_INIT_NO_RESTRICT 0\r
187	#define PAL_CACHE_INIT_RESTRICTED 1\r
188	\r
189	/**\r
190	\r
191	Initialize the instruction or data caches. It is required by\r
192	IPF. The PAL procedure supports the Static Registers calling\r
193	convention. It could be called at physical mode.\r
194	\r
195	@param Index Index of PAL_CACHE_INIT within the list of PAL\r
196	procedures.\r
197	\r
198	@param Level Unsigned 64-bit integer containing the level of\r
199	cache to initialize. If the cache level can be\r
200	initialized independently, only that level will\r
201	be initialized. Otherwise\r
202	implementation-dependent side-effects will\r
203	occur.\r
204	\r
205	@param CacheType Unsigned 64-bit integer with a value of 1 to\r
206	initialize the instruction cache, 2 to\r
207	initialize the data cache, or 3 to\r
208	initialize both. All other values are\r
209	reserved.\r
210	\r
211	@param Restrict Unsigned 64-bit integer with a value of 0 or\r
212	1. All other values are reserved. If\r
213	restrict is 1 and initializing the specified\r
214	level and cache_type of the cache would\r
215	cause side-effects, PAL_CACHE_INIT will\r
216	return -4 instead of initializing the cache.\r
217	\r
218	\r
219	@return Status 0 - Call completed without error\r
220	\r
221	@return Status -2 - Invalid argument\r
222	\r
223	@return Status -3 - Call completed with error.\r
224	\r
225	@return Status -4 - Call could not initialize the specified\r
226	level and cache_type of the cache without\r
227	side-effects and restrict was 1. \r
228	\r
229	**/\r
230	#define PAL_CACHE_INIT 3 \r
231	\r
232	\r
233	//\r
234	// PAL_CACHE_PROTECTION.Method.\r
235	// \r
236	#define PAL_CACHE_PROTECTION_NONE_PROTECT 0\r
237	#define PAL_CACHE_PROTECTION_ODD_PROTECT 1\r
238	#define PAL_CACHE_PROTECTION_EVEN_PROTECT 2\r
239	#define PAL_CACHE_PROTECTION_ECC_PROTECT 3\r
240	\r
241	\r
242	\r
243	//\r
244	// PAL_CACHE_PROTECTION.TagOrData.\r
245	// \r
246	#define PAL_CACHE_PROTECTION_PROTECT_DATA 0\r
247	#define PAL_CACHE_PROTECTION_PROTECT_TAG 1\r
248	#define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2\r
249	#define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3\r
250	\r
251	//\r
252	// 32-bit protection information structures.\r
253	// \r
254	typedef struct {\r
255	UINT32 DataBits:8;\r
256	UINT32 TagProtLsb:6;\r
257	UINT32 TagProtMsb:6;\r
258	UINT32 ProtBits:6;\r
259	UINT32 Method:4;\r
260	UINT32 TagOrData:2;\r
261	} PAL_CACHE_PROTECTION;\r
262	\r
263	/**\r
264	\r
265	Return instruction or data cache protection information. It is\r
266	required by IPF. The PAL procedure supports the Static\r
267	Registers calling convention. It could be called at physical\r
268	mode and Virtual mode.\r
269	\r
270	@param Index Index of PAL_CACHE_PROT_INFO within the list of\r
271	PAL procedures.\r
272	\r
273	@param CacheLevel Unsigned 64-bit integer specifying the level\r
274	in the cache hierarchy for which information\r
275	is requested. This value must be between 0\r
276	and one less than the value returned in the\r
277	cache_levels return value from\r
278	PAL_CACHE_SUMMARY.\r
279	\r
280	@param CacheType Unsigned 64-bit integer with a value of 1\r
281	for instruction cache and 2 for data or\r
282	unified cache. All other values are\r
283	reserved.\r
284	\r
285	@return R9 Detail the characteristics of a given\r
286	processor controlled cache in the cache\r
287	hierarchy. See PAL_CACHE_PROTECTION[0..1].\r
288	\r
289	@return R10 Detail the characteristics of a given\r
290	processor controlled cache in the cache\r
291	hierarchy. See PAL_CACHE_PROTECTION[2..3].\r
292	\r
293	@return R11 Detail the characteristics of a given\r
294	processor controlled cache in the cache\r
295	hierarchy. See PAL_CACHE_PROTECTION[4..5].\r
296	\r
297	\r
298	@return Status 0 - Call completed without error\r
299	\r
300	@return Status -2 - Invalid argument\r
301	\r
302	@return Status -3 - Call completed with error.\r
303	\r
304	**/\r
305	#define PAL_CACHE_PROT_INFO 38\r
306	\r
307	\r
308	\r
309	\r
310	\r
311	\r
312	\r
313	///\r
314	// ?????????\r
315	\r
316	\r
317	\r
318	/**\r
319	\r
320	Returns information on which logical processors share caches.\r
321	It is optional.\r
322	\r
323	@param CallingConvention Static Registers\r
324	\r
325	@param Mode Physical/Virtual\r
326	\r
327	**/\r
328	#define PAL_CACHE_SHARED_INFO 43\r
329	\r
330	\r
331	/**\r
332	\r
333	Return a summary of the cache hierarchy. It is required by\r
334	IPF.\r
335	\r
336	@param CallingConvention Static Registers\r
337	\r
338	@param Mode Physical/Virtual\r
339	\r
340	**/\r
341	#define PAL_CACHE_SUMMARY 4\r
342	\r
343	/**\r
344	\r
345	Return a list of supported memory attributes.. It is required\r
346	by IPF.\r
347	\r
348	@param CallingConvention Static Registers\r
349	\r
350	@param Mode Physical/Virtual\r
351	\r
352	**/\r
353	#define PAL_MEM_ATTRIB 5\r
354	\r
355	/**\r
356	\r
357	Used in architected sequence to transition pages from a\r
358	cacheable, speculative attribute to an uncacheable attribute.\r
359	It is required by IPF.\r
360	\r
361	@param CallingConvention Static Registers\r
362	\r
363	@param Mode Physical/Virtual\r
364	\r
365	**/\r
366	#define PAL_PREFETCH_VISIBILITY 41\r
367	\r
368	/**\r
369	\r
370	Return information needed for ptc.e instruction to purge\r
371	entire TC. It is required by IPF.\r
372	\r
373	@param CallingConvention Static Registers\r
374	\r
375	@param Mode Physical/Virtual\r
376	\r
377	**/\r
378	#define PAL_PTCE_INFO 6\r
379	\r
380	/**\r
381	\r
382	Return detailed information about virtual memory features\r
383	supported in the processor. It is required by IPF.\r
384	\r
385	@param CallingConvention Static Registers\r
386	\r
387	@param Mode Physical/Virtual\r
388	\r
389	**/\r
390	#define PAL_VM_INFO 7\r
391	\r
392	\r
393	/**\r
394	\r
395	Return virtual memory TC and hardware walker page sizes\r
396	supported in the processor. It is required by IPF.\r
397	\r
398	@param CallingConvention Static Registers\r
399	\r
400	@param Mode Physical\r
401	\r
402	**/\r
403	#define PAL_VM_PAGE_SIZE 34\r
404	\r
405	/**\r
406	\r
407	Return summary information about virtual memory features\r
408	supported in the processor. It is required by IPF.\r
409	\r
410	@param CallingConvention Static Registers\r
411	\r
412	@param Mode Physical/Virtual\r
413	\r
414	**/\r
415	#define PAL_VM_SUMMARY 8\r
416	\r
417	/**\r
418	\r
419	Read contents of a translation register. It is required by\r
420	IPF.\r
421	\r
422	@param CallingConvention Stacked Register\r
423	\r
424	@param Mode Physical\r
425	\r
426	**/\r
427	#define PAL_VM_TR_READ 261 \r
428	\r
429	/**\r
430	\r
431	Return configurable processor bus interface features and their\r
432	current settings. It is required by IPF.\r
433	\r
434	@param CallingConvention Static Registers\r
435	\r
436	@param Mode Physical\r
437	\r
438	**/\r
439	#define PAL_BUS_GET_FEATURES 9\r
440	\r
441	\r
442	/**\r
443	\r
444	Enable or disable configurable features in processor bus\r
445	interface. It is required by IPF.\r
446	\r
447	@param CallingConvention Static Registers\r
448	\r
449	@param Mode Physical\r
450	\r
451	**/\r
452	#define PAL_BUS_SET_FEATURES 10\r
453	\r
454	\r
455	/**\r
456	\r
457	Return the number of instruction and data breakpoint\r
458	registers. It is required by IPF.\r
459	\r
460	@param CallingConvention Static Registers\r
461	\r
462	@param Mode Physical/Virtual\r
463	\r
464	**/\r
465	#define PAL_DEBUG_INFO 11\r
466	\r
467	/**\r
468	\r
469