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a7b64584 | 1 | /** @file\r |
5d51e463 | 2 | Main PAL API's defined in Intel Itanium Architecture Software Developer's Manual.\r |
a7b64584 | 3 | \r |
9095d37b | 4 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r |
9344f092 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
a7b64584 | 6 | \r |
7 | **/\r | |
8 | \r | |
9 | #ifndef __PAL_API_H__\r | |
10 | #define __PAL_API_H__\r | |
11 | \r | |
12 | #define PAL_SUCCESS 0x0\r | |
13 | \r | |
7e6a7a63 | 14 | ///\r |
15 | /// CacheType of PAL_CACHE_FLUSH.\r | |
16 | ///\r | |
a7b64584 | 17 | #define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1\r |
18 | #define PAL_CACHE_FLUSH_DATA_ALL 2\r | |
19 | #define PAL_CACHE_FLUSH_ALL 3\r | |
20 | #define PAL_CACHE_FLUSH_SYNC_TO_DATA 4\r | |
21 | \r | |
22 | \r | |
7e6a7a63 | 23 | ///\r |
24 | /// Bitmask of Opearation of PAL_CACHE_FLUSH.\r | |
25 | ///\r | |
a7b64584 | 26 | #define PAL_CACHE_FLUSH_INVALIDATE_LINES BIT0\r |
27 | #define PAL_CACHE_FLUSH_NO_INVALIDATE_LINES 0\r | |
28 | #define PAL_CACHE_FLUSH_POLL_INTERRUPT BIT1\r | |
29 | #define PAL_CACHE_FLUSH_NO_INTERRUPT 0\r | |
30 | \r | |
31 | /**\r | |
32 | PAL Procedure - PAL_CACHE_FLUSH.\r | |
33 | \r | |
1a2f870c | 34 | Flush the instruction or data caches. It is required by Itanium processors.\r |
a7b64584 | 35 | The PAL procedure supports the Static Registers calling\r |
36 | convention. It could be called at virtual mode and physical\r | |
37 | mode.\r | |
38 | \r | |
39 | @param Index Index of PAL_CACHE_FLUSH within the\r | |
40 | list of PAL procedures.\r | |
41 | @param CacheType Unsigned 64-bit integer indicating\r | |
42 | which cache to flush.\r | |
43 | @param Operation Formatted bit vector indicating the\r | |
44 | operation of this call.\r | |
45 | @param ProgressIndicator Unsigned 64-bit integer specifying\r | |
46 | the starting position of the flush\r | |
47 | operation.\r | |
48 | \r | |
49 | @retval 2 Call completed without error, but a PMI\r | |
50 | was taken during the execution of this\r | |
51 | procedure.\r | |
52 | @retval 1 Call has not completed flushing due to\r | |
53 | a pending interrupt.\r | |
54 | @retval 0 Call completed without error\r | |
55 | @retval -2 Invalid argument\r | |
56 | @retval -3 Call completed with error\r | |
57 | \r | |
58 | @return R9 Unsigned 64-bit integer specifying the vector\r | |
59 | number of the pending interrupt.\r | |
60 | @return R10 Unsigned 64-bit integer specifying the\r | |
61 | starting position of the flush operation.\r | |
62 | @return R11 Unsigned 64-bit integer specifying the vector\r | |
63 | number of the pending interrupt.\r | |
64 | \r | |
65 | **/\r | |
66 | #define PAL_CACHE_FLUSH 1\r | |
67 | \r | |
68 | \r | |
7e6a7a63 | 69 | ///\r |
70 | /// Attributes of PAL_CACHE_CONFIG_INFO1\r | |
71 | ///\r | |
a7b64584 | 72 | #define PAL_CACHE_ATTR_WT 0\r |
73 | #define PAL_CACHE_ATTR_WB 1\r | |
74 | \r | |
7e6a7a63 | 75 | ///\r |
76 | /// PAL_CACHE_CONFIG_INFO1.StoreHint\r | |
77 | ///\r | |
a7b64584 | 78 | #define PAL_CACHE_STORE_TEMPORAL 0\r |
79 | #define PAL_CACHE_STORE_NONE_TEMPORAL 3\r | |
80 | \r | |
7e6a7a63 | 81 | ///\r |
82 | /// PAL_CACHE_CONFIG_INFO1.StoreHint\r | |
83 | ///\r | |
a7b64584 | 84 | #define PAL_CACHE_STORE_TEMPORAL_LVL_1 0\r |
85 | #define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3\r | |
86 | \r | |
7e6a7a63 | 87 | ///\r |
88 | /// PAL_CACHE_CONFIG_INFO1.StoreHint\r | |
89 | ///\r | |
a7b64584 | 90 | #define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0\r |
91 | #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1\r | |
92 | #define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3\r | |
93 | \r | |
7e6a7a63 | 94 | ///\r |
95 | /// Detail the characteristics of a given processor controlled\r | |
96 | /// cache in the cache hierarchy.\r | |
97 | ///\r | |
a7b64584 | 98 | typedef struct {\r |
99 | UINT64 IsUnified : 1;\r | |
100 | UINT64 Attributes : 2;\r | |
101 | UINT64 Associativity:8;\r | |
102 | UINT64 LineSize:8;\r | |
103 | UINT64 Stride:8;\r | |
104 | UINT64 StoreLatency:8;\r | |
105 | UINT64 StoreHint:8;\r | |
106 | UINT64 LoadHint:8;\r | |
107 | } PAL_CACHE_INFO_RETURN1;\r | |
108 | \r | |
7e6a7a63 | 109 | ///\r |
110 | /// Detail the characteristics of a given processor controlled\r | |
111 | /// cache in the cache hierarchy.\r | |
112 | ///\r | |
a7b64584 | 113 | typedef struct {\r |
114 | UINT64 CacheSize:32;\r | |
115 | UINT64 AliasBoundary:8;\r | |
116 | UINT64 TagLsBits:8;\r | |
117 | UINT64 TagMsBits:8;\r | |
118 | } PAL_CACHE_INFO_RETURN2;\r | |
119 | \r | |
120 | /**\r | |
121 | PAL Procedure - PAL_CACHE_INFO.\r | |
122 | \r | |
123 | Return detailed instruction or data cache information. It is\r | |
1a2f870c | 124 | required by Itanium processors. The PAL procedure supports the Static\r |
a7b64584 | 125 | Registers calling convention. It could be called at virtual\r |
126 | mode and physical mode.\r | |
127 | \r | |
128 | @param Index Index of PAL_CACHE_INFO within the list of\r | |
129 | PAL procedures.\r | |
130 | @param CacheLevel Unsigned 64-bit integer specifying the\r | |
131 | level in the cache hierarchy for which\r | |
132 | information is requested. This value must\r | |
133 | be between 0 and one less than the value\r | |
134 | returned in the cache_levels return value\r | |
135 | from PAL_CACHE_SUMMARY.\r | |
136 | @param CacheType Unsigned 64-bit integer with a value of 1\r | |
137 | for instruction cache and 2 for data or\r | |
138 | unified cache. All other values are\r | |
139 | reserved.\r | |
140 | @param Reserved Should be 0.\r | |
141 | \r | |
142 | @retval 0 Call completed without error\r | |
143 | @retval -2 Invalid argument\r | |
144 | @retval -3 Call completed with error\r | |
145 | \r | |
146 | @return R9 Detail the characteristics of a given\r | |
147 | processor controlled cache in the cache\r | |
148 | hierarchy. See PAL_CACHE_INFO_RETURN1.\r | |
149 | @return R10 Detail the characteristics of a given\r | |
150 | processor controlled cache in the cache\r | |
151 | hierarchy. See PAL_CACHE_INFO_RETURN2.\r | |
152 | @return R11 Reserved with 0.\r | |
153 | \r | |
154 | **/\r | |
155 | #define PAL_CACHE_INFO 2\r | |
156 | \r | |
157 | \r | |
158 | \r | |
7e6a7a63 | 159 | ///\r |
160 | /// Level of PAL_CACHE_INIT.\r | |
161 | ///\r | |
a7b64584 | 162 | #define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL\r |
163 | \r | |
7e6a7a63 | 164 | ///\r |
165 | /// CacheType\r | |
166 | ///\r | |
a7b64584 | 167 | #define PAL_CACHE_INIT_TYPE_INSTRUCTION 0x1\r |
168 | #define PAL_CACHE_INIT_TYPE_DATA 0x2\r | |
169 | #define PAL_CACHE_INIT_TYPE_INSTRUCTION_AND_DATA 0x3\r | |
170 | \r | |
7e6a7a63 | 171 | ///\r |
172 | /// Restrict of PAL_CACHE_INIT.\r | |
173 | ///\r | |
a7b64584 | 174 | #define PAL_CACHE_INIT_NO_RESTRICT 0\r |
175 | #define PAL_CACHE_INIT_RESTRICTED 1\r | |
176 | \r | |
177 | /**\r | |
178 | PAL Procedure - PAL_CACHE_INIT.\r | |
179 | \r | |
180 | Initialize the instruction or data caches. It is required by\r | |
1a2f870c | 181 | Itanium processors. The PAL procedure supports the Static Registers calling\r |
a7b64584 | 182 | convention. It could be called at physical mode.\r |
183 | \r | |
184 | @param Index Index of PAL_CACHE_INIT within the list of PAL\r | |
185 | procedures.\r | |
186 | @param Level Unsigned 64-bit integer containing the level of\r | |
187 | cache to initialize. If the cache level can be\r | |
188 | initialized independently, only that level will\r | |
189 | be initialized. Otherwise\r | |
190 | implementation-dependent side-effects will\r | |
191 | occur.\r | |
192 | @param CacheType Unsigned 64-bit integer with a value of 1 to\r | |
193 | initialize the instruction cache, 2 to\r | |
194 | initialize the data cache, or 3 to\r | |
195 | initialize both. All other values are\r | |
196 | reserved.\r | |
197 | @param Restrict Unsigned 64-bit integer with a value of 0 or\r | |
198 | 1. All other values are reserved. If\r | |
199 | restrict is 1 and initializing the specified\r | |
200 | level and cache_type of the cache would\r | |
201 | cause side-effects, PAL_CACHE_INIT will\r | |
202 | return -4 instead of initializing the cache.\r | |
203 | \r | |
204 | @retval 0 Call completed without error\r | |
205 | @retval -2 Invalid argument\r | |
206 | @retval -3 Call completed with error.\r | |
207 | @retval -4 Call could not initialize the specified\r | |
208 | level and cache_type of the cache without\r | |
209 | side-effects and restrict was 1.\r | |
210 | \r | |
211 | **/\r | |
212 | #define PAL_CACHE_INIT 3\r | |
213 | \r | |
214 | \r | |
7e6a7a63 | 215 | ///\r |
216 | /// PAL_CACHE_PROTECTION.Method.\r | |
217 | ///\r | |
a7b64584 | 218 | #define PAL_CACHE_PROTECTION_NONE_PROTECT 0\r |
219 | #define PAL_CACHE_PROTECTION_ODD_PROTECT 1\r | |
220 | #define PAL_CACHE_PROTECTION_EVEN_PROTECT 2\r | |
221 | #define PAL_CACHE_PROTECTION_ECC_PROTECT 3\r | |
222 | \r | |
223 | \r | |
224 | \r | |
7e6a7a63 | 225 | ///\r |
226 | /// PAL_CACHE_PROTECTION.TagOrData.\r | |
227 | ///\r | |
a7b64584 | 228 | #define PAL_CACHE_PROTECTION_PROTECT_DATA 0\r |
229 | #define PAL_CACHE_PROTECTION_PROTECT_TAG 1\r | |
230 | #define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2\r | |
231 | #define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3\r | |
232 | \r | |
7e6a7a63 | 233 | ///\r |
234 | /// 32-bit protection information structures.\r | |
235 | ///\r | |
a7b64584 | 236 | typedef struct {\r |
237 | UINT32 DataBits:8;\r | |
238 | UINT32 TagProtLsb:6;\r | |
239 | UINT32 TagProtMsb:6;\r | |
240 | UINT32 ProtBits:6;\r | |
241 | UINT32 Method:4;\r | |
242 | UINT32 TagOrData:2;\r | |
243 | } PAL_CACHE_PROTECTION;\r | |
244 | \r | |
245 | /**\r | |
246 | PAL Procedure - PAL_CACHE_PROT_INFO.\r | |
247 | \r | |
248 | Return instruction or data cache protection information. It is\r | |
1a2f870c | 249 | required by Itanium processors. The PAL procedure supports the Static\r |
a7b64584 | 250 | Registers calling convention. It could be called at physical\r |
251 | mode and Virtual mode.\r | |
252 | \r | |
253 | @param Index Index of PAL_CACHE_PROT_INFO within the list of\r | |
254 | PAL procedures.\r | |
255 | @param CacheLevel Unsigned 64-bit integer specifying the level\r | |
256 | in the cache hierarchy for which information\r | |
257 | is requested. This value must be between 0\r | |
258 | and one less than the value returned in the\r | |
259 | cache_levels return value from\r | |
260 | PAL_CACHE_SUMMARY.\r | |
261 | @param CacheType Unsigned 64-bit integer with a value of 1\r | |
262 | for instruction cache and 2 for data or\r | |
263 | unified cache. All other values are\r | |
264 | reserved.\r | |
265 | \r | |
266 | @retval 0 Call completed without error\r | |
267 | @retval -2 Invalid argument\r | |
268 | @retval -3 Call completed with error.\r | |
269 | \r | |
270 | @return R9 Detail the characteristics of a given\r | |
271 | processor controlled cache in the cache\r | |
272 | hierarchy. See PAL_CACHE_PROTECTION[0..1].\r | |
273 | @return R10 Detail the characteristics of a given\r | |
274 | processor controlled cache in the cache\r | |
275 | hierarchy. See PAL_CACHE_PROTECTION[2..3].\r | |
276 | @return R11 Detail the characteristics of a given\r | |
277 | processor controlled cache in the cache\r | |
278 | hierarchy. See PAL_CACHE_PROTECTION[4..5].\r | |
279 | \r | |
280 | **/\r | |
281 | #define PAL_CACHE_PROT_INFO 38\r | |
282 | \r | |
a7b64584 | 283 | typedef struct {\r |
992f22b9 LG |
284 | UINT64 ThreadId : 16; ///< The thread identifier of the logical\r |
285 | ///< processor for which information is being\r | |
286 | ///< returned. This value will be unique on a per core basis.\r | |
a7b64584 | 287 | UINT64 Reserved1: 16;\r |
992f22b9 LG |
288 | UINT64 CoreId: 16; ///< The core identifier of the logical processor\r |
289 | ///< for which information is being returned.\r | |
290 | ///< This value will be unique on a per physical\r | |
291 | ///< processor package basis.\r | |
a7b64584 | 292 | UINT64 Reserved2: 16;\r |
293 | } PAL_PCOC_N_CACHE_INFO1;\r | |
294 | \r | |
a7b64584 | 295 | \r |
a7b64584 | 296 | typedef struct {\r |
992f22b9 LG |
297 | UINT64 LogicalAddress : 16; ///< Logical address: geographical address\r |
298 | ///< of the logical processor for which\r | |
299 | ///< information is being returned. This is\r | |
300 | ///< the same value that is returned by the\r | |
301 | ///< PAL_FIXED_ADDR procedure when it is\r | |
302 | ///< called on the logical processor.\r | |
a7b64584 | 303 | UINT64 Reserved1: 16;\r |
304 | UINT64 Reserved2: 32;\r | |
305 | } PAL_PCOC_N_CACHE_INFO2;\r | |
306 | \r | |
307 | /**\r | |
308 | PAL Procedure - PAL_CACHE_SHARED_INFO.\r | |
309 | \r | |
310 | Returns information on which logical processors share caches.\r | |
311 | It is optional. The PAL procedure supports the Static\r | |
312 | Registers calling convention. It could be called at physical\r | |
313 | mode and Virtual mode.\r | |
314 | \r | |
315 | @param Index Index of PAL_CACHE_SHARED_INFO within the list\r | |
316 | of PAL procedures.\r | |
317 | @param CacheLevel Unsigned 64-bit integer specifying the\r | |
318 | level in the cache hierarchy for which\r | |
319 | information is requested. This value must\r | |
320 | be between 0 and one less than the value\r | |
321 | returned in the cache_levels return value\r | |
322 | from PAL_CACHE_SUMMARY.\r | |
323 | @param CacheType Unsigned 64-bit integer with a value of 1\r | |
324 | for instruction cache and 2 for data or\r | |
325 | unified cache. All other values are\r | |
326 | reserved.\r | |
327 | @param ProcNumber Unsigned 64-bit integer that specifies for\r | |
328 | which logical processor information is\r | |
329 | being requested. This input argument must\r | |
330 | be zero for the first call to this\r | |
331 | procedure and can be a maximum value of\r | |
332 | one less than the number of logical\r | |
333 | processors sharing this cache, which is\r | |
334 | returned by the num_shared return value.\r | |
335 | \r | |
336 | @retval 0 Call completed without error\r | |
337 | @retval -1 Unimplemented procedure\r | |
338 | @retval -2 Invalid argument\r | |
339 | @retval -3 Call completed with error.\r | |
340 | \r | |
341 | @return R9 Unsigned integer that returns the number of\r | |
342 | logical processors that share the processor\r | |
343 | cache level and type, for which information was\r | |
344 | requested.\r | |
345 | @return R10 The format of PAL_PCOC_N_CACHE_INFO1.\r | |
346 | @return R11 The format of PAL_PCOC_N_CACHE_INFO2.\r | |
347 | \r | |
348 | **/\r | |
349 | #define PAL_CACHE_SHARED_INFO 43\r | |
350 | \r | |
351 | \r | |
352 | /**\r | |
353 | PAL Procedure - PAL_CACHE_SUMMARY.\r | |
354 | \r | |
355 | Return a summary of the cache hierarchy. It is required by\r | |
1a2f870c | 356 | Itanium processors. The PAL procedure supports the Static Registers calling\r |
a7b64584 | 357 | convention. It could be called at physical mode and Virtual\r |
358 | mode.\r | |
359 | \r | |
360 | @param Index Index of PAL_CACHE_SUMMARY within the list of\r | |
361 | PAL procedures.\r | |
362 | \r | |
363 | @retval 0 Call completed without error\r | |
364 | @retval -2 Invalid argument\r | |
365 | @retval -3 Call completed with error.\r | |
366 | \r | |
367 | @return R9 CacheLevels Unsigned 64-bit integer denoting the\r | |
368 | number of levels of cache\r | |
369 | implemented by the processor.\r | |
370 | Strictly, this is the number of\r | |
371 | levels for which the cache\r | |
372 | controller is integrated into the\r | |
373 | processor (the cache SRAMs may be\r | |
374 | external to the processor).\r | |
375 | @return R10 UniqueCaches Unsigned 64-bit integer denoting the\r | |
376 | number of unique caches implemented\r | |
377 | by the processor. This has a maximum\r | |
378 | of 2*cache_levels, but may be less\r | |
379 | if any of the levels in the cache\r | |
380 | hierarchy are unified caches or do\r | |
381 | not have both instruction and data\r | |
382 | caches.\r | |
383 | \r | |
384 | **/\r | |
385 | #define PAL_CACHE_SUMMARY 4\r | |
386 | \r | |
387 | \r | |
388 | //\r | |
389 | // Virtual Memory Attributes implemented by processor.\r | |
390 | //\r | |
391 | #define PAL_MEMORY_ATTR_WB 0\r | |
392 | #define PAL_MEMORY_ATTR_WC 6\r | |
393 | #define PAL_MEMORY_ATTR_UC 4\r | |
394 | #define PAL_MEMORY_ATTR_UCE 5\r | |
395 | #define PAL_MEMORY_ATTR_NATPAGE 7\r | |
396 | \r | |
397 | /**\r | |
398 | PAL Procedure - PAL_MEM_ATTRIB.\r | |
399 | \r | |
400 | Return a list of supported memory attributes.. It is required\r | |
1a2f870c | 401 | by Itanium processors. The PAL procedure supports the Static Registers calling\r |
a7b64584 | 402 | convention. It could be called at physical mode and Virtual\r |
403 | mode.\r | |
404 | \r | |
405 | @param Index Index of PAL_MEM_ATTRIB within the list of PAL\r | |
406 | procedures.\r | |
407 | \r | |
408 | @retval 0 Call completed without error\r | |
409 | @retval -2 Invalid argument\r | |
410 | @retval -3 Call completed with error.\r | |
411 | \r | |
412 | @return R9 Attributes 8-bit vector of memory attributes\r | |
413 | implemented by processor. See Virtual\r | |
414 | Memory Attributes above.\r | |
415 | \r | |
416 | **/\r | |
417 | \r | |
418 | #define PAL_MEM_ATTRIB 5\r | |
419 | \r | |
420 | /**\r | |
421 | PAL Procedure - PAL_PREFETCH_VISIBILITY.\r | |
422 | \r | |
423 | Used in architected sequence to transition pages from a\r | |
424 | cacheable, speculative attribute to an uncacheable attribute.\r | |
1a2f870c | 425 | It is required by Itanium processors. The PAL procedure supports the Static\r |
a7b64584 | 426 | Registers calling convention. It could be called at physical\r |
427 | mode and Virtual mode.\r | |
428 | \r | |
429 | @param Index Index of PAL_PREFETCH_VISIBILITY within the list\r | |
430 | of PAL procedures.\r | |
431 | @param TransitionType Unsigned integer specifying the type\r | |
432 | of memory attribute transition that is\r | |
433 | being performed.\r | |
434 | \r | |
435 | @retval 1 Call completed without error; this\r | |
436 | call is not necessary on remote\r | |
437 | processors.\r | |
438 | @retval 0 Call completed without error\r | |
439 | @retval -2 Invalid argument\r | |
440 | @retval -3 Call completed with error.\r | |
441 | \r | |
442 | **/\r | |
443 | #define PAL_PREFETCH_VISIBILITY 41\r | |
444 | \r | |
445 | /**\r | |
446 | PAL Procedure - PAL_PTCE_INFO.\r | |
447 | \r | |
448 | Return information needed for ptc.e instruction to purge\r | |
1a2f870c | 449 | entire TC. It is required by Itanium processors. The PAL procedure supports\r |
a7b64584 | 450 | the Static Registers calling convention. It could be called at\r |
451 | physical mode and Virtual mode.\r | |
452 | \r | |
453 | @param Index Index of PAL_PTCE_INFO within the list\r | |
454 | of PAL procedures.\r | |
455 | \r | |
456 | @retval 0 Call completed without error\r | |
457 | @retval -2 Invalid argument\r | |
458 | @retval -3 Call completed with error.\r | |
459 | \r | |
460 | @return R9 Unsigned 64-bit integer denoting the beginning\r | |
461 | address to be used by the first PTCE instruction\r | |
462 | in the purge loop.\r | |
463 | @return R10 Two unsigned 32-bit integers denoting the loop\r | |
464 | counts of the outer (loop 1) and inner (loop 2)\r | |
465 | purge loops. count1 (loop 1) is contained in bits\r | |
466 | 63:32 of the parameter, and count2 (loop 2) is\r | |
467 | contained in bits 31:0 of the parameter.\r | |
468 | @return R11 Two unsigned 32-bit integers denoting the loop\r | |
469 | strides of the outer (loop 1) and inner (loop 2)\r | |
470 | purge loops. stride1 (loop 1) is contained in bits\r | |
471 | 63:32 of the parameter, and stride2 (loop 2) is\r | |
472 | contained in bits 31:0 of the parameter.\r | |
473 | \r | |
474 | **/\r | |
475 | #define PAL_PTCE_INFO 6\r | |
476 | \r | |
a7b64584 | 477 | typedef struct {\r |
992f22b9 LG |
478 | UINT64 NumberSets:8; ///< Unsigned 8-bit integer denoting the number\r |
479 | ///< of hash sets for the specified level\r | |
480 | ///< (1=fully associative)\r | |
481 | UINT64 NumberWays:8; ///< Unsigned 8-bit integer denoting the\r | |
482 | ///< associativity of the specified level\r | |
483 | ///< (1=direct).\r | |
484 | UINT64 NumberEntries:16; ///< Unsigned 16-bit integer denoting the\r | |
485 | ///< number of entries in the specified TC.\r | |
486 | UINT64 PageSizeIsOptimized:1; ///< Flag denoting whether the\r | |
487 | ///< specified level is optimized for\r | |
488 | ///< the region's preferred page size\r | |
489 | ///< (1=optimized) tc_pages indicates\r | |
490 | ///< which page sizes are usable by\r | |
491 | ///< this translation cache.\r | |
492 | UINT64 TcIsUnified:1; ///< Flag denoting whether the specified TC is\r | |
493 | ///< unified (1=unified).\r | |
494 | UINT64 EntriesReduction:1; ///< Flag denoting whether installed\r | |
495 | ///< translation registers will reduce\r | |
496 | ///< the number of entries within the\r | |
497 | ///< specified TC.\r | |
a7b64584 | 498 | } PAL_TC_INFO;\r |
499 | \r | |
500 | /**\r | |
501 | PAL Procedure - PAL_VM_INFO.\r | |
502 | \r | |
503 | Return detailed information about virtual memory features\r | |
1a2f870c | 504 | supported in the processor. It is required by Itanium processors. The PAL\r |
a7b64584 | 505 | procedure supports the Static Registers calling convention. It\r |
506 | could be called at physical mode and Virtual mode.\r | |
507 | \r | |
508 | @param Index Index of PAL_VM_INFO within the list\r | |
509 | of PAL procedures.\r | |
510 | @param TcLevel Unsigned 64-bit integer specifying the level\r | |
511 | in the TLB hierarchy for which information is\r | |
512 | required. This value must be between 0 and one\r | |
513 | less than the value returned in the\r | |
514 | vm_info_1.num_tc_levels return value from\r | |
515 | PAL_VM_SUMMARY.\r | |
516 | @param TcType Unsigned 64-bit integer with a value of 1 for\r | |
517 | instruction translation cache and 2 for data\r | |
518 | or unified translation cache. All other values\r | |
519 | are reserved.\r | |
520 | \r | |
521 | @retval 0 Call completed without error\r | |
522 | @retval -2 Invalid argument\r | |
523 | @retval -3 Call completed with error.\r | |
524 | \r | |
525 | @return R9 8-byte formatted value returning information\r | |
526 | about the specified TC. See PAL_TC_INFO above.\r | |
527 | @return R10 64-bit vector containing a bit for each page\r | |
528 | size supported in the specified TC, where bit\r | |
529 | position n indicates a page size of 2**n.\r | |
530 | \r | |
531 | **/\r | |
532 | #define PAL_VM_INFO 7\r | |
533 | \r | |
534 | \r | |
535 | /**\r | |
536 | PAL Procedure - PAL_VM_PAGE_SIZE.\r | |
537 | \r | |
538 | Return virtual memory TC and hardware walker page sizes\r | |
1a2f870c | 539 | supported in the processor. It is required by Itanium processors. The PAL\r |
a7b64584 | 540 | procedure supports the Static Registers calling convention. It\r |
541 | could be called at physical mode and Virtual mode.\r | |
542 | \r | |
543 | @param Index Index of PAL_VM_PAGE_SIZE within the list\r | |
544 | of PAL procedures.\r | |
545 | \r | |
546 | @retval 0 Call completed without error\r | |
547 | @retval -2 Invalid argument\r | |
548 | @retval -3 Call completed with error.\r | |
549 | \r | |
550 | @return R9 64-bit vector containing a bit for each\r | |
551 | architected page size that is supported for\r | |
552 | TLB insertions and region registers.\r | |
553 | @return R10 64-bit vector containing a bit for each\r | |
554 | architected page size supported for TLB purge\r | |
555 | operations.\r | |
556 | \r | |
557 | **/\r | |
558 | #define PAL_VM_PAGE_SIZE 34\r | |
559 | \r | |
a7b64584 | 560 | typedef struct {\r |
992f22b9 LG |
561 | UINT64 WalkerPresent:1; ///< 1-bit flag indicating whether a hardware\r |
562 | ///< TLB walker is implemented (1 = walker\r | |
563 | ///< present).\r | |
564 | UINT64 WidthOfPhysicalAddress: 7; ///< Unsigned 7-bit integer\r | |
565 | ///< denoting the number of bits of\r | |
566 | ///< physical address implemented.\r | |
567 | UINT64 WidthOfKey:8; ///< Unsigned 8-bit integer denoting the number\r | |
568 | ///< of bits mplemented in the PKR.key field.\r | |
569 | UINT64 MaxPkrIndex:8; ///< Unsigned 8-bit integer denoting the\r | |
570 | ///< maximum PKR index (number of PKRs-1).\r | |
571 | UINT64 HashTagId:8; ///< Unsigned 8-bit integer which uniquely\r | |
572 | ///< identifies the processor hash and tag\r | |
573 | ///< algorithm.\r | |
574 | UINT64 MaxDtrIndex:8; ///< Unsigned 8 bit integer denoting the\r | |
575 | ///< maximum data translation register index\r | |
576 | ///< (number of dtr entries - 1).\r | |
577 | UINT64 MaxItrIndex:8; ///< Unsigned 8 bit integer denoting the\r | |
578 | ///< maximum instruction translation register\r | |
579 | ///< index (number of itr entries - 1).\r | |
580 | UINT64 NumberOfUniqueTc:8; ///< Unsigned 8-bit integer denoting the\r | |
581 | ///< number of unique TCs implemented.\r | |
582 | ///< This is a maximum of\r | |
583 | ///< 2*num_tc_levels.\r | |
584 | UINT64 NumberOfTcLevels:8; ///< Unsigned 8-bit integer denoting the\r | |
585 | ///< number of TC levels.\r | |
a7b64584 | 586 | } PAL_VM_INFO1;\r |
587 | \r | |
a7b64584 | 588 | typedef struct {\r |
992f22b9 LG |
589 | UINT64 WidthOfVirtualAddress:8; ///< Unsigned 8-bit integer denoting\r |
590 | ///< is the total number of virtual\r | |
591 | ///< address bits - 1.\r | |
592 | UINT64 WidthOfRid:8; ///< Unsigned 8-bit integer denoting the number\r | |
593 | ///< of bits implemented in the RR.rid field.\r | |
594 | UINT64 MaxPurgedTlbs:16; ///< Unsigned 16 bit integer denoting the\r | |
595 | ///< maximum number of concurrent outstanding\r | |
596 | ///< TLB purges allowed by the processor. A\r | |
597 | ///< value of 0 indicates one outstanding\r | |
598 | ///< purge allowed. A value of 216-1\r | |
599 | ///< indicates no limit on outstanding\r | |
600 | ///< purges. All other values indicate the\r | |
601 | ///< actual number of concurrent outstanding\r | |
602 | ///< purges allowed.\r | |
a7b64584 | 603 | UINT64 Reserved:32;\r |
604 | } PAL_VM_INFO2;\r | |
605 | \r | |
606 | /**\r | |
607 | PAL Procedure - PAL_VM_SUMMARY.\r | |
608 | \r | |
609 | Return summary information about virtual memory features\r | |
1a2f870c | 610 | supported in the processor. It is required by Itanium processors. The PAL\r |
a7b64584 | 611 | procedure supports the Static Registers calling convention. It\r |
612 | could be called at physical mode and Virtual mode.\r | |
613 | \r | |
614 | @param Index Index of PAL_VM_SUMMARY within the list\r | |
615 | of PAL procedures.\r | |
616 | \r | |
617 | @retval 0 Call completed without error\r | |
618 | @retval -2 Invalid argument\r | |
619 | @retval -3 Call completed with error.\r | |
620 | \r | |
621 | @return R9 8-byte formatted value returning global virtual\r | |
622 | memory information. See PAL_VM_INFO1 above.\r | |
623 | @return R10 8-byte formatted value returning global virtual\r | |
624 | memory information. See PAL_VM_INFO2 above.\r | |
625 | \r | |
626 | **/\r | |
627 | #define PAL_VM_SUMMARY 8\r | |
628 | \r | |
629 | \r | |
630 | //\r | |
631 | // Bit mask of TR_valid flag.\r | |
632 | //\r | |
633 | #define PAL_TR_ACCESS_RIGHT_IS_VALID BIT0\r | |
634 | #define PAL_TR_PRIVILEGE_LEVEL_IS_VALID BIT1\r | |
635 | #define PAL_TR_DIRTY_IS_VALID BIT2\r | |
636 | #define PAL_TR_MEMORY_ATTR_IS_VALID BIT3\r | |
637 | \r | |
638 | \r | |
639 | /**\r | |
640 | PAL Procedure - PAL_VM_TR_READ.\r | |
641 | \r | |
642 | Read contents of a translation register. It is required by\r | |
1a2f870c | 643 | Itanium processors. The PAL procedure supports the Stacked Register calling\r |
a7b64584 | 644 | convention. It could be called at physical mode.\r |
645 | \r | |
646 | @param Index Index of PAL_VM_TR_READ within the list\r | |
647 | of PAL procedures.\r | |
648 | @param RegNumber Unsigned 64-bit number denoting which TR to\r | |
649 | read.\r | |
650 | @param TrType Unsigned 64-bit number denoting whether to\r | |
651 | read an ITR (0) or DTR (1). All other values\r | |
652 | are reserved.\r | |
653 | @param TrBuffer 64-bit pointer to the 32-byte memory buffer in\r | |
654 | which translation data is returned.\r | |
655 | \r | |
656 | @retval 0 Call completed without error\r | |
657 | @retval -2 Invalid argument\r | |
658 | @retval -3 Call completed with error.\r | |
659 | \r | |
660 | @return R9 Formatted bit vector denoting which fields are\r | |
661 | valid. See TR_valid above.\r | |
662 | \r | |
663 | **/\r | |
664 | #define PAL_VM_TR_READ 261\r | |
665 | \r | |
666 | \r | |
667 | \r | |
668 | \r | |
669 | //\r | |
670 | // Bit Mask of Processor Bus Fesatures .\r | |
671 | //\r | |
672 | \r | |
673 | /**\r | |
674 | \r | |
675 | When 0, bus data errors are detected and single bit errors are\r | |
676 | corrected. When 1, no error detection or correction is done.\r | |
677 | \r | |
678 | **/\r | |
679 | #define PAL_BUS_DISABLE_DATA_ERROR_SIGNALLING BIT63\r | |
680 | \r | |
681 | \r | |
682 | /**\r | |
683 | \r | |
684 | When 0, bus address errors are signalled on the bus. When 1,\r | |
685 | no bus errors are signalled on the bus. If Disable Bus Address\r | |
686 | Error Checking is 1, this bit is ignored.\r | |
687 | \r | |
688 | **/\r | |
689 | #define PAL_BUS_DISABLE_ADDRESS_ERROR_SIGNALLING BIT62\r | |
690 | \r | |
691 | \r | |
692 | \r | |
693 | \r | |
694 | /**\r | |
695 | \r | |
696 | When 0, bus errors are detected, single bit errors are\r | |
697 | corrected., and a CMCI or MCA is generated internally to the\r | |
698 | processor. When 1, no bus address errors are detected or\r | |
699 | corrected.\r | |
700 | \r | |
701 | **/\r | |
702 | #define PAL_BUS_DISABLE_ADDRESS_ERROR_CHECK BIT61\r | |
703 | \r | |
704 | \r | |
705 | /**\r | |
706 | \r | |
707 | When 0, bus protocol errors (BINIT#) are signaled by the\r | |
708 | processor on the bus. When 1, bus protocol errors (BINIT#) are\r | |
709 | not signaled on the bus. If Disable Bus Initialization Event\r | |
710 | Checking is 1, this bit is ignored.\r | |
711 | \r | |
712 | **/\r | |
713 | #define PAL_BUS_DISABLE_INITIALIZATION_EVENT_SIGNALLING BIT60\r | |
714 | \r | |
715 | \r | |
716 | /**\r | |
717 | \r | |
718 | When 0, bus protocol errors (BINIT#) are detected and sampled\r | |
719 | and an MCA is generated internally to the processor. When 1,\r | |
720 | the processor will ignore bus protocol error conditions\r | |
721 | (BINIT#).\r | |
722 | \r | |
723 | **/\r | |
724 | #define PAL_BUS_DISABLE_INITIALIZATION_EVENT_CHECK BIT59\r | |
725 | \r | |
726 | \r | |
727 | \r | |
728 | /**\r | |
729 | \r | |
730 | When 0, BERR# is signalled if a bus error is detected. When 1,\r | |
731 | bus errors are not signalled on the bus.\r | |
732 | \r | |
733 | **/\r | |
734 | #define PAL_BUS_DISABLE_ERROR_SIGNALLING BIT58\r | |
735 | \r | |
736 | \r | |
737 | \r | |
738 | \r | |
739 | /**\r | |
740 | \r | |
741 | When 0, BERR# is signalled when internal processor requestor\r | |
742 | initiated bus errors are detected. When 1, internal requester\r | |
743 | bus errors are not signalled on the bus.\r | |
744 | \r | |
745 | **/\r | |
746 | #define PAL_BUS_DISABLE__INTERNAL_ERROR_SIGNALLING BIT57\r | |
747 | \r | |
748 | \r | |
749 | /**\r | |
750 | \r | |
751 | When 0, the processor takes an MCA if BERR# is asserted. When\r | |
752 | 1, the processor ignores the BERR# signal.\r | |
753 | \r | |
754 | **/\r | |
755 | #define PAL_BUS_DISABLE_ERROR_CHECK BIT56\r | |
756 | \r | |
757 | \r | |
758 | /**\r | |
759 | \r | |
760 | When 0, the processor asserts BINIT# if it detects a parity\r | |
761 | error on the signals which identify the transactions to which\r | |
762 | this is a response. When 1, the processor ignores parity on\r | |
763 | these signals.\r | |
764 | \r | |
765 | **/\r | |
766 | #define PAL_BUS_DISABLE_RSP_ERROR_CHECK BIT55\r | |
767 | \r | |
768 | \r | |
769 | /**\r | |
770 | \r | |
771 | When 0, the in-order transaction queue is limited only by the\r | |
772 | number of hardware entries. When 1, the processor's in-order\r | |
773 | transactions queue is limited to one entry.\r | |
774 | \r | |
775 | **/\r | |
776 | #define PAL_BUS_DISABLE_TRANSACTION_QUEUE BIT54\r | |
777 | \r | |
778 | /**\r | |
779 | \r | |
780 | Enable a bus cache line replacement transaction when a cache\r | |
781 | line in the exclusive state is replaced from the highest level\r | |
782 | processor cache and is not present in the lower level processor\r | |
783 | caches. When 0, no bus cache line replacement transaction will\r | |
784 | be seen on the bus. When 1, bus cache line replacement\r | |
785 | transactions will be seen on the bus when the above condition is\r | |
786 | detected.\r | |
787 | \r | |
788 | **/\r | |
789 | #define PAL_BUS_ENABLE_EXCLUSIVE_CACHE_LINE_REPLACEMENT BIT53\r | |
790 | \r | |
791 | \r | |
792 | /**\r | |
793 | \r | |
794 | Enable a bus cache line replacement transaction when a cache\r | |
795 | line in the shared or exclusive state is replaced from the\r | |
796 | highest level processor cache and is not present in the lower\r | |
797 | level processor caches.\r | |
798 | When 0, no bus cache line replacement transaction will be seen\r | |
799 | on the bus. When 1, bus cache line replacement transactions\r | |
800 | will be seen on the bus when the above condition is detected.\r | |
801 | \r | |
802 | **/\r | |
803 | #define PAL_BUS_ENABLE_SHARED_CACHE_LINE_REPLACEMENT BIT52\r | |
804 | \r | |
805 | \r | |
806 | \r | |
807 | /**\r | |
808 | \r | |
809 | When 0, the data bus is configured at the 2x data transfer\r | |
810 | rate.When 1, the data bus is configured at the 1x data\r | |
811 | transfer rate, 30 Opt. Req. Disable Bus Lock Mask. When 0, the\r | |
812 | processor executes locked transactions atomically. When 1, the\r | |
813 | processor masks the bus lock signal and executes locked\r | |
814 | transactions as a non-atomic series of transactions.\r | |
815 | \r | |
816 | **/\r | |
817 | #define PAL_BUS_ENABLE_HALF_TRANSFER BIT30\r | |
818 | \r | |
819 | /**\r | |
820 | \r | |
821 | When 0, the processor will deassert bus request when finished\r | |
822 | with each transaction. When 1, the processor will continue to\r | |
823 | assert bus request after it has finished, if it was the last\r | |
824 | agent to own the bus and if there are no other pending\r | |
825 | requests.\r | |
826 | \r | |
827 | **/\r | |
828 | #define PAL_BUS_REQUEST_BUS_PARKING BIT29\r | |
829 | \r | |
830 | \r | |
831 | /**\r | |
832 | PAL Procedure - PAL_BUS_GET_FEATURES.\r | |
833 | \r | |
834 | Return configurable processor bus interface features and their\r | |
1a2f870c | 835 | current settings. It is required by Itanium processors. The PAL procedure\r |
a7b64584 | 836 | supports the Stacked Register calling convention. It could be\r |
837 | called at physical mode.\r | |
838 | \r | |
839 | @param Index Index of PAL_BUS_GET_FEATURES within the list\r | |
840 | of PAL procedures.\r | |
841 | \r | |
842 | @retval 0 Call completed without error\r | |
843 | @retval -2 Invalid argument\r | |
844 | @retval -3 Call completed with error.\r | |
845 | \r | |
846 | @return R9 64-bit vector of features implemented.\r | |
847 | (1=implemented, 0=not implemented)\r | |
848 | @return R10 64-bit vector of current feature settings.\r | |
849 | @return R11 64-bit vector of features controllable by\r | |
850 | software. (1=controllable, 0= not controllable)\r | |
851 | \r | |
852 | **/\r | |
853 | #define PAL_BUS_GET_FEATURES 9\r | |
854 | \r | |
855 | /**\r | |
856 | PAL Procedure - PAL_BUS_SET_FEATURES.\r | |
857 | \r | |
858 | Enable or disable configurable features in processor bus\r | |
1a2f870c | 859 | interface. It is required by Itanium processors. The PAL procedure\r |
a7b64584 | 860 | supports the Static Registers calling convention. It could be\r |
861 | called at physical mode.\r | |
862 | \r | |
863 | @param Index Index of PAL_BUS_SET_FEATURES within the list\r | |
864 | of PAL procedures.\r | |
865 | @param FeatureSelect 64-bit vector denoting desired state of\r | |
866 | each feature (1=select, 0=non-select).\r | |
867 | \r | |
868 | @retval 0 Call completed without error\r | |
869 | @retval -2 Invalid argument\r | |
870 | @retval -3 Call completed with error.\r | |
871 | \r | |
872 | **/\r | |
873 | #define PAL_BUS_SET_FEATURES 10\r | |
874 | \r | |
875 | \r | |
876 | /**\r | |
877 | PAL Procedure - PAL_DEBUG_INFO.\r | |
878 | \r | |
879 | Return the number of instruction and data breakpoint\r | |
1a2f870c | 880 | registers. It is required by Itanium processors. The\r |
a7b64584 | 881 | PAL procedure supports the Static Registers calling\r |
882 | convention. It could be called at physical mode and virtual\r | |
883 | mode.\r | |
884 | \r | |
885 | @param Index Index of PAL_DEBUG_INFO within the list of PAL\r | |
886 | procedures.\r | |
887 | \r | |
888 | @retval 0 Call completed without error\r | |
889 | @retval -2 Invalid argument\r | |
890 | @retval -3 Call completed with error.\r | |
891 | \r | |
892 | @return R9 Unsigned 64-bit integer denoting the number of\r | |
893 | pairs of instruction debug registers implemented\r | |
894 | by the processor.\r | |
895 | @return R10 Unsigned 64-bit integer denoting the number of\r | |
896 | pairs of data debug registers implemented by the\r | |
897 | processor.\r | |
898 | \r | |
899 | **/\r | |
900 | #define PAL_DEBUG_INFO 11\r | |
901 | \r | |
902 | /**\r | |
903 | PAL Procedure - PAL_FIXED_ADDR.\r | |
904 | \r | |
905 | Return the fixed component of a processor's directed address.\r | |
1a2f870c | 906 | It is required by Itanium processors. The PAL\r |
a7b64584 | 907 | procedure supports the Static Registers calling convention. It\r |
908 | could be called at physical mode and virtual mode.\r | |
909 | \r | |
910 | @param Index Index of PAL_FIXED_ADDR within the list of PAL\r | |
911 | procedures.\r | |
912 | \r | |
913 | @retval 0 Call completed without error\r | |
914 | @retval -2 Invalid argument\r | |
915 | @retval -3 Call completed with error.\r | |
916 | \r | |
917 | @return R9 Fixed geographical address of this processor.\r | |
918 | \r | |
919 | **/\r | |
920 | #define PAL_FIXED_ADDR 12\r | |
921 | \r | |
922 | /**\r | |
923 | PAL Procedure - PAL_FREQ_BASE.\r | |
924 | \r | |
925 | Return the frequency of the output clock for use by the\r | |
926 | platform, if generated by the processor. It is optinal. The\r | |
927 | PAL procedure supports the Static Registers calling\r | |
928 | convention. It could be called at physical mode and virtual\r | |
929 | mode.\r | |
930 | \r | |
931 | @param Index Index of PAL_FREQ_BASE within the list of PAL\r | |
932 | procedures.\r | |
933 | \r | |
934 | @retval 0 Call completed without error\r | |
935 | @retval -1 Unimplemented procedure\r | |
936 | @retval -2 Invalid argument\r | |
937 | @retval -3 Call completed with error.\r | |
938 | \r | |
939 | @return R9 Base frequency of the platform if generated by the\r | |
940 | processor chip.\r | |
941 | \r | |
942 | **/\r | |
943 | #define PAL_FREQ_BASE 13\r | |
944 | \r | |
945 | \r | |
946 | /**\r | |
947 | PAL Procedure - PAL_FREQ_RATIOS.\r | |
948 | \r | |
949 | Return ratio of processor, bus, and interval time counter to\r | |
950 | processor input clock or output clock for platform use, if\r | |
1a2f870c | 951 | generated by the processor. It is required by Itanium processors. The PAL\r |
a7b64584 | 952 | procedure supports the Static Registers calling convention. It\r |
953 | could be called at physical mode and virtual mode.\r | |
954 | \r | |
955 | @param Index Index of PAL_FREQ_RATIOS within the list of PAL\r | |
956 | procedures.\r | |
957 | \r | |
958 | @retval 0 Call completed without error\r | |
959 | @retval -2 Invalid argument\r | |
960 | @retval -3 Call completed with error.\r | |
961 | \r | |
962 | @return R9 Ratio of the processor frequency to the input\r | |
963 | clock of the processor, if the platform clock is\r | |
964 | generated externally or to the output clock to the\r | |
965 | platform, if the platform clock is generated by\r | |
966 | the processor.\r | |
967 | @return R10 Ratio of the bus frequency to the input clock of\r | |
968 | the processor, if the platform clock is generated\r | |
969 | externally or to the output clock to the platform,\r | |
970 | if the platform clock is generated by the\r | |
971 | processor.\r | |
972 | @return R11 Ratio of the interval timer counter rate to input\r | |
973 | clock of the processor, if the platform clock is\r | |
974 | generated externally or to the output clock to the\r | |
975 | platform, if the platform clock is generated by\r | |
976 | the processor.\r | |
977 | \r | |
978 | **/\r | |
979 | #define PAL_FREQ_RATIOS 14\r | |
980 | \r | |
a7b64584 | 981 | typedef struct {\r |
992f22b9 LG |
982 | UINT64 NumberOfLogicalProcessors:16; ///< Total number of logical\r |
983 | ///< processors on this physical\r | |
984 | ///< processor package that are\r | |
985 | ///< enabled.\r | |
986 | UINT64 ThreadsPerCore:8; ///< Number of threads per core.\r | |
a7b64584 | 987 | UINT64 Reserved1:8;\r |
e2a5ae07 | 988 | UINT64 CoresPerProcessor:8; ///< Total number of cores on this\r |
992f22b9 | 989 | ///< physical processor package.\r |
a7b64584 | 990 | UINT64 Reserved2:8;\r |
992f22b9 LG |
991 | UINT64 PhysicalProcessorPackageId:8; ///< Physical processor package\r |
992 | ///< identifier which was\r | |
993 | ///< assigned at reset by the\r | |
994 | ///< platform or bus\r | |
995 | ///< controller. This value may\r | |
996 | ///< or may not be unique\r | |
997 | ///< across the entire platform\r | |
998 | ///< since it depends on the\r | |
999 | ///< platform vendor's policy.\r | |
a7b64584 | 1000 | UINT64 Reserved3:8;\r |
1001 | } PAL_LOGICAL_PROCESSPR_OVERVIEW;\r | |
1002 | \r | |
a7b64584 | 1003 | typedef struct {\r |
992f22b9 LG |
1004 | UINT64 ThreadId:16; ///< The thread identifier of the logical\r |
1005 | ///< processor for which information is being\r | |
1006 | ///< returned. This value will be unique on a per\r | |
1007 | ///< core basis.\r | |
a7b64584 | 1008 | UINT64 Reserved1:16;\r |
992f22b9 LG |
1009 | UINT64 CoreId:16; ///< The core identifier of the logical processor\r |
1010 | ///< for which information is being returned.\r | |
1011 | ///< This value will be unique on a per physical\r | |
1012 | ///< processor package basis.\r | |
a7b64584 | 1013 | UINT64 Reserved2:16;\r |
1014 | } PAL_LOGICAL_PROCESSORN_INFO1;\r | |
1015 | \r | |
a7b64584 | 1016 | typedef struct {\r |
992f22b9 LG |
1017 | UINT64 LogicalAddress:16; ///< Geographical address of the logical\r |
1018 | ///< processor for which information is being\r | |
1019 | ///< returned. This is the same value that is\r | |
1020 | ///< returned by the PAL_FIXED_ADDR procedure\r | |
1021 | ///< when it is called on the logical processor.\r | |
a7b64584 | 1022 | UINT64 Reserved:48;\r |
1023 | } PAL_LOGICAL_PROCESSORN_INFO2;\r | |
1024 | \r | |
1025 | /**\r | |
1026 | PAL Procedure - PAL_LOGICAL_TO_PHYSICAL.\r | |
1027 | \r | |
1028 | Return information on which logical processors map to a\r | |
1029 | physical processor die. It is optinal. The PAL procedure\r | |
1030 | supports the Static Registers calling convention. It could be\r | |
1031 | called at physical mode and virtual mode.\r | |
1032 | \r | |
1033 | @param Index Index of PAL_LOGICAL_TO_PHYSICAL within the list of PAL\r | |
1034 | procedures.\r | |
1035 | @param ProcessorNumber Signed 64-bit integer that specifies\r | |
1036 | for which logical processor\r | |
1037 | information is being requested. When\r | |
1038 | this input argument is -1, information\r | |
1039 | is returned about the logical\r | |
1040 | processor on which the procedure call\r | |
1041 | is made. This input argument must be\r | |
1042 | in the range of 1 up to one less than\r | |
1043 | the number of logical processors\r | |
1044 | returned by num_log in the\r | |
1045 | log_overview return value.\r | |
1046 | \r | |
1047 | @retval 0 Call completed without error\r | |
1048 | @retval -1 Unimplemented procedure\r | |
1049 | @retval -2 Invalid argument\r | |
1050 | @retval -3 Call completed with error.\r | |
1051 | \r | |
1052 | @return R9 The format of PAL_LOGICAL_PROCESSPR_OVERVIEW.\r | |
1053 | @return R10 The format of PAL_LOGICAL_PROCESSORN_INFO1.\r | |
1054 | @return R11 The format of PAL_LOGICAL_PROCESSORN_INFO2.\r | |
1055 | \r | |
1056 | **/\r | |
1057 | #define PAL_LOGICAL_TO_PHYSICAL 42\r | |
1058 | \r | |
a7b64584 | 1059 | typedef struct {\r |
992f22b9 LG |
1060 | UINT64 NumberOfPmcPairs:8; ///< Unsigned 8-bit number defining the\r |
1061 | ///< number of generic PMC/PMD pairs.\r | |
1062 | UINT64 WidthOfCounter:8; ///< Unsigned 8-bit number in the range\r | |
1063 | ///< 0:60 defining the number of\r | |
1064 | ///< implemented counter bits.\r | |
1065 | UINT64 TypeOfCycleCounting:8; ///< Unsigned 8-bit number defining the\r | |
1066 | ///< event type for counting processor cycles.\r | |
1067 | UINT64 TypeOfRetiredInstructionBundle:8; ///< Retired Unsigned 8-bit\r | |
1068 | ///< number defining the\r | |
1069 | ///< event type for retired\r | |
1070 | ///< instruction bundles.\r | |
a7b64584 | 1071 | UINT64 Reserved:32;\r |
1072 | } PAL_PERFORMANCE_INFO;\r | |
1073 | \r | |
1074 | /**\r | |
1075 | PAL Procedure - PAL_PERF_MON_INFO.\r | |
1076 | \r | |
1077 | Return the number and type of performance monitors. It is\r | |
1a2f870c | 1078 | required by Itanium processors. The PAL procedure supports the Static\r |
a7b64584 | 1079 | Registers calling convention. It could be called at physical\r |
1080 | mode and virtual mode.\r | |
1081 | \r | |
1082 | @param Index Index of PAL_PERF_MON_INFO within the list of\r | |
1083 | PAL procedures.\r | |
1084 | @param PerformanceBuffer An address to an 8-byte aligned\r | |
1085 | 128-byte memory buffer.\r | |
1086 | \r | |
1087 | @retval 0 Call completed without error\r | |
1088 | @retval -2 Invalid argument\r | |
1089 | @retval -3 Call completed with error.\r | |
1090 | \r | |
1091 | @return R9 Information about the performance monitors\r | |
1092 | implemented. See PAL_PERFORMANCE_INFO;\r | |
1093 | \r | |
1094 | **/\r | |
1095 | #define PAL_PERF_MON_INFO 15\r | |
1096 | \r | |
1097 | #define PAL_PLATFORM_ADDR_INTERRUPT_BLOCK_TOKEN 0x0\r | |
1098 | #define PAL_PLATFORM_ADDR_IO_BLOCK_TOKEN 0x1\r | |
1099 | \r | |
1100 | /**\r | |
1101 | PAL Procedure - PAL_PLATFORM_ADDR.\r | |
1102 | \r | |
1103 | Specify processor interrupt block address and I/O port space\r | |
1a2f870c | 1104 | address. It is required by Itanium processors. The PAL procedure supports the\r |
a7b64584 | 1105 | Static Registers calling convention. It could be called at\r |
1106 | physical mode and virtual mode.\r | |
1107 | \r | |
1108 | @param Index Index of PAL_PLATFORM_ADDR within the list of\r | |
1109 | PAL procedures.\r | |
1110 | @param Type Unsigned 64-bit integer specifying the type of\r | |
1111 | block. 0 indicates that the processor interrupt\r | |
1112 | block pointer should be initialized. 1 indicates\r | |
1113 | that the processor I/O block pointer should be\r | |
1114 | initialized.\r | |
1115 | @param Address Unsigned 64-bit integer specifying the address\r | |
1116 | to which the processor I/O block or interrupt\r | |
1117 | block shall be set. The address must specify\r | |
1118 | an implemented physical address on the\r | |
1119 | processor model, bit 63 is ignored.\r | |
1120 | \r | |
1121 | @retval 0 Call completed without error\r | |
1122 | @retval -1 Unimplemented procedure.\r | |
1123 | @retval -2 Invalid argument\r | |
1124 | @retval -3 Call completed with error.\r | |
1125 | \r | |
1126 | **/\r | |
1127 | #define PAL_PLATFORM_ADDR 16\r | |
1128 | \r | |
a7b64584 | 1129 | typedef struct {\r |
1130 | UINT64 Reserved1:36;\r | |
992f22b9 LG |
1131 | UINT64 FaultInUndefinedIns:1; ///< Bit36, No Unimplemented\r |
1132 | ///< instruction address reported as\r | |
1133 | ///< fault. Denotes how the processor\r | |
1134 | ///< reports the detection of\r | |
1135 | ///< unimplemented instruction\r | |
1136 | ///< addresses. When 1, the processor\r | |
1137 | ///< reports an Unimplemented\r | |
1138 | ///< Instruction Address fault on the\r | |
1139 | ///< unimplemented address; when 0, it\r | |
1140 | ///< reports an Unimplemented\r | |
1141 | ///< Instruction Address trap on the\r | |
1142 | ///< previous instruction in program\r | |
1143 | ///< order. This feature may only be\r | |
1144 | ///< interrogated by\r | |
1145 | ///< PAL_PROC_GET_FEATURES. It may not\r | |
1146 | ///< be enabled or disabled by\r | |
1147 | ///< PAL_PROC_SET_FEATURES. The\r | |
1148 | ///< corresponding argument is ignored.\r | |
9095d37b | 1149 | \r |
992f22b9 LG |
1150 | UINT64 NoPresentPmi:1; ///< Bit37, No INIT, PMI, and LINT pins\r |
1151 | ///< present. Denotes the absence of INIT,\r | |
1152 | ///< PMI, LINT0 and LINT1 pins on the\r | |
1153 | ///< processor. When 1, the pins are absent.\r | |
1154 | ///< When 0, the pins are present. This\r | |
1155 | ///< feature may only be interrogated by\r | |
1156 | ///< PAL_PROC_GET_FEATURES. It may not be\r | |
1157 | ///< enabled or disabled by\r | |
1158 | ///< PAL_PROC_SET_FEATURES. The corresponding\r | |
1159 | ///< argument is ignored.\r | |
9095d37b | 1160 | \r |
992f22b9 LG |
1161 | UINT64 NoSimpleImpInUndefinedIns:1; ///< Bit38, No Simple\r |
1162 | ///< implementation of\r | |
1163 | ///< unimplemented instruction\r | |
1164 | ///< addresses. Denotes how an\r | |
1165 | ///< unimplemented instruction\r | |
1166 | ///< address is recorded in IIP\r | |
1167 | ///< on an Unimplemented\r | |
1168 | ///< Instruction Address trap or\r | |
1169 | ///< fault. When 1, the full\r | |
1170 | ///< unimplemented address is\r | |
1171 | ///< recorded in IIP; when 0, the\r | |
1172 | ///< address is sign extended\r | |
1173 | ///< (virtual addresses) or zero\r | |
1174 | ///< extended (physical\r | |
1175 | ///< addresses). This feature may\r | |
1176 | ///< only be interrogated by\r | |
1177 | ///< PAL_PROC_GET_FEATURES. It\r | |
1178 | ///< may not be enabled or\r | |
1179 | ///< disabled by\r | |
1180 | ///< PAL_PROC_SET_FEATURES. The\r | |
1181 | ///< corresponding argument is\r | |
1182 | ///< ignored.\r | |
1183 | \r | |
1184 | UINT64 NoVariablePState:1; ///< Bit39, No Variable P-state\r | |
1185 | ///< performance: A value of 1, indicates\r | |
1186 | ///< that a processor implements\r | |
1187 | ///< techniques to optimize performance\r | |
1188 | ///< for the given P-state power budget\r | |
1189 | ///< by dynamically varying the\r | |
1190 | ///< frequency, such that maximum\r | |
1191 | ///< performance is achieved for the\r | |
1192 | ///< power budget. A value of 0,\r | |
1193 | ///< indicates that P-states have no\r | |
1194 | ///< frequency variation or very small\r | |
1195 | ///< frequency variations for their given\r | |
1196 | ///< power budget. This feature may only\r | |
1197 | ///< be interrogated by\r | |
1198 | ///< PAL_PROC_GET_FEATURES. it may not be\r | |
1199 | ///< enabled or disabled by\r | |
1200 | ///< PAL_PROC_SET_FEATURES. The\r | |
1201 | ///< corresponding argument is ignored.\r | |
1202 | \r | |
1203 | UINT64 NoVM:1; ///< Bit40, No Virtual Machine features implemented.\r | |
1204 | ///< Denotes whether PSR.vm is implemented. This\r | |
1205 | ///< feature may only be interrogated by\r | |
1206 | ///< PAL_PROC_GET_FEATURES. It may not be enabled or\r | |
1207 | ///< disabled by PAL_PROC_SET_FEATURES. The\r | |
1208 | ///< corresponding argument is ignored.\r | |
1209 | \r | |
1210 | UINT64 NoXipXpsrXfs:1; ///< Bit41, No XIP, XPSR, and XFS\r | |
1211 | ///< implemented. Denotes whether XIP, XPSR,\r | |
1212 | ///< and XFS are implemented for machine\r | |
1213 | ///< check recovery. This feature may only be\r | |
1214 | ///< interrogated by PAL_PROC_GET_FEATURES.\r | |
1215 | ///< It may not be enabled or disabled by\r | |
1216 | ///< PAL_PROC_SET_FEATURES. The corresponding\r | |
1217 | ///< argument is ignored.\r | |
1218 | \r | |
1219 | UINT64 NoXr1ThroughXr3:1; ///< Bit42, No XR1 through XR3 implemented.\r | |
1220 | ///< Denotes whether XR1 XR3 are\r | |
1221 | ///< implemented for machine check\r | |
1222 | ///< recovery. This feature may only be\r | |
1223 | ///< interrogated by PAL_PROC_GET_FEATURES.\r | |
1224 | ///< It may not be enabled or disabled by\r | |
1225 | ///< PAL_PROC_SET_FEATURES. The\r | |
1226 | ///< corresponding argument is ignored.\r | |
1227 | \r | |
1228 | UINT64 DisableDynamicPrediction:1; ///< Bit43, Disable Dynamic\r | |
1229 | ///< Predicate Prediction. When\r | |
1230 | ///< 0, the processor may predict\r | |
1231 | ///< predicate results and\r | |
1232 | ///< execute speculatively, but\r | |
1233 | ///< may not commit results until\r | |
1234 | ///< the actual predicates are\r | |
1235 | ///< known. When 1, the processor\r | |
1236 | ///< shall not execute predicated\r | |
1237 | ///< instructions until the\r | |
1238 | ///< actual predicates are known.\r | |
1239 | \r | |
1240 | UINT64 DisableSpontaneousDeferral:1; ///< Bit44, Disable Spontaneous\r | |
1241 | ///< Deferral. When 1, the\r | |
1242 | ///< processor may optionally\r | |
1243 | ///< defer speculative loads\r | |
1244 | ///< that do not encounter any\r | |
1245 | ///< exception conditions, but\r | |
1246 | ///< that trigger other\r | |
1247 | ///< implementation-dependent\r | |
1248 | ///< conditions (e.g., cache\r | |
1249 | ///< miss). When 0, spontaneous\r | |
1250 | ///< deferral is disabled.\r | |
1251 | \r | |
1252 | UINT64 DisableDynamicDataCachePrefetch:1; ///< Bit45, Disable Dynamic\r | |
1253 | ///< Data Cache Prefetch.\r | |
1254 | ///< When 0, the processor\r | |
1255 | ///< may prefetch into the\r | |
1256 | ///< caches any data which\r | |
1257 | ///< has not been accessed\r | |
1258 | ///< by instruction\r | |
1259 | ///< execution, but which\r | |
1260 | ///< is likely to be\r | |
1261 | ///< accessed. When 1, no\r | |
1262 | ///< data may be fetched\r | |
1263 | ///< until it is needed for\r | |
1264 | ///< instruction execution\r | |
1265 | ///< or is fetched by an\r | |
1266 | ///< lfetch instruction.\r | |
1267 | \r | |
1268 | UINT64 DisableDynamicInsCachePrefetch:1; ///< Bit46, Disable\r | |
1269 | ///< DynamicInstruction Cache\r | |
1270 | ///< Prefetch. When 0, the\r | |
1271 | ///< processor may prefetch\r | |
1272 | ///< into the caches any\r | |
1273 | ///< instruction which has\r | |
1274 | ///< not been executed, but\r | |
1275 | ///< whose execution is\r | |
1276 | ///< likely. When 1,\r | |
1277 | ///< instructions may not be\r | |
1278 | ///< fetched until needed or\r | |
1279 | ///< hinted for execution.\r | |
1280 | ///< (Prefetch for a hinted\r | |
1281 | ///< branch is allowed even\r | |
1282 | ///< when dynamic instruction\r | |
1283 | ///< cache prefetch is\r | |
1284 | ///< disabled.)\r | |
1285 | \r | |
1286 | UINT64 DisableBranchPrediction:1; ///< Bit47, Disable Dynamic branch\r | |
1287 | ///< prediction. When 0, the\r | |
1288 | ///< processor may predict branch\r | |
1289 | ///< targets and speculatively\r | |
1290 | ///< execute, but may not commit\r | |
1291 | ///< results. When 1, the processor\r | |
1292 | ///< must wait until branch targets\r | |
1293 | ///< are known to execute.\r | |
a7b64584 | 1294 | UINT64 Reserved2:4;\r |
992f22b9 LG |
1295 | UINT64 DisablePState:1; ///< Bit52, Disable P-states. When 1, the PAL\r |
1296 | ///< P-state procedures (PAL_PSTATE_INFO,\r | |
1297 | ///< PAL_SET_PSTATE, PAL_GET_PSTATE) will\r | |
1298 | ///< return with a status of -1\r | |
1299 | ///< (Unimplemented procedure).\r | |
1300 | \r | |
1301 | UINT64 EnableMcaOnDataPoisoning:1; ///< Bit53, Enable MCA signaling\r | |
1302 | ///< on data-poisoning event\r | |
1303 | ///< detection. When 0, a CMCI\r | |
1304 | ///< will be signaled on error\r | |
1305 | ///< detection. When 1, an MCA\r | |
1306 | ///< will be signaled on error\r | |
1307 | ///< detection. If this feature\r | |
1308 | ///< is not supported, then the\r | |
1309 | ///< corresponding argument is\r | |
1310 | ///< ignored when calling\r | |
1311 | ///< PAL_PROC_SET_FEATURES. Note\r | |
1312 | ///< that the functionality of\r | |
1313 | ///< this bit is independent of\r | |
1314 | ///< the setting in bit 60\r | |
1315 | ///< (Enable CMCI promotion), and\r | |
1316 | ///< that the bit 60 setting does\r | |
1317 | ///< not affect CMCI signaling\r | |
1318 | ///< for data-poisoning related\r | |
1319 | ///< events. Volume 2: Processor\r | |
1320 | ///< Abstraction Layer 2:431\r | |
1321 | ///< PAL_PROC_GET_FEATURES\r | |
1322 | \r | |
1323 | UINT64 EnableVmsw:1; ///< Bit54, Enable the use of the vmsw\r | |
1324 | ///< instruction. When 0, the vmsw instruction\r | |
1325 | ///< causes a Virtualization fault when\r | |
1326 | ///< executed at the most privileged level.\r | |
1327 | ///< When 1, this bit will enable normal\r | |
1328 | ///< operation of the vmsw instruction.\r | |
1329 | \r | |
1330 | UINT64 EnableEnvNotification:1; ///< Bit55, Enable external\r | |
1331 | ///< notification when the processor\r | |
1332 | ///< detects hardware errors caused\r | |
1333 | ///< by environmental factors that\r | |
1334 | ///< could cause loss of\r | |
1335 | ///< deterministic behavior of the\r | |
1336 | ///< processor. When 1, this bit will\r | |
1337 | ///< enable external notification,\r | |
1338 | ///< when 0 external notification is\r | |
1339 | ///< not provided. The type of\r | |
1340 | ///< external notification of these\r | |
1341 | ///< errors is processor-dependent. A\r | |
1342 | ///< loss of processor deterministic\r | |
1343 | ///< behavior is considered to have\r | |
1344 | ///< occurred if these\r | |
1345 | ///< environmentally induced errors\r | |
1346 | ///< cause the processor to deviate\r | |
1347 | ///< from its normal execution and\r | |
1348 | ///< eventually causes different\r | |
1349 | ///< behavior which can be observed\r | |
1350 | ///< at the processor bus pins.\r | |
1351 | ///< Processor errors that do not\r | |
1352 | ///< have this effects (i.e.,\r | |
1353 | ///< software induced machine checks)\r | |
1354 | ///< may or may not be promoted\r | |
1355 | ///< depending on the processor\r | |
1356 | ///< implementation.\r | |
1357 | \r | |
1358 | UINT64 DisableBinitWithTimeout:1; ///< Bit56, Disable a BINIT on\r | |
1359 | ///< internal processor time-out.\r | |
1360 | ///< When 0, the processor may\r | |
1361 | ///< generate a BINIT on an\r | |
1362 | ///< internal processor time-out.\r | |
1363 | ///< When 1, the processor will not\r | |
1364 | ///< generate a BINIT on an\r | |
1365 | ///< internal processor time-out.\r | |
1366 | ///< The event is silently ignored.\r | |
1367 | \r | |
1368 | UINT64 DisableDPM:1; ///< Bit57, Disable Dynamic Power Management\r | |
1369 | ///< (DPM). When 0, the hardware may reduce\r | |
1370 | ///< power consumption by removing the clock\r | |
1371 | ///< input from idle functional units. When 1,\r | |
1372 | ///< all functional units will receive clock\r | |
1373 | ///< input, even when idle.\r | |
1374 | \r | |
1375 | UINT64 DisableCoherency:1; ///< Bit58, Disable Coherency. When 0,\r | |
1376 | ///< the processor uses normal coherency\r | |
1377 | ///< requests and responses. When 1, the\r | |
1378 | ///< processor answers all requests as if\r | |
1379 | ///< the line were not present.\r | |
1380 | \r | |
1381 | UINT64 DisableCache:1; ///< Bit59, Disable Cache. When 0, the\r | |
1382 | ///< processor performs cast outs on\r | |
1383 | ///< cacheable pages and issues and responds\r | |
1384 | ///< to coherency requests normally. When 1,\r | |
1385 | ///< the processor performs a memory access\r | |
1386 | ///< for each reference regardless of cache\r | |
1387 | ///< contents and issues no coherence\r | |
1388 | ///< requests and responds as if the line\r | |
1389 | ///< were not present. Cache contents cannot\r | |
1390 | ///< be relied upon when the cache is\r | |
1391 | ///< disabled. WARNING: Semaphore\r | |
1392 | ///< instructions may not be atomic or may\r | |
1393 | ///< cause Unsupported Data Reference faults\r | |
1394 | ///< if caches are disabled.\r | |
1395 | \r | |
1396 | UINT64 EnableCmciPromotion:1; ///< Bit60, Enable CMCI promotion When\r | |
1397 | ///< 1, Corrected Machine Check\r | |
1398 | ///< Interrupts (CMCI) are promoted to\r | |
1399 | ///< MCAs. They are also further\r | |
1400 | ///< promoted to BERR if bit 39, Enable\r | |
1401 | ///< MCA promotion, is also set and\r | |
1402 | ///< they are promoted to BINIT if bit\r | |
1403 | ///< 38, Enable MCA to BINIT promotion,\r | |
1404 | ///< is also set. This bit has no\r | |
1405 | ///< effect if MCA signalling is\r | |
1406 | ///< disabled (see\r | |
1407 | ///< PAL_BUS_GET/SET_FEATURES)\r | |
1408 | \r | |
1409 | UINT64 EnableMcaToBinitPromotion:1; ///< Bit61, Enable MCA to BINIT\r | |
1410 | ///< promotion. When 1, machine\r | |
1411 | ///< check aborts (MCAs) are\r | |
1412 | ///< promoted to the Bus\r | |
1413 | ///< Initialization signal, and\r | |
1414 | ///< the BINIT pin is assert on\r | |
1415 | ///< each occurrence of an MCA.\r | |
1416 | ///< Setting this bit has no\r | |
1417 | ///< effect if BINIT signalling\r | |
1418 | ///< is disabled. (See\r | |
1419 | ///< PAL_BUS_GET/SET_FEATURES)\r | |
1420 | \r | |
1421 | UINT64 EnableMcaPromotion:1; ///< Bit62, Enable MCA promotion. When\r | |
1422 | ///< 1, machine check aborts (MCAs) are\r | |
1423 | ///< promoted to the Bus Error signal,\r | |
1424 | ///< and the BERR pin is assert on each\r | |
1425 | ///< occurrence of an MCA. Setting this\r | |
1426 | ///< bit has no effect if BERR\r | |
1427 | ///< signalling is disabled. (See\r | |
1428 | ///< PAL_BUS_GET/SET_FEATURES)\r | |
9095d37b | 1429 | \r |
992f22b9 LG |
1430 | UINT64 EnableBerrPromotion:1; ///< Bit63. Enable BERR promotion. When\r |
1431 | ///< 1, the Bus Error (BERR) signal is\r | |
1432 | ///< promoted to the Bus Initialization\r | |
1433 | ///< (BINIT) signal, and the BINIT pin\r | |
1434 | ///< is asserted on the occurrence of\r | |
1435 | ///< each Bus Error. Setting this bit\r | |
1436 | ///< has no effect if BINIT signalling\r | |
1437 | ///< is disabled. (See\r | |
1438 | ///< PAL_BUS_GET/SET_FEATURES)\r | |
a7b64584 | 1439 | } PAL_PROCESSOR_FEATURES;\r |
1440 | \r | |
1441 | /**\r | |
1442 | PAL Procedure - PAL_PROC_GET_FEATURES.\r | |
1443 | \r | |
1444 | Return configurable processor features and their current\r | |
1a2f870c | 1445 | setting. It is required by Itanium processors. The PAL procedure supports the\r |
a7b64584 | 1446 | Static Registers calling convention. It could be called at\r |
1447 | physical mode and virtual mode.\r | |
1448 | \r | |
1449 | @param Index Index of PAL_PROC_GET_FEATURES within the list of\r | |
1450 | PAL procedures.\r | |
1451 | @param Reserved Reserved parameter.\r | |
1452 | @param FeatureSet Feature set information is being requested\r | |
1453 | for.\r | |
1454 | \r | |
1455 | @retval 1 Call completed without error; The\r | |
1456 | feature_set passed is not supported but a\r | |
1457 | feature_set of a larger value is supported.\r | |
1458 | @retval 0 Call completed without error\r | |
1459 | @retval -2 Invalid argument\r | |
1460 | @retval -3 Call completed with error.\r | |
1461 | @retval -8 feature_set passed is beyond the maximum\r | |
1462 | feature_set supported\r | |
1463 | \r | |
1464 | @return R9 64-bit vector of features implemented. See\r | |
1465 | PAL_PROCESSOR_FEATURES.\r | |
1466 | @return R10 64-bit vector of current feature settings. See\r | |
1467 | PAL_PROCESSOR_FEATURES.\r | |
1468 | @return R11 64-bit vector of features controllable by\r | |
1469 | software.\r | |
1470 | \r | |
1471 | **/\r | |
1472 | #define PAL_PROC_GET_FEATURES 17\r | |
1473 | \r | |
1474 | \r | |
1475 | /**\r | |
1476 | PAL Procedure - PAL_PROC_SET_FEATURES.\r | |
1477 | \r | |
1478 | Enable or disable configurable processor features. It is\r | |
1a2f870c | 1479 | required by Itanium processors. The PAL procedure supports the Static\r |
a7b64584 | 1480 | Registers calling convention. It could be called at physical\r |
1481 | mode.\r | |
1482 | \r | |
1483 | @param Index Index of PAL_PROC_SET_FEATURES within the list of\r | |
1484 | PAL procedures.\r | |
1485 | @param FeatureSelect 64-bit vector denoting desired state of\r | |
1486 | each feature (1=select, 0=non-select).\r | |
1487 | @param FeatureSet Feature set to apply changes to. See\r | |
1488 | PAL_PROC_GET_FEATURES for more information\r | |
1489 | on feature sets.\r | |
1490 | \r | |
1491 | @retval 1 Call completed without error; The\r | |
1492 | feature_set passed is not supported but a\r | |
1493 | feature_set of a larger value is supported\r | |
1494 | @retval 0 Call completed without error\r | |
1495 | @retval -2 Invalid argument\r | |
1496 | @retval -3 Call completed with error.\r | |
1497 | @retval -8 feature_set passed is beyond the maximum\r | |
1498 | feature_set supported\r | |
1499 | \r | |
1500 | **/\r | |
1501 | #define PAL_PROC_SET_FEATURES 18\r | |
1502 | \r | |
1503 | \r | |
1504 | //\r | |
1505 | // Value of PAL_REGISTER_INFO.InfoRequest.\r | |
1506 | //\r | |
1507 | #define PAL_APPLICATION_REGISTER_IMPLEMENTED 0\r | |
1508 | #define PAL_APPLICATION_REGISTER_READABLE 1\r | |
1509 | #define PAL_CONTROL_REGISTER_IMPLEMENTED 2\r | |
1510 | #define PAL_CONTROL_REGISTER_READABLE 3\r | |
1511 | \r | |
1512 | \r | |
1513 | /**\r | |
1514 | PAL Procedure - PAL_REGISTER_INFO.\r | |
1515 | \r | |
1a2f870c | 1516 | Return AR and CR register information. It is required by Itanium processors.\r |
a7b64584 | 1517 | The PAL procedure supports the Static Registers calling\r |
1518 | convention. It could be called at physical mode and virtual\r | |
1519 | mode.\r | |
1520 | \r | |
1521 | @param Index Index of PAL_REGISTER_INFO within the list of\r | |
1522 | PAL procedures.\r | |
1523 | @param InfoRequest Unsigned 64-bit integer denoting what\r | |
1524 | register information is requested. See\r | |
1525 | PAL_REGISTER_INFO.InfoRequest above.\r | |
1526 | \r | |
1527 | @retval 0 Call completed without error\r | |
1528 | @retval -2 Invalid argument\r | |
1529 | @retval -3 Call completed with error.\r | |
1530 | \r | |
1531 | @return R9 64-bit vector denoting information for registers\r | |
1532 | 0-63. Bit 0 is register 0, bit 63 is register 63.\r | |
1533 | @return R10 64-bit vector denoting information for registers\r | |
1534 | 64-127. Bit 0 is register 64, bit 63 is register\r | |
1535 | 127.\r | |
1536 | \r | |
1537 | **/\r | |
1538 | #define PAL_REGISTER_INFO 39\r | |
1539 | \r | |
1540 | /**\r | |
1541 | PAL Procedure - PAL_RSE_INFO.\r | |
1542 | \r | |
1a2f870c | 1543 | Return RSE information. It is required by Itanium processors. The PAL\r |
a7b64584 | 1544 | procedure supports the Static Registers calling convention. It\r |
1545 | could be called at physical mode and virtual mode.\r | |
1546 | \r | |
1547 | @param Index Index of PAL_RSE_INFO within the list of\r | |
1548 | PAL procedures.\r | |
1549 | @param InfoRequest Unsigned 64-bit integer denoting what\r | |
1550 | register information is requested. See\r | |
1551 | PAL_REGISTER_INFO.InfoRequest above.\r | |
1552 | \r | |
1553 | @retval 0 Call completed without error\r | |
1554 | @retval -2 Invalid argument\r | |
1555 | @retval -3 Call completed with error.\r | |
1556 | \r | |
1557 | @return R9 Number of physical stacked general registers.\r | |
1558 | @return R10 RSE hints supported by processor.\r | |
1559 | \r | |
1560 | **/\r | |
1561 | #define PAL_RSE_INFO 19\r | |
1562 | \r | |
a7b64584 | 1563 | typedef struct {\r |
992f22b9 LG |
1564 | UINT64 VersionOfPalB:16; ///< Is a 16-bit binary coded decimal (BCD)\r |
1565 | ///< number that provides identification\r | |
1566 | ///< information about the PAL_B firmware.\r | |
a7b64584 | 1567 | UINT64 Reserved1:8;\r |
992f22b9 LG |
1568 | UINT64 PalVendor:8; ///< Is an unsigned 8-bit integer indicating the\r |
1569 | ///< vendor of the PAL code.\r | |
1570 | UINT64 VersionOfPalA:16; ///< Is a 16-bit binary coded decimal (BCD)\r | |
1571 | ///< number that provides identification\r | |
1572 | ///< information about the PAL_A firmware. In\r | |
1573 | ///< the split PAL_A model, this return value\r | |
1574 | ///< is the version number of the\r | |
1575 | ///< processor-specific PAL_A. The generic\r | |
1576 | ///< PAL_A version is not returned by this\r | |
1577 | ///< procedure in the split PAL_A model.\r | |
a7b64584 | 1578 | UINT64 Reserved2:16;\r |
1579 | } PAL_VERSION_INFO;\r | |
1580 | \r | |
1581 | /**\r | |
1582 | PAL Procedure - PAL_VERSION.\r | |
1583 | \r | |
1a2f870c | 1584 | Return version of PAL code. It is required by Itanium processors. The PAL\r |
a7b64584 | 1585 | procedure supports the Static Registers calling convention. It\r |
1586 | could be called at physical mode and virtual mode.\r | |
1587 | \r | |
1588 | @param Index Index of PAL_VERSION within the list of\r | |
1589 | PAL procedures.\r | |
1590 | @param InfoRequest Unsigned 64-bit integer denoting what\r | |
1591 | register information is requested. See\r | |
1592 | PAL_REGISTER_INFO.InfoRequest above.\r | |
1593 | \r | |
1594 | @retval 0 Call completed without error\r | |
1595 | @retval -2 Invalid argument\r | |
1596 | @retval -3 Call completed with error.\r | |
1597 | \r | |
1598 | @return R9 8-byte formatted value returning the minimum PAL\r | |
1599 | version needed for proper operation of the\r | |
1600 | processor. See PAL_VERSION_INFO above.\r | |
1601 | @return R10 8-byte formatted value returning the current PAL\r | |
1602 | version running on the processor. See\r | |
1603 | PAL_VERSION_INFO above.\r | |
1604 | \r | |
1605 | **/\r | |
1606 | #define PAL_VERSION 20\r | |
1607 | \r | |
1608 | \r | |
1609 | \r | |
1610 | //\r | |
1611 | // Vectors of PAL_MC_CLEAR_LOG.pending\r | |
1612 | //\r | |
1613 | #define PAL_MC_PENDING BIT0\r | |
1614 | #define PAL_INIT_PENDING BIT1\r | |
1615 | \r | |
1616 | /**\r | |
1617 | PAL Procedure - PAL_MC_CLEAR_LOG.\r | |
1618 | \r | |
1619 | Clear all error information from processor error logging\r | |
1a2f870c | 1620 | registers. It is required by Itanium processors. The PAL procedure supports\r |
a7b64584 | 1621 | the Static Registers calling convention. It could be called at\r |
1622 | physical mode and virtual mode.\r | |
1623 | \r | |
1624 | @param Index Index of PAL_MC_CLEAR_LOG within the list of\r | |
1625 | PAL procedures.\r | |
1626 | \r | |
1627 | @retval 0 Call completed without error\r | |
1628 | @retval -2 Invalid argument\r | |
1629 | @retval -3 Call completed with error.\r | |
1630 | \r | |
1631 | @return R9 64-bit vector denoting whether an event is\r | |
1632 | pending. See PAL_MC_CLEAR_LOG.pending above.\r | |
1633 | \r | |
1634 | **/\r | |
1635 | #define PAL_MC_CLEAR_LOG 21\r | |
1636 | \r | |
1637 | /**\r | |
1638 | PAL Procedure - PAL_MC_DRAIN.\r | |
1639 | \r | |
1640 | Ensure that all operations that could cause an MCA have\r | |
1a2f870c | 1641 | completed. It is required by Itanium processors. The PAL procedure supports\r |
a7b64584 | 1642 | the Static Registers calling convention. It could be called at\r |
1643 | physical mode and virtual mode.\r | |
1644 | \r | |
1645 | @param Index Index of PAL_MC_DRAIN within the list of PAL\r | |
1646 | procedures.\r | |
1647 | \r | |
1648 | @retval 0 Call completed without error\r | |
1649 | @retval -2 Invalid argument\r | |
1650 | @retval -3 Call completed with error.\r | |
1651 | \r | |
1652 | **/\r | |
1653 | #define PAL_MC_DRAIN 22\r | |
1654 | \r | |
1655 | \r | |
1656 | /**\r | |
1657 | PAL Procedure - PAL_MC_DYNAMIC_STATE.\r | |
1658 | \r | |
1659 | Return Processor Dynamic State for logging by SAL. It is\r | |
1660 | optional. The PAL procedure supports the Static Registers\r | |
1661 | calling convention. It could be called at physical mode.\r | |
1662 | \r | |
1663 | @param Index Index of PAL_MC_DYNAMIC_STATE within the list of PAL\r | |
1664 | procedures.\r | |
1665 | @param Offset Offset of the next 8 bytes of Dynamic Processor\r | |
1666 | State to return. (multiple of 8).\r | |
1667 | \r | |
1668 | @retval 0 Call completed without error\r | |
1669 | @retval -1 Unimplemented procedure.\r | |
1670 | @retval -2 Invalid argument\r | |
1671 | @retval -3 Call completed with error.\r | |
1672 | \r | |
1673 | @return R9 Unsigned 64-bit integer denoting bytes of Dynamic\r | |
1674 | Processor State returned.\r | |
1675 | @return R10 Next 8 bytes of Dynamic Processor State.\r | |
1676 | \r | |
1677 | **/\r | |
1678 | #define PAL_MC_DYNAMIC_STATE 24\r | |
1679 | \r | |
1680 | \r | |
1681 | \r | |
1682 | //\r | |
1683 | // Values of PAL_MC_ERROR_INFO.InfoIndex.\r | |
1684 | //\r | |
1685 | #define PAL_PROCESSOR_ERROR_MAP 0\r | |
1686 | #define PAL_PROCESSOR_STATE_PARAM 1\r | |
1687 | #define PAL_STRUCTURE_SPECIFIC_ERROR 2\r | |
1688 | \r | |
a7b64584 | 1689 | typedef struct {\r |
992f22b9 LG |
1690 | UINT64 CoreId:4; ///< Bit3:0, Processor core ID (default is 0 for\r |
1691 | ///< processors with a single core)\r | |
1692 | \r | |
1693 | UINT64 ThreadId:4; ///< Bit7:4, Logical thread ID (default is 0 for\r | |
1694 | ///< processors that execute a single thread)\r | |
1695 | \r | |
1696 | UINT64 InfoOfInsCache:4; ///< Bit11:8, Error information is\r | |
1697 | ///< available for 1st, 2nd, 3rd, and 4th\r | |
1698 | ///< level instruction caches.\r | |
1699 | \r | |
1700 | UINT64 InfoOfDataCache:4; ///< Bit15:12, Error information is\r | |
1701 | ///< available for 1st, 2nd, 3rd, and 4th\r | |
1702 | ///< level data/unified caches.\r | |
1703 | \r | |
1704 | UINT64 InfoOfInsTlb:4; ///< Bit19:16 Error information is available\r | |
1705 | ///< for 1st, 2nd, 3rd, and 4th level\r | |
1706 | ///< instruction TLB.\r | |
1707 | \r | |
1708 | UINT64 InfoOfDataTlb:4; ///< Bit23:20, Error information is available\r | |
1709 | ///< for 1st, 2nd, 3rd, and 4th level\r | |
1710 | ///< data/unified TLB\r | |
1711 | \r | |
1712 | UINT64 InfoOfProcessorBus:4; ///< Bit27:24 Error information is\r | |
1713 | ///< available for the 1st, 2nd, 3rd,\r | |
1714 | ///< and 4th level processor bus\r | |
1715 | ///< hierarchy.\r | |
1716 | UINT64 InfoOfRegisterFile:4; ///< Bit31:28 Error information is\r | |
1717 | ///< available on register file\r | |
1718 | ///< structures.\r | |
1719 | UINT64 InfoOfMicroArch:4; ///< Bit47:32, Error information is\r | |
1720 | ///< available on micro-architectural\r | |
1721 | ///< structures.\r | |
a7b64584 | 1722 | UINT64 Reserved:16;\r |
1723 | } PAL_MC_ERROR_INFO_LEVEL_INDEX;\r | |
1724 | \r | |
1725 | //\r | |
1726 | // Value of PAL_MC_ERROR_INFO.ErrorTypeIndex\r | |
1727 | //\r | |
1728 | #define PAL_ERR_INFO_BY_LEVEL_INDEX 0\r | |
1729 | #define PAL_ERR_INFO_TARGET_ADDRESS 1\r | |
1730 | #define PAL_ERR_INFO_REQUESTER_IDENTIFIER 2\r | |
1731 | #define PAL_ERR_INFO_REPONSER_INDENTIFIER 3\r | |
1732 | #define PAL_ERR_INFO_PRECISE_INSTRUCTION_POINTER 4\r | |
1733 | \r | |
a7b64584 | 1734 | typedef struct {\r |
992f22b9 LG |
1735 | UINT64 Operation:4; ///< Bit3:0, Type of cache operation that caused\r |
1736 | ///< the machine check: 0 - unknown or internal\r | |
1737 | ///< error 1 - load 2 - store 3 - instruction\r | |
1738 | ///< fetch or instruction prefetch 4 - data\r | |
1739 | ///< prefetch (both hardware and software) 5 -\r | |
1740 | ///< snoop (coherency check) 6 - cast out\r | |
1741 | ///< (explicit or implicit write-back of a cache\r | |
1742 | ///< line) 7 - move in (cache line fill)\r | |
1743 | \r | |
1744 | UINT64 FailedCacheLevel:2; ///< Bit5:4 Level of cache where the\r | |
1745 | ///< error occurred. A value of 0\r | |
1746 | ///< indicates the first level of cache.\r | |
a7b64584 | 1747 | UINT64 Reserved1:2;\r |
992f22b9 LG |
1748 | UINT64 FailedInDataPart:1; ///< Bit8, Failure located in the data part of the cache line.\r |
1749 | UINT64 FailedInTagPart:1; ///< Bit9, Failure located in the tag part of the cache line.\r | |
1750 | UINT64 FailedInDataCache:1; ///< Bit10, Failure located in the data cache\r | |
7e6a7a63 | 1751 | \r |
992f22b9 LG |
1752 | UINT64 FailedInInsCache:1; ///< Bit11, Failure located in the\r |
1753 | ///< instruction cache.\r | |
9095d37b | 1754 | \r |
992f22b9 LG |
1755 | UINT64 Mesi:3; ///< Bit14:12, 0 - cache line is invalid. 1 - cache\r |
1756 | ///< line is held shared. 2 - cache line is held\r | |
1757 | ///< exclusive. 3 - cache line is modified. All other\r | |
1758 | ///< values are reserved.\r | |
9095d37b | 1759 | \r |
992f22b9 LG |
1760 | UINT64 MesiIsValid:1; ///< Bit15, The mesi field in the cache_check\r |
1761 | ///< parameter is valid.\r | |
9095d37b | 1762 | \r |
992f22b9 LG |
1763 | UINT64 FailedWay:5; ///< Bit20:16, Failure located in the way of\r |
1764 | ///< the cache indicated by this value.\r | |
7e6a7a63 | 1765 | \r |
992f22b9 LG |
1766 | UINT64 WayIndexIsValid:1; ///< Bit21, The way and index field in the\r |
1767 | ///< cache_check parameter is valid.\r | |
a7b64584 | 1768 | \r |
1769 | UINT64 Reserved2:1;\r | |
992f22b9 LG |
1770 | UINT64 MultipleBitsError:1; ///< Bit23, A multiple-bit error was\r |
1771 | ///< detected, and data was poisoned for\r | |
1772 | ///< the corresponding cache line during\r | |
1773 | ///< castout.\r | |
a7b64584 | 1774 | UINT64 Reserved3:8;\r |
992f22b9 LG |
1775 | UINT64 IndexOfCacheLineError:20; ///< Bit51:32, Index of the cache\r |
1776 | ///< line where the error occurred.\r | |
a7b64584 | 1777 | UINT64 Reserved4:2;\r |
a7b64584 | 1778 | \r |
992f22b9 LG |
1779 | UINT64 InstructionSet:1; ///< Bit54, Instruction set. If this value\r |
1780 | ///< is set to zero, the instruction that\r | |
1781 | ///< generated the machine check was an\r | |
1782 | ///< Intel Itanium instruction. If this bit\r | |
1783 | ///< is set to one, the instruction that\r | |
1784 | ///< generated the machine check was IA-32\r | |
1785 | ///< instruction.\r | |
1786 | \r | |
1787 | UINT64 InstructionSetIsValid:1; ///< Bit55, The is field in the\r | |
1788 | ///< cache_check parameter is valid.\r | |
1789 | \r | |
1790 | UINT64 PrivilegeLevel:2; ///< Bit57:56, Privilege level. The\r | |
1791 | ///< privilege level of the instruction\r | |
1792 | ///< bundle responsible for generating the\r | |
1793 | ///< machine check.\r | |
1794 | \r | |
1795 | UINT64 PrivilegeLevelIsValide:1; ///< Bit58, The pl field of the\r | |
1796 | ///< cache_check parameter is\r | |
1797 | ///< valid.\r | |
1798 | \r | |
1799 | UINT64 McCorrected:1; ///< Bit59, Machine check corrected: This bit\r | |
1800 | ///< is set to one to indicate that the machine\r | |
1801 | ///< check has been corrected.\r | |
1802 | \r | |
1803 | UINT64 TargetAddressIsValid:1; ///< Bit60, Target address is valid:\r | |
1804 | ///< This bit is set to one to\r | |
1805 | ///< indicate that a valid target\r | |
1806 | ///< address has been logged.\r | |
1807 | \r | |
1808 | UINT64 RequesterIdentifier:1; ///< Bit61, Requester identifier: This\r | |
1809 | ///< bit is set to one to indicate that\r | |
1810 | ///< a valid requester identifier has\r | |
1811 | ///< been logged.\r | |
1812 | \r | |
1813 | UINT64 ResponserIdentifier:1; ///< Bit62, Responder identifier: This\r | |
1814 | ///< bit is set to one to indicate that\r | |
1815 | ///< a valid responder identifier has\r | |
1816 | ///< been logged.\r | |
1817 | \r | |
1818 | UINT64 PreciseInsPointer:1; ///< Bit63, Precise instruction pointer.\r | |
1819 | ///< This bit is set to one to indicate\r | |
1820 | ///< that a valid precise instruction\r | |
1821 | ///< pointer has been logged.\r | |
a7b64584 | 1822 | \r |
1823 | } PAL_CACHE_CHECK_INFO;\r | |
1824 | \r | |
a7b64584 | 1825 | \r |
a7b64584 | 1826 | typedef struct {\r |
992f22b9 LG |
1827 | UINT64 FailedSlot:8; ///< Bit7:0, Slot number of the translation\r |
1828 | ///< register where the failure occurred.\r | |
1829 | UINT64 FailedSlotIsValid:1; ///< Bit8, The tr_slot field in the\r | |
1830 | ///< TLB_check parameter is valid.\r | |
a7b64584 | 1831 | UINT64 Reserved1 :1;\r |
992f22b9 LG |
1832 | UINT64 TlbLevel:2; ///< Bit11:10, The level of the TLB where the\r |
1833 | ///< error occurred. A value of 0 indicates the\r | |
1834 | ///< first level of TLB\r | |
a7b64584 | 1835 | UINT64 Reserved2 :4;\r |
7e6a7a63 | 1836 | \r |
992f22b9 LG |
1837 | UINT64 FailedInDataTr:1; ///< Bit16, Error occurred in the data\r |
1838 | ///< translation registers.\r | |
1839 | \r | |
1840 | UINT64 FailedInInsTr:1; ///< Bit17, Error occurred in the instruction\r | |
1841 | ///< translation registers\r | |
1842 | \r | |
1843 | UINT64 FailedInDataTc:1; ///< Bit18, Error occurred in data\r | |
1844 | ///< translation cache.\r | |
1845 | \r | |
1846 | UINT64 FailedInInsTc:1; ///< Bit19, Error occurred in the instruction\r | |
1847 | ///< translation cache.\r | |
1848 | \r | |
1849 | UINT64 FailedOperation:4; ///< Bit23:20, Type of cache operation that\r | |
1850 | ///< caused the machine check: 0 - unknown\r | |
1851 | ///< 1 - TLB access due to load instruction\r | |
1852 | ///< 2 - TLB access due to store\r | |
1853 | ///< instruction 3 - TLB access due to\r | |
1854 | ///< instruction fetch or instruction\r | |
1855 | ///< prefetch 4 - TLB access due to data\r | |
1856 | ///< prefetch (both hardware and software)\r | |
1857 | ///< 5 - TLB shoot down access 6 - TLB\r | |
1858 | ///< probe instruction (probe, tpa) 7 -\r | |
1859 | ///< move in (VHPT fill) 8 - purge (insert\r | |
1860 | ///< operation that purges entries or a TLB\r | |
1861 | ///< purge instruction) All other values\r | |
1862 | ///< are reserved.\r | |
7e6a7a63 | 1863 | \r |
a7b64584 | 1864 | UINT64 Reserved3:30;\r |
992f22b9 LG |
1865 | UINT64 InstructionSet:1; ///< Bit54, Instruction set. If this value\r |
1866 | ///< is set to zero, the instruction that\r | |
1867 | ///< generated the machine check was an\r | |
1868 | ///< Intel Itanium instruction. If this bit\r | |
1869 | ///< is set to one, the instruction that\r | |
1870 | ///< generated the machine check was IA-32\r | |
1871 | ///< instruction.\r | |
1872 | \r | |
1873 | UINT64 InstructionSetIsValid:1; ///< Bit55, The is field in the\r | |
1874 | ///< TLB_check parameter is valid.\r | |
1875 | \r | |
1876 | UINT64 PrivelegeLevel:2; ///< Bit57:56, Privilege level. The\r | |
1877 | ///< privilege level of the instruction\r | |
1878 | ///< bundle responsible for generating the\r | |
1879 | ///< machine check.\r | |
1880 | \r | |
1881 | UINT64 PrivelegeLevelIsValid:1; ///< Bit58, The pl field of the\r | |
1882 | ///< TLB_check parameter is valid.\r | |
1883 | \r | |
1884 | UINT64 McCorrected:1; ///< Bit59, Machine check corrected: This bit\r | |
1885 | ///< is set to one to indicate that the machine\r | |
1886 | ///< check has been corrected.\r | |
1887 | \r | |
1888 | UINT64 TargetAddressIsValid:1; ///< Bit60, Target address is valid:\r | |
1889 | ///< This bit is set to one to\r | |
1890 | ///< indicate that a valid target\r | |
1891 | ///< address has been logged.\r | |
1892 | \r | |
1893 | UINT64 RequesterIdentifier:1; ///< Bit61 Requester identifier: This\r | |
1894 | ///< bit is set to one to indicate that\r | |
1895 | ///< a valid requester identifier has\r | |
1896 | ///< been logged.\r | |
1897 | \r | |
1898 | UINT64 ResponserIdentifier:1; ///< Bit62, Responder identifier: This\r | |
1899 | ///< bit is set to one to indicate that\r | |
1900 | ///< a valid responder identifier has\r | |
1901 | ///< been logged.\r | |
1902 | \r | |
1903 | UINT64 PreciseInsPointer:1; ///< Bit63 Precise instruction pointer.\r | |
1904 | ///< This bit is set to one to indicate\r | |
1905 | ///< that a valid precise instruction\r | |
1906 | ///< pointer has been logged.\r | |
a7b64584 | 1907 | } PAL_TLB_CHECK_INFO;\r |
1908 | \r | |
1909 | /**\r | |
1910 | PAL Procedure - PAL_MC_ERROR_INFO.\r | |
1911 | \r | |
1912 | Return Processor Machine Check Information and Processor\r | |
1a2f870c | 1913 | Static State for logging by SAL. It is required by Itanium processors. The\r |
a7b64584 | 1914 | PAL procedure supports the Static Registers calling\r |
1915 | convention. It could be called at physical and virtual mode.\r | |
1916 | \r | |
1917 | @param Index Index of PAL_MC_ERROR_INFO within the list of PAL\r | |
1918 | procedures.\r | |
1919 | @param InfoIndex Unsigned 64-bit integer identifying the\r | |
1920 | error information that is being requested.\r | |
1921 | See PAL_MC_ERROR_INFO.InfoIndex.\r | |
1922 | @param LevelIndex 8-byte formatted value identifying the\r | |
1923 | structure to return error information\r | |
1924 | on. See PAL_MC_ERROR_INFO_LEVEL_INDEX.\r | |
1925 | @param ErrorTypeIndex Unsigned 64-bit integer denoting the\r | |
1926 | type of error information that is\r | |
1927 | being requested for the structure\r | |
1928 | identified in LevelIndex.\r | |
1929 | \r | |
1930 | @retval 0 Call completed without error\r | |
1931 | @retval -2 Invalid argument\r | |
1932 | @retval -3 Call completed with error.\r | |
1933 | @retval -6 Argument was valid, but no error\r | |
1934 | information was available\r | |
1935 | \r | |
1936 | @return R9 Error information returned. The format of this\r | |
1937 | value is dependant on the input values passed.\r | |
1938 | @return R10 If this value is zero, all the error information\r | |
1939 | specified by err_type_index has been returned. If\r | |
1940 | this value is one, more structure-specific error\r | |
1941 | information is available and the caller needs to\r | |
1942 | make this procedure call again with level_index\r | |
1943 | unchanged and err_type_index, incremented.\r | |
1944 | \r | |
1945 | **/\r | |
1946 | #define PAL_MC_ERROR_INFO 25\r | |
1947 | \r | |
1948 | /**\r | |
1949 | PAL Procedure - PAL_MC_EXPECTED.\r | |
1950 | \r | |
1951 | Set/Reset Expected Machine Check Indicator. It is required by\r | |
1a2f870c | 1952 | Itanium processors. The PAL procedure supports the Static Registers calling\r |
a7b64584 | 1953 | convention. It could be called at physical mode.\r |
1954 | \r | |
1955 | @param Index Index of PAL_MC_EXPECTED within the list of PAL\r | |
1956 | procedures.\r | |
1957 | @param Expected Unsigned integer with a value of 0 or 1 to\r | |
1958 | set or reset the hardware resource\r | |
1959 | PALE_CHECK examines for expected machine\r | |
1960 | checks.\r | |
1961 | \r | |
1962 | @retval 0 Call completed without error\r | |
1963 | @retval -2 Invalid argument\r | |
1964 | @retval -3 Call completed with error.\r | |
1965 | \r | |
1966 | @return R9 Unsigned integer denoting whether a machine check\r | |
1967 | was previously expected.\r | |
1968 | \r | |
1969 | **/\r | |
1970 | #define PAL_MC_EXPECTED 23\r | |
1971 | \r | |
1972 | /**\r | |
1973 | PAL Procedure - PAL_MC_REGISTER_MEM.\r | |
1974 | \r | |
1975 | Register min-state save area with PAL for machine checks and\r | |
1a2f870c | 1976 | inits. It is required by Itanium processors. The PAL procedure supports the\r |
a7b64584 | 1977 | Static Registers calling convention. It could be called at\r |
1978 | physical mode.\r | |
1979 | \r | |
1980 | @param Index Index of PAL_MC_REGISTER_MEM within the list of PAL\r | |
1981 | procedures.\r | |
1982 | @param Address Physical address of the buffer to be\r | |
1983 | registered with PAL.\r | |
1984 | \r | |
1985 | @retval 0 Call completed without error\r | |
1986 | @retval -2 Invalid argument\r | |
1987 | @retval -3 Call completed with error.\r | |
1988 | \r | |
1989 | **/\r | |
1990 | #define PAL_MC_REGISTER_MEM 27\r | |
1991 | \r | |
1992 | /**\r | |
1993 | PAL Procedure - PAL_MC_RESUME.\r | |
1994 | \r | |
1995 | Restore minimal architected state and return to interrupted\r | |
1a2f870c | 1996 | process. It is required by Itanium processors. The PAL procedure supports the\r |
a7b64584 | 1997 | Static Registers calling convention. It could be called at\r |
1998 | physical mode.\r | |
1999 | \r | |
2000 | @param Index Index of PAL_MC_RESUME within the list of PAL\r | |
2001 | procedures.\r | |
2002 | @param SetCmci Unsigned 64 bit integer denoting whether to\r | |
2003 | set the CMC interrupt. A value of 0 indicates\r | |
2004 | not to set the interrupt, a value of 1\r | |
2005 | indicated to set the interrupt, and all other\r | |
2006 | values are reserved.\r | |
2007 | @param SavePtr Physical address of min-state save area used\r | |
2008 | to used to restore processor state.\r | |
2009 | @param NewContext Unsigned 64-bit integer denoting whether\r | |
2010 | the caller is returning to a new context.\r | |
2011 | A value of 0 indicates the caller is\r | |
2012 | returning to the interrupted context, a\r | |
2013 | value of 1 indicates that the caller is\r | |
2014 | returning to a new context.\r | |
2015 | \r | |
2016 | @retval -2 Invalid argument\r | |
2017 | @retval -3 Call completed with error.\r | |
2018 | \r | |
2019 | **/\r | |
2020 | #define PAL_MC_RESUME 26\r | |
2021 | \r | |
2022 | /**\r | |
2023 | PAL Procedure - PAL_HALT.\r | |
2024 | \r | |
2025 | Enter the low-power HALT state or an implementation-dependent\r | |
2026 | low-power state. It is optinal. The PAL procedure supports the\r | |
2027 | Static Registers calling convention. It could be called at\r | |
2028 | physical mode.\r | |
2029 | \r | |
2030 | @param Index Index of PAL_HALT within the list of PAL\r | |
2031 | procedures.\r | |
2032 | @param HaltState Unsigned 64-bit integer denoting low power\r | |
2033 | state requested.\r | |
2034 | @param IoDetailPtr 8-byte aligned physical address pointer to\r | |
2035 | information on the type of I/O\r | |
2036 | (load/store) requested.\r | |
2037 | \r | |
2038 | @retval 0 Call completed without error\r | |
2039 | @retval -1 Unimplemented procedure\r | |
2040 | @retval -2 Invalid argument\r | |
2041 | @retval -3 Call completed with error.\r | |
2042 | \r | |
2043 | @return R9 Value returned if a load instruction is requested\r | |
2044 | in the io_detail_ptr\r | |
2045 | \r | |
2046 | **/\r | |
2047 | #define PAL_HALT 28\r | |
2048 | \r | |
2049 | \r | |
2050 | /**\r | |
2051 | PAL Procedure - PAL_HALT_INFO.\r | |
2052 | \r | |
2053 | Return the low power capabilities of the processor. It is\r | |
1a2f870c | 2054 | required by Itanium processors. The PAL procedure supports the\r |
a7b64584 | 2055 | Stacked Registers calling convention. It could be called at\r |
2056 | physical and virtual mode.\r | |
2057 | \r | |
2058 | @param Index Index of PAL_HALT_INFO within the list of PAL\r | |
2059 | procedures.\r | |
2060 | @param PowerBuffer 64-bit pointer to a 64-byte buffer aligned\r | |
2061 | on an 8-byte boundary.\r | |
2062 | \r | |
2063 | @retval 0 Call completed without error\r | |
2064 | @retval -2 Invalid argument\r | |
2065 | @retval -3 Call completed with error.\r | |
2066 | \r | |
2067 | **/\r | |
2068 | #define PAL_HALT_INFO 257\r | |
2069 | \r | |
2070 | \r | |
2071 | /**\r | |
2072 | PAL Procedure - PAL_HALT_LIGHT.\r | |
2073 | \r | |
2074 | Enter the low power LIGHT HALT state. It is required by\r | |
1a2f870c | 2075 | Itanium processors. The PAL procedure supports the Static Registers calling\r |
a7b64584 | 2076 | convention. It could be called at physical and virtual mode.\r |
2077 | \r | |
2078 | @param Index Index of PAL_HALT_LIGHT within the list of PAL\r | |
2079 | procedures.\r | |
2080 | \r | |
2081 | @retval 0 Call completed without error\r | |
2082 | @retval -2 Invalid argument\r | |
2083 | @retval -3 Call completed with error.\r | |
2084 | \r | |
2085 | **/\r | |
2086 | #define PAL_HALT_LIGHT 29\r | |
2087 | \r | |
2088 | /**\r | |
2089 | PAL Procedure - PAL_CACHE_LINE_INIT.\r | |
2090 | \r | |
2091 | Initialize tags and data of a cache line for processor\r | |
1a2f870c | 2092 | testing. It is required by Itanium processors. The PAL procedure supports the\r |
a7b64584 | 2093 | Static Registers calling convention. It could be called at\r |
2094 | physical and virtual mode.\r | |
2095 | \r | |
2096 | @param Index Index of PAL_CACHE_LINE_INIT within the list of PAL\r | |
2097 | procedures.\r | |
2098 | @param Address Unsigned 64-bit integer value denoting the\r | |
2099 | physical address from which the physical page\r | |
2100 | number is to be generated. The address must be\r | |
2101 | an implemented physical address, bit 63 must\r | |
2102 | be zero.\r | |
2103 | @param DataValue 64-bit data value which is used to\r | |
2104 | initialize the cache line.\r | |
2105 | \r | |
2106 | @retval 0 Call completed without error\r | |
2107 | @retval -2 Invalid argument\r | |
2108 | @retval -3 Call completed with error.\r | |
2109 | \r | |
2110 | **/\r | |
2111 | #define PAL_CACHE_LINE_INIT 31\r | |
2112 | \r | |
2113 | /**\r | |
2114 | PAL Procedure - PAL_CACHE_READ.\r | |
2115 | \r | |
2116 | Read tag and data of a cache line for diagnostic testing. It\r | |
2117 | is optional. The PAL procedure supports the\r | |
2118 | Satcked Registers calling convention. It could be called at\r | |
2119 | physical mode.\r | |
2120 | \r | |
2121 | @param Index Index of PAL_CACHE_READ within the list of PAL\r | |
2122 | procedures.\r | |
2123 | @param LineId 8-byte formatted value describing where in the\r | |
2124 | cache to read the data.\r | |
2125 | @param Address 64-bit 8-byte aligned physical address from\r | |
2126 | which to read the data. The address must be an\r | |
2127 | implemented physical address on the processor\r | |
2128 | model with bit 63 set to zero.\r | |
2129 | \r | |
2130 | @retval 1 The word at address was found in the\r | |
2131 | cache, but the line was invalid.\r | |
2132 | @retval 0 Call completed without error\r | |
2133 | @retval -2 Invalid argument\r | |
2134 | @retval -3 Call completed with error.\r | |
2135 | @retval -5 The word at address was not found in the\r | |
2136 | cache.\r | |
2137 | @retval -7 The operation requested is not supported\r | |
2138 | for this cache_type and level.\r | |
2139 | \r | |
2140 | @return R9 Right-justified value returned from the cache\r | |
2141 | line.\r | |
2142 | @return R10 The number of bits returned in data.\r | |
2143 | @return R11 The status of the cache line.\r | |
2144 | \r | |
2145 | **/\r | |
2146 | #define PAL_CACHE_READ 259\r | |
2147 | \r | |
2148 | \r | |
2149 | /**\r | |
2150 | PAL Procedure - PAL_CACHE_WRITE.\r | |
2151 | \r | |
2152 | Write tag and data of a cache for diagnostic testing. It is\r | |
2153 | optional. The PAL procedure supports the Satcked Registers\r | |
2154 | calling convention. It could be called at physical mode.\r | |
2155 | \r | |
2156 | @param Index Index of PAL_CACHE_WRITE within the list of PAL\r | |
2157 | procedures.\r | |
2158 | @param LineId 8-byte formatted value describing where in the\r | |
2159 | cache to write the data.\r | |
2160 | @param Address 64-bit 8-byte aligned physical address at\r | |
2161 | which the data should be written. The address\r | |
2162 | must be an implemented physical address on the\r | |
2163 | processor model with bit 63 set to 0.\r | |
2164 | @param Data Unsigned 64-bit integer value to write into\r | |
2165 | the specified part of the cache.\r | |
2166 | \r | |
2167 | @retval 0 Call completed without error\r | |
2168 | @retval -2 Invalid argument\r | |
2169 | @retval -3 Call completed with error.\r | |
2170 | @retval -7 The operation requested is not supported\r | |
2171 | for this cache_type and level.\r | |
2172 | \r | |
2173 | **/\r | |
2174 | #define PAL_CACHE_WRITE 260\r | |
2175 | \r | |
2176 | /**\r | |
2177 | PAL Procedure - PAL_TEST_INFO.\r | |
2178 | \r | |
2179 | Returns alignment and size requirements needed for the memory\r | |
2180 | buffer passed to the PAL_TEST_PROC procedure as well as\r | |
2181 | information on self-test control words for the processor self\r | |
1a2f870c | 2182 | tests. It is required by Itanium processors. The PAL procedure supports the\r |
a7b64584 | 2183 | Static Registers calling convention. It could be called at\r |
2184 | physical mode.\r | |
2185 | \r | |
2186 | @param Index Index of PAL_TEST_INFO within the list of PAL\r | |
2187 | procedures.\r | |
2188 | @param TestPhase Unsigned integer that specifies which phase\r | |
2189 | of the processor self-test information is\r | |
2190 | being requested on. A value of 0 indicates\r | |
2191 | the phase two of the processor self-test and\r | |
2192 | a value of 1 indicates phase one of the\r | |
2193 | processor self-test. All other values are\r | |
2194 | reserved.\r | |
2195 | \r | |
2196 | @retval 0 Call completed without error\r | |
2197 | @retval -2 Invalid argument\r | |
2198 | @retval -3 Call completed with error.\r | |
2199 | \r | |
2200 | @return R9 Unsigned 64-bit integer denoting the number of\r | |
2201 | bytes of main memory needed to perform the second\r | |
2202 | phase of processor self-test.\r | |
2203 | @return R10 Unsigned 64-bit integer denoting the alignment\r | |
2204 | required for the memory buffer.\r | |
2205 | @return R11 48-bit wide bit-field indicating if control of\r | |
2206 | the processor self-tests is supported and which\r | |
2207 | bits of the test_control field are defined for\r | |
2208 | use.\r | |
2209 | \r | |
2210 | **/\r | |
2211 | #define PAL_TEST_INFO 37\r | |
2212 | \r | |
a7b64584 | 2213 | typedef struct {\r |
992f22b9 LG |
2214 | UINT64 BufferSize:56; ///< Indicates the size in bytes of the memory\r |
2215 | ///< buffer that is passed to this procedure.\r | |
2216 | ///< BufferSize must be greater than or equal in\r | |
2217 | ///< size to the bytes_needed return value from\r | |
2218 | ///< PAL_TEST_INFO, otherwise this procedure will\r | |
2219 | ///< return with an invalid argument return\r | |
2220 | ///< value.\r | |
2221 | \r | |
2222 | UINT64 TestPhase:8; ///< Defines which phase of the processor\r | |
2223 | ///< self-tests are requested to be run. A value\r | |
2224 | ///< of zero indicates to run phase two of the\r | |
2225 | ///< processor self-tests. Phase two of the\r | |
2226 | ///< processor self-tests are ones that require\r | |
2227 | ///< external memory to execute correctly. A\r | |
2228 | ///< value of one indicates to run phase one of\r | |
2229 | ///< the processor self-tests. Phase one of the\r | |
2230 | ///< processor self-tests are tests run during\r | |
2231 | ///< PALE_RESET and do not depend on external\r | |
2232 | ///< memory to run correctly. When the caller\r | |
2233 | ///< requests to have phase one of the processor\r | |
2234 | ///< self-test run via this procedure call, a\r | |
2235 | ///< memory buffer may be needed to save and\r | |
2236 | ///< restore state as required by the PAL calling\r | |
2237 | ///< conventions. The procedure PAL_TEST_INFO\r | |
2238 | ///< informs the caller about the requirements of\r | |
2239 | ///< the memory buffer.\r | |
a7b64584 | 2240 | } PAL_TEST_INFO_INFO;\r |
2241 | \r | |
a7b64584 | 2242 | typedef struct {\r |
992f22b9 LG |
2243 | UINT64 TestControl:47; ///< This is an ordered implementation-specific\r |
2244 | ///< control word that allows the user control\r | |
2245 | ///< over the length and runtime of the\r | |
2246 | ///< processor self-tests. This control word is\r | |
2247 | ///< ordered from the longest running tests up\r | |
2248 | ///< to the shortest running tests with bit 0\r | |
2249 | ///< controlling the longest running test. PAL\r | |
2250 | ///< may not implement all 47-bits of the\r | |
2251 | ///< test_control word. PAL communicates if a\r | |
2252 | ///< bit provides control by placing a zero in\r | |
2253 | ///< that bit. If a bit provides no control,\r | |
2254 | ///< PAL will place a one in it. PAL will have\r | |
2255 | ///< two sets of test_control bits for the two\r | |
2256 | ///< phases of the processor self-test. PAL\r | |
2257 | ///< provides information about implemented\r | |
2258 | ///< test_control bits at the hand-off from PAL\r | |
2259 | ///< to SAL for the firmware recovery check.\r | |
2260 | ///< These test_control bits provide control\r | |
2261 | ///< for phase one of processor self-test. It\r | |
2262 | ///< also provides this information via the PAL\r | |
2263 | ///< procedure call PAL_TEST_INFO for both the\r | |
2264 | ///< phase one and phase two processor tests\r | |
2265 | ///< depending on which information the caller\r | |
2266 | ///< is requesting. PAL interprets these bits\r | |
2267 | ///< as input parameters on two occasions. The\r | |
2268 | ///< first time is when SAL passes control back\r | |
2269 | ///< to PAL after the firmware recovery check.\r | |
2270 | ///< The second time is when a call to\r | |
2271 | ///< PAL_TEST_PROC is made. When PAL interprets\r | |
2272 | ///< these bits it will only interpret\r | |
2273 | ///< implemented test_control bits and will\r | |
2274 | ///< ignore the values located in the\r | |
2275 | ///< unimplemented test_control bits. PAL\r | |
2276 | ///< interprets the implemented bits such that\r | |
2277 | ///< if a bit contains a zero, this indicates\r | |
2278 | ///< to run the test. If a bit contains a one,\r | |
2279 | ///< this indicates to PAL to skip the test. If\r | |
2280 | ///< the cs bit indicates that control is not\r | |
2281 | ///< available, the test_control bits will be\r | |
2282 | ///< ignored or generate an illegal argument in\r | |
2283 | ///< procedure calls if the caller sets these\r | |
2284 | ///< bits.\r | |
9095d37b | 2285 | \r |
992f22b9 LG |
2286 | UINT64 ControlSupport:1; ///< This bit defines if an implementation\r |
2287 | ///< supports control of the PAL self-tests\r | |
2288 | ///< via the self-test control word. If\r | |
2289 | ///< this bit is 0, the implementation does\r | |
2290 | ///< not support control of the processor\r | |
2291 | ///< self-tests via the self-test control\r | |
2292 | ///< word. If this bit is 1, the\r | |
2293 | ///< implementation does support control of\r | |
2294 | ///< the processor self-tests via the\r | |
2295 | ///< self-test control word. If control is\r | |
2296 | ///< not supported, GR37 will be ignored at\r | |
2297 | ///< the hand-off between SAL and PAL after\r | |
2298 | ///< the firmware recovery check and the\r | |
2299 | ///< PAL procedures related to the\r | |
2300 | ///< processor self-tests may return\r | |
2301 | ///< illegal arguments if a user tries to\r | |
2302 | ///< use the self-test control features.\r | |
a7b64584 | 2303 | UINT64 Reserved:16;\r |
2304 | } PAL_SELF_TEST_CONTROL;\r | |
2305 | \r | |
a7b64584 | 2306 | typedef struct {\r |
992f22b9 LG |
2307 | UINT64 Attributes:8; ///< Specifies the memory attributes that are\r |
2308 | ///< allowed to be used with the memory buffer\r | |
2309 | ///< passed to this procedure. The attributes\r | |
2310 | ///< parameter is a vector where each bit\r | |
2311 | ///< represents one of the virtual memory\r | |
2312 | ///< attributes defined by the architecture.See\r | |
2313 | ///< MEMORY_AATRIBUTES. The caller is required\r | |
2314 | ///< to support the cacheable attribute for the\r | |
2315 | ///< memory buffer, otherwise an invalid\r | |
2316 | ///< argument will be returned.\r | |
a7b64584 | 2317 | UINT64 Reserved:8;\r |
992f22b9 LG |
2318 | UINT64 TestControl:48; ///< Is the self-test control word\r |
2319 | ///< corresponding to the test_phase passed.\r | |
2320 | ///< This test_control directs the coverage and\r | |
2321 | ///< runtime of the processor self-tests\r | |
2322 | ///< specified by the test_phase input\r | |
2323 | ///< argument. Information on if this\r | |
2324 | ///< feature is implemented and the number of\r | |
2325 | ///< bits supported can be obtained by the\r | |
2326 | ///< PAL_TEST_INFO procedure call. If this\r | |
2327 | ///< feature is implemented by the processor,\r | |
2328 | ///< the caller can selectively skip parts of\r | |
2329 | ///< the processor self-test by setting\r | |
2330 | ///< test_control bits to a one. If a bit has a\r | |
2331 | ///< zero, this test will be run. The values in\r | |
2332 | ///< the unimplemented bits are ignored. If\r | |
2333 | ///< PAL_TEST_INFO indicated that the self-test\r | |
2334 | ///< control word is not implemented, this\r | |
2335 | ///< procedure will return with an invalid\r | |
2336 | ///< argument status if the caller sets any of\r | |
2337 | ///< the test_control bits. See\r | |
2338 | ///< PAL_SELF_TEST_CONTROL.\r | |
a7b64584 | 2339 | } PAL_TEST_CONTROL;\r |
2340 | \r | |
2341 | /**\r | |
2342 | PAL Procedure - PAL_TEST_PROC.\r | |
2343 | \r | |
1a2f870c | 2344 | Perform late processor self test. It is required by Itanium processors. The\r |
a7b64584 | 2345 | PAL procedure supports the Static Registers calling\r |
2346 | convention. It could be called at physical mode.\r | |
2347 | \r | |
2348 | @param Index Index of PAL_TEST_PROC within the list of PAL\r | |
2349 | procedures.\r | |
2350 | @param TestAddress 64-bit physical address of main memory\r | |
2351 | area to be used by processor self-test.\r | |
2352 | The memory region passed must be\r | |
2353 | cacheable, bit 63 must be zero.\r | |
2354 | @param TestInfo Input argument specifying the size of the\r | |
2355 | memory buffer passed and the phase of the\r | |
2356 | processor self-test that should be run. See\r | |
2357 | PAL_TEST_INFO.\r | |
2358 | @param TestParam Input argument specifying the self-test\r | |
2359 | control word and the allowable memory\r | |
2360 | attributes that can be used with the memory\r | |
2361 | buffer. See PAL_TEST_CONTROL.\r | |
2362 | \r | |
2363 | @retval 1 Call completed without error, but hardware\r | |
2364 | failures occurred during self-test.\r | |
2365 | @retval 0 Call completed without error\r | |
2366 | @retval -2 Invalid argument\r | |
2367 | @retval -3 Call completed with error.\r | |
2368 | \r | |
2369 | @return R9 Formatted 8-byte value denoting the state of the\r | |
2370 | processor after self-test\r | |
2371 | \r | |
2372 | **/\r | |
2373 | #define PAL_TEST_PROC 258\r | |
2374 | \r | |
a7b64584 | 2375 | typedef struct {\r |
992f22b9 LG |
2376 | UINT32 NumberOfInterruptControllers; ///< Number of interrupt\r |
2377 | ///< controllers currently\r | |
2378 | ///< enabled on the system.\r | |
7e6a7a63 | 2379 | \r |
992f22b9 LG |
2380 | UINT32 NumberOfProcessors; ///< Number of processors currently\r |
2381 | ///< enabled on the system.\r | |
a7b64584 | 2382 | } PAL_PLATFORM_INFO;\r |
2383 | \r | |
2384 | /**\r | |
2385 | PAL Procedure - PAL_COPY_INFO.\r | |
2386 | \r | |
2387 | Return information needed to relocate PAL procedures and PAL\r | |
1a2f870c | 2388 | PMI code to memory. It is required by Itanium processors. The PAL procedure\r |
a7b64584 | 2389 | supports the Static Registers calling convention. It could be\r |
2390 | called at physical mode.\r | |
2391 | \r | |
2392 | @param Index Index of PAL_COPY_INFO within the list of PAL\r | |
2393 | procedures.\r | |
2394 | @param CopyType Unsigned integer denoting type of procedures\r | |
2395 | for which copy information is requested.\r | |
2396 | @param PlatformInfo 8-byte formatted value describing the\r | |
2397 | number of processors and the number of\r | |
2398 | interrupt controllers currently enabled\r | |
2399 | on the system. See PAL_PLATFORM_INFO.\r | |
2400 | @param McaProcStateInfo Unsigned integer denoting the number\r | |
2401 | of bytes that SAL needs for the\r | |
2402 | min-state save area for each\r | |
2403 | processor.\r | |
2404 | \r | |
2405 | @retval 0 Call completed without error\r | |
2406 | @retval -2 Invalid argument\r | |
2407 | @retval -3 Call completed with error.\r | |
2408 | \r | |
2409 | @return R9 Unsigned integer denoting the number of bytes of\r | |
2410 | PAL information that must be copied to main\r | |
2411 | memory.\r | |
2412 | @return R10 Unsigned integer denoting the starting alignment\r | |
2413 | of the data to be copied.\r | |
2414 | \r | |
2415 | **/\r | |
2416 | #define PAL_COPY_INFO 30\r | |
2417 | \r | |
2418 | /**\r | |
2419 | PAL Procedure - PAL_COPY_PAL.\r | |
2420 | \r | |
2421 | Relocate PAL procedures and PAL PMI code to memory. It is\r | |
1a2f870c | 2422 | required by Itanium processors. The PAL procedure supports the Stacked\r |
a7b64584 | 2423 | Registers calling convention. It could be called at physical\r |
2424 | mode.\r | |
2425 | \r | |
2426 | @param Index Index of PAL_COPY_PAL within the list of PAL\r | |
2427 | procedures.\r | |
2428 | @param TargetAddress Physical address of a memory buffer to\r | |
2429 | copy relocatable PAL procedures and PAL\r | |
2430 | PMI code.\r | |
2431 | @param AllocSize Unsigned integer denoting the size of the\r | |
2432 | buffer passed by SAL for the copy operation.\r | |
2433 | @param CopyOption Unsigned integer indicating whether\r | |
2434 | relocatable PAL code and PAL PMI code\r | |
2435 | should be copied from firmware address\r | |
2436 | space to main memory.\r | |
2437 | \r | |
2438 | @retval 0 Call completed without error\r | |
2439 | @retval -2 Invalid argument\r | |
2440 | @retval -3 Call completed with error.\r | |
2441 | \r | |
2442 | @return R9 Unsigned integer denoting the offset of PAL_PROC\r | |
2443 | in the relocatable segment copied.\r | |
2444 | \r | |
2445 | **/\r | |
2446 | #define PAL_COPY_PAL 256\r | |
2447 | \r | |
2448 | /**\r | |
2449 | PAL Procedure - PAL_ENTER_IA_32_ENV.\r | |
2450 | \r | |
2451 | Enter IA-32 System environment. It is optional. The PAL\r | |
2452 | procedure supports the Static Registers calling convention.\r | |
2453 | It could be called at physical mode.\r | |
2454 | \r | |
2455 | Note: Since this is a special call, it does not follow the PAL\r | |
2456 | static register calling convention. GR28 contains the index of\r | |
2457 | PAL_ENTER_IA_32_ENV within the list of PAL procedures. All other\r | |
2458 | input arguments including GR29-GR31 are setup by SAL to values\r | |
2459 | as required by the IA-32 operating system defined in Table\r | |
2460 | 11-67. The registers that are designated as preserved, scratch,\r | |
2461 | input arguments and procedure return values by the static\r | |
2462 | procedure calling convention are not followed by this call. For\r | |
2463 | instance, GR5 and GR6 need not be preserved since these are\r | |
2464 | regarded as scratch by the IA-32 operating system. Note: In an\r | |
2465 | MP system, this call must be COMPLETED on the first CPU to enter\r | |
2466 | the IA-32 System Environment (may or may not be the BSP) prior\r | |
2467 | to being called on the remaining processors in the MP system.\r | |
2468 | \r | |
2469 | @param Index GR28 contains the index of the\r | |
2470 | PAL_ENTER_IA_32_ENV call within the list of PAL\r | |
2471 | procedures.\r | |
2472 | \r | |
2473 | \r | |
2474 | @retval The status is returned in GR4.\r | |
2475 | -1 - Un-implemented procedure 0 JMPE detected\r | |
2476 | at privilege level\r | |
2477 | \r | |
2478 | 0 - 1 SAL allocated buffer for IA-32 System\r | |
2479 | Environment operation is too small\r | |
2480 | \r | |
2481 | 2 - IA-32 Firmware Checksum Error\r | |
2482 | \r | |
2483 | 3 - SAL allocated buffer for IA-32 System\r | |
2484 | Environment operation is not properly aligned\r | |
2485 | \r | |
2486 | 4 - Error in SAL MP Info Table\r | |
2487 | \r | |
2488 | 5 - Error in SAL Memory Descriptor Table\r | |
2489 | \r | |
2490 | 6 - Error in SAL System Table\r | |
2491 | \r | |
2492 | 7 - Inconsistent IA-32 state\r | |
2493 | \r | |
2494 | 8 - IA-32 Firmware Internal Error\r | |
2495 | \r | |
2496 | 9 - IA-32 Soft Reset (Note: remaining register\r | |
2497 | state is undefined for this termination\r | |
2498 | reason)\r | |
2499 | \r | |
2500 | 10 - Machine Check Error\r | |
2501 | \r | |
2502 | 11 - Error in SAL I/O Intercept Table\r | |
2503 | \r | |
2504 | 12 - Processor exit due to other processor in\r | |
2505 | MP system terminating the IA32 system\r | |
2506 | environment. (Note: remaining register state\r | |
2507 | is undefined for this termination reason.)\r | |
2508 | \r | |
2509 | 13 - Itanium architecture-based state\r | |
2510 | corruption by either SAL PMI handler or I/O\r | |
2511 | Intercept callback function.\r | |
2512 | \r | |
2513 | \r | |
2514 | **/\r | |
2515 | #define PAL_ENTER_IA_32_ENV 33\r | |
2516 | \r | |
2517 | /**\r | |
2518 | PAL Procedure - PAL_PMI_ENTRYPOINT.\r | |
2519 | \r | |
2520 | Register PMI memory entrypoints with processor. It is required\r | |
1a2f870c | 2521 | by Itanium processors. The PAL procedure supports the Stacked Registers\r |
a7b64584 | 2522 | calling convention. It could be called at physical mode.\r |
2523 | \r | |
2524 | @param Index Index of PAL_PMI_ENTRYPOINT within the list of\r | |
2525 | PAL procedures.\r | |
2526 | @param SalPmiEntry 256-byte aligned physical address of SAL\r | |
2527 | PMI entrypoint in memory.\r | |
2528 | \r | |
2529 | @retval 0 Call completed without error\r | |
2530 | @retval -2 Invalid argument\r | |
2531 | @retval -3 Call completed with error.\r | |
2532 | \r | |
2533 | **/\r | |
2534 | #define PAL_PMI_ENTRYPOINT 32\r | |
2535 | \r | |
2536 | \r | |
2537 | /**\r | |
2538 | \r | |
2539 | The ASCII brand identification string will be copied to the\r | |
2540 | address specified in the address input argument. The processor\r | |
2541 | brand identification string is defined to be a maximum of 128\r | |
2542 | characters long; 127 bytes will contain characters and the 128th\r | |
2543 | byte is defined to be NULL (0). A processor may return less than\r | |
2544 | the 127 ASCII characters as long as the string is null\r | |
2545 | terminated. The string length will be placed in the brand_info\r | |
2546 | return argument.\r | |
2547 | \r | |
2548 | **/\r | |
2549 | #define PAL_BRAND_INFO_ID_REQUEST 0\r | |
2550 | \r | |
2551 | /**\r | |
2552 | PAL Procedure - PAL_BRAND_INFO.\r | |
2553 | \r | |
2554 | Provides processor branding information. It is optional by\r | |
1a2f870c | 2555 | Itanium processors. The PAL procedure supports the Stacked Registers calling\r |
a7b64584 | 2556 | convention. It could be called at physical and Virtual mode.\r |
2557 | \r | |
2558 | @param Index Index of PAL_BRAND_INFO within the list of PAL\r | |
2559 | procedures.\r | |
2560 | @param InfoRequest Unsigned 64-bit integer specifying the\r | |
2561 | information that is being requested. (See\r | |
2562 | PAL_BRAND_INFO_ID_REQUEST)\r | |
2563 | @param Address Unsigned 64-bit integer specifying the\r | |
2564 | address of the 128-byte block to which the\r | |
2565 | processor brand string shall be written.\r | |
2566 | \r | |
2567 | @retval 0 Call completed without error\r | |
2568 | @retval -1 Unimplemented procedure\r | |
2569 | @retval -2 Invalid argument\r | |
2570 | @retval -3 Call completed with error.\r | |
2571 | @retval -6 Input argument is not implemented.\r | |
2572 | \r | |
2573 | @return R9 Brand information returned. The format of this\r | |
2574 | value is dependent on the input values passed.\r | |
2575 | \r | |
2576 | **/\r | |
2577 | #define PAL_BRAND_INFO 274\r | |
2578 | \r | |
2579 | /**\r | |
2580 | PAL Procedure - PAL_GET_HW_POLICY.\r | |
2581 | \r | |
2582 | Returns the current hardware resource sharing policy of the\r | |
1a2f870c | 2583 | processor. It is optional by Itanium processors. The PAL procedure supports\r |
a7b64584 | 2584 | the Static Registers calling convention. It could be called at\r |
2585 | physical and Virtual mode.\r | |
2586 | \r | |
2587 | \r | |
2588 | @param Index Index of PAL_GET_HW_POLICY within the list of PAL\r | |
2589 | procedures.\r | |
2590 | @param ProcessorNumber Unsigned 64-bit integer that specifies\r | |
2591 | for which logical processor\r | |
2592 | information is being requested. This\r | |
2593 | input argument must be zero for the\r | |
2594 | first call to this procedure and can\r | |
2595 | be a maximum value of one less than\r | |
2596 | the number of logical processors\r | |
2597 | impacted by the hardware resource\r | |
2598 | sharing policy, which is returned by\r | |
2599 | the R10 return value.\r | |
2600 | \r | |
2601 | @retval 0 Call completed without error\r | |
2602 | @retval -1 Unimplemented procedure\r | |
2603 | @retval -2 Invalid argument\r | |
2604 | @retval -3 Call completed with error.\r | |
2605 | @retval -9 Call requires PAL memory buffer.\r | |
2606 | \r | |
2607 | @return R9 Unsigned 64-bit integer representing the current\r | |
2608 | hardware resource sharing policy.\r | |
2609 | @return R10 Unsigned 64-bit integer that returns the number\r | |
2610 | of logical processors impacted by the policy\r | |
2611 | input argument.\r | |
2612 | @return R11 Unsigned 64-bit integer containing the logical\r | |
2613 | address of one of the logical processors\r | |
2614 | impacted by policy modification.\r | |
2615 | \r | |
2616 | **/\r | |
2617 | #define PAL_GET_HW_POLICY 48\r | |
2618 | \r | |
2619 | \r | |
2620 | //\r | |
2621 | // Value of PAL_SET_HW_POLICY.Policy\r | |
2622 | //\r | |
2623 | #define PAL_SET_HW_POLICY_PERFORMANCE 0\r | |
2624 | #define PAL_SET_HW_POLICY_FAIRNESS 1\r | |
2625 | #define PAL_SET_HW_POLICY_HIGH_PRIORITY 2\r | |
2626 | #define PAL_SET_HW_POLICY_EXCLUSIVE_HIGH_PRIORITY 3\r | |
2627 | \r | |
2628 | /**\r | |
2629 | PAL Procedure - PAL_SET_HW_POLICY.\r | |
2630 | \r | |
2631 | Sets the current hardware resource sharing policy of the\r | |
1a2f870c | 2632 | processor. It is optional by Itanium processors. The PAL procedure supports\r |
a7b64584 | 2633 | the Static Registers calling convention. It could be called at\r |
2634 | physical and Virtual mode.\r | |
2635 | \r | |
2636 | @param Index Index of PAL_SET_HW_POLICY within the list of PAL\r | |
2637 | procedures.\r | |
2638 | @param Policy Unsigned 64-bit integer specifying the hardware\r | |
2639 | resource sharing policy the caller is setting.\r | |
2640 | See Value of PAL_SET_HW_POLICY.Policy above.\r | |
2641 | \r | |
2642 | @retval 1 Call completed successfully but could not\r | |
2643 | change the hardware policy since a\r | |
2644 | competing logical processor is set in\r | |
2645 | exclusive high priority.\r | |
2646 | @retval 0 Call completed without error\r | |
2647 | @retval -1 Unimplemented procedure\r | |
2648 | @retval -2 Invalid argument\r | |
2649 | @retval -3 Call completed with error.\r | |
2650 | @retval -9 Call requires PAL memory buffer.\r | |
2651 | \r | |
2652 | **/\r | |
2653 | #define PAL_SET_HW_POLICY 49\r | |
2654 | \r | |
a7b64584 | 2655 | typedef struct {\r |
992f22b9 LG |
2656 | UINT64 Mode:3; ///< Bit2:0, Indicates the mode of operation for this\r |
2657 | ///< procedure: 0 - Query mode 1 - Error inject mode\r | |
2658 | ///< (err_inj should also be specified) 2 - Cancel\r | |
2659 | ///< outstanding trigger. All other fields in\r | |
2660 | ///< PAL_MC_ERROR_TYPE_INFO,\r | |
2661 | ///< PAL_MC_ERROR_STRUCTURE_INFO and\r | |
2662 | ///< PAL_MC_ERROR_DATA_BUFFER are ignored. All other\r | |
2663 | ///< values are reserved.\r | |
2664 | \r | |
2665 | UINT64 ErrorInjection:3; ///< Bit5:3, indicates the mode of error\r | |
2666 | ///< injection: 0 - Error inject only (no\r | |
2667 | ///< error consumption) 1 - Error inject\r | |
2668 | ///< and consume All other values are\r | |
2669 | ///< reserved.\r | |
2670 | \r | |
2671 | UINT64 ErrorSeverity:2; ///< Bit7:6, indicates the severity desired\r | |
2672 | ///< for error injection/query. Definitions\r | |
2673 | ///< of the different error severity types\r | |
2674 | ///< 0 - Corrected error 1 - Recoverable\r | |
2675 | ///< error 2 - Fatal error 3 - Reserved\r | |
2676 | \r | |
2677 | UINT64 ErrorStructure:5; ///< Bit12:8, Indicates the structure\r | |
2678 | ///< identification for error\r | |
2679 | ///< injection/query: 0 - Any structure\r | |
2680 | ///< (cannot be used during query mode).\r | |
2681 | ///< When selected, the structure type used\r | |
2682 | ///< for error injection is determined by\r | |
2683 | ///< PAL. 1 - Cache 2 - TLB 3 - Register\r | |
2684 | ///< file 4 - Bus/System interconnect 5-15\r | |
2685 | ///< - Reserved 16-31 - Processor\r | |
2686 | ///< specific error injection\r | |
2687 | ///< capabilities.ErrorDataBuffer is used\r | |
2688 | ///< to specify error types. Please refer\r | |
2689 | ///< to the processor specific\r | |
2690 | ///< documentation for additional details.\r | |
2691 | \r | |
2692 | UINT64 StructureHierarchy:3; ///< Bit15:13, Indicates the structure\r | |
2693 | ///< hierarchy for error\r | |
2694 | ///< injection/query: 0 - Any level of\r | |
2695 | ///< hierarchy (cannot be used during\r | |
2696 | ///< query mode). When selected, the\r | |
2697 | ///< structure hierarchy used for error\r | |
2698 | ///< injection is determined by PAL. 1\r | |
2699 | ///< - Error structure hierarchy\r | |
2700 | ///< level-1 2 - Error structure\r | |
2701 | ///< hierarchy level-2 3 - Error\r | |
2702 | ///< structure hierarchy level-3 4 -\r | |
2703 | ///< Error structure hierarchy level-4\r | |
2704 | ///< All other values are reserved.\r | |
7e6a7a63 | 2705 | \r |
e2a5ae07 | 2706 | UINT64 Reserved:32; ///< Reserved 47:16 Reserved\r |
2707 | \r | |
2708 | UINT64 ImplSpec:16; ///< Bit63:48, Processor specific error injection capabilities.\r | |
a7b64584 | 2709 | } PAL_MC_ERROR_TYPE_INFO;\r |
2710 | \r | |
7e6a7a63 | 2711 | typedef struct {\r |
992f22b9 LG |
2712 | UINT64 StructInfoIsValid:1; ///< Bit0 When 1, indicates that the\r |
2713 | ///< structure information fields\r | |
2714 | ///< (c_t,cl_p,cl_id) are valid and\r | |
2715 | ///< should be used for error injection.\r | |
2716 | ///< When 0, the structure information\r | |
2717 | ///< fields are ignored, and the values\r | |
2718 | ///< of these fields used for error\r | |
2719 | ///< injection are\r | |
2720 | ///< implementation-specific.\r | |
2721 | \r | |
2722 | UINT64 CacheType:2; ///< Bit2:1 Indicates which cache should be used\r | |
2723 | ///< for error injection: 0 - Reserved 1 -\r | |
2724 | ///< Instruction cache 2 - Data or unified cache\r | |
2725 | ///< 3 - Reserved\r | |
2726 | \r | |
2727 | UINT64 PortionOfCacheLine:3; ///< Bit5:3 Indicates the portion of the\r | |
2728 | ///< cache line where the error should\r | |
2729 | ///< be injected: 0 - Reserved 1 - Tag\r | |
2730 | ///< 2 - Data 3 - mesi All other\r | |
2731 | ///< values are reserved.\r | |
2732 | \r | |
2733 | UINT64 Mechanism:3; ///< Bit8:6 Indicates which mechanism is used to\r | |
2734 | ///< identify the cache line to be used for error\r | |
2735 | ///< injection: 0 - Reserved 1 - Virtual address\r | |
2736 | ///< provided in the inj_addr field of the buffer\r | |
2737 | ///< pointed to by err_data_buffer should be used\r | |
2738 | ///< to identify the cache line for error\r | |
2739 | ///< injection. 2 - Physical address provided in\r | |
2740 | ///< the inj_addr field of the buffer pointed to\r | |
2741 | ///< by err_data_buffershould be used to identify\r | |
2742 | ///< the cache line for error injection. 3 - way\r | |
2743 | ///< and index fields provided in err_data_buffer\r | |
2744 | ///< should be used to identify the cache line\r | |
2745 | ///< for error injection. All other values are\r | |
2746 | ///< reserved.\r | |
2747 | \r | |
2748 | UINT64 DataPoisonOfCacheLine:1; ///< Bit9 When 1, indicates that a\r | |
2749 | ///< multiple bit, non-correctable\r | |
2750 | ///< error should be injected in the\r | |
2751 | ///< cache line specified by cl_id.\r | |
2752 | ///< If this injected error is not\r | |
2753 | ///< consumed, it may eventually\r | |
2754 | ///< cause a data-poisoning event\r | |
2755 | ///< resulting in a corrected error\r | |
2756 | ///< signal, when the associated\r | |
2757 | ///< cache line is cast out (implicit\r | |
2758 | ///< or explicit write-back of the\r | |
2759 | ///< cache line). The error severity\r | |
2760 | ///< specified by err_sev in\r | |
2761 | ///< err_type_info must be set to 0\r | |
2762 | ///< (corrected error) when this bit\r | |
2763 | ///< is set.\r | |
a7b64584 | 2764 | \r |
7e6a7a63 | 2765 | UINT64 Reserved1:22;\r |
a7b64584 | 2766 | \r |
992f22b9 LG |
2767 | UINT64 TrigerInfoIsValid:1; ///< Bit32 When 1, indicates that the\r |
2768 | ///< trigger information fields (trigger,\r | |
2769 | ///< trigger_pl) are valid and should be\r | |
2770 | ///< used for error injection. When 0,\r | |
2771 | ///< the trigger information fields are\r | |
2772 | ///< ignored and error injection is\r | |
2773 | ///< performed immediately.\r | |
2774 | \r | |
2775 | UINT64 Triger:4; ///< Bit36:33 Indicates the operation type to be\r | |
2776 | ///< used as the error trigger condition. The\r | |
2777 | ///< address corresponding to the trigger is\r | |
2778 | ///< specified in the trigger_addr field of the\r | |
2779 | ///< buffer pointed to by err_data_buffer: 0 -\r | |
2780 | ///< Instruction memory access. The trigger match\r | |
2781 | ///< conditions for this operation type are similar\r | |
2782 | ///< to the IBR address breakpoint match conditions\r | |
2783 | ///< 1 - Data memory access. The trigger match\r | |
2784 | ///< conditions for this operation type are similar\r | |
2785 | ///< to the DBR address breakpoint match conditions\r | |
2786 | ///< All other values are reserved.\r | |
2787 | \r | |
2788 | UINT64 PrivilegeOfTriger:3; ///< Bit39:37 Indicates the privilege\r | |
2789 | ///< level of the context during which\r | |
2790 | ///< the error should be injected: 0 -\r | |
2791 | ///< privilege level 0 1 - privilege\r | |
2792 | ///< level 1 2 - privilege level 2 3 -\r | |
2793 | ///< privilege level 3 All other values\r | |
2794 | ///< are reserved. If the implementation\r | |
2795 | ///< does not support privilege level\r | |
2796 | ///< qualifier for triggers (i.e. if\r | |
2797 | ///< trigger_pl is 0 in the capabilities\r | |
2798 | ///< vector), this field is ignored and\r | |
2799 | ///< triggers can be taken at any\r | |
2800 | ///< privilege level.\r | |
a7b64584 | 2801 | \r |
a7b64584 | 2802 | UINT64 Reserved2:24;\r |
2803 | } PAL_MC_ERROR_STRUCT_INFO;\r | |
2804 | \r | |
2805 | /**\r | |
2806 | \r | |
2807 | Buffer Pointed to by err_data_buffer - TLB\r | |
2808 | \r | |
2809 | **/\r | |
2810 | typedef struct {\r | |
2811 | UINT64 TrigerAddress;\r | |
2812 | UINT64 VirtualPageNumber:52;\r | |
2813 | UINT64 Reserved1:8;\r | |
2814 | UINT64 RegionId:24;\r | |
2815 | UINT64 Reserved2:40;\r | |
2816 | } PAL_MC_ERROR_DATA_BUFFER_TLB;\r | |
2817 | \r | |
2818 | /**\r | |
2819 | PAL Procedure - PAL_MC_ERROR_INJECT.\r | |
2820 | \r | |
2821 | Injects the requested processor error or returns information\r | |
2822 | on the supported injection capabilities for this particular\r | |
1a2f870c | 2823 | processor implementation. It is optional by Itanium processors. The PAL\r |
a7b64584 | 2824 | procedure supports the Stacked Registers calling convention.\r |
2825 | It could be called at physical and Virtual mode.\r | |
2826 | \r | |
2827 | @param Index Index of PAL_MC_ERROR_INJECT within the list of PAL\r | |
2828 | procedures.\r | |
2829 | @param ErrorTypeInfo Unsigned 64-bit integer specifying the\r | |
2830 | first level error information which\r | |
2831 | identifies the error structure and\r | |
2832 | corresponding structure hierarchy, and\r | |
2833 | the error severity.\r | |
2834 | @param ErrorStructInfo Unsigned 64-bit integer identifying\r | |
2835 | the optional structure specific\r | |
2836 | information that provides the second\r | |
2837 | level details for the requested error.\r | |
2838 | @param ErrorDataBuffer 64-bit physical address of a buffer\r | |
2839 | providing additional parameters for\r | |
2840 | the requested error. The address of\r | |
2841 | this buffer must be 8-byte aligned.\r | |
2842 | \r | |
2843 | @retval 0 Call completed without error\r | |
2844 | @retval -1 Unimplemented procedure\r | |
2845 | @retval -2 Invalid argument\r | |
2846 | @retval -3 Call completed with error.\r | |
2847 | @retval -4 Call completed with error; the requested\r | |
2848 | error could not be injected due to failure in\r | |
2849 | locating the target location in the specified\r | |
2850 | structure.\r | |
2851 | @retval -5 Argument was valid, but requested error\r | |
2852 | injection capability is not supported.\r | |
2853 | @retval -9 Call requires PAL memory buffer.\r | |
2854 | \r | |
2855 | @return R9 64-bit vector specifying the supported error\r | |
2856 | injection capabilities for the input argument\r | |
2857 | combination of struct_hier, err_struct and\r | |
2858 | err_sev fields in ErrorTypeInfo.\r | |
2859 | @return R10 64-bit vector specifying the architectural\r | |
2860 | resources that are used by the procedure.\r | |
2861 | \r | |
2862 | **/\r | |
2863 | #define PAL_MC_ERROR_INJECT 276\r | |
2864 | \r | |
2865 | \r | |
2866 | //\r | |
2867 | // Types of PAL_GET_PSTATE.Type\r | |
2868 | //\r | |
2869 | #define PAL_GET_PSTATE_RECENT 0\r | |
2870 | #define PAL_GET_PSTATE_AVERAGE_NEW_START 1\r | |
2871 | #define PAL_GET_PSTATE_AVERAGE 2\r | |
2872 | #define PAL_GET_PSTATE_NOW 3\r | |
2873 | \r | |
2874 | /**\r | |
2875 | PAL Procedure - PAL_GET_PSTATE.\r | |
2876 | \r | |
2877 | Returns the performance index of the processor. It is optional\r | |
1a2f870c | 2878 | by Itanium processors. The PAL procedure supports the Stacked Registers\r |
a7b64584 | 2879 | calling convention. It could be called at physical and Virtual\r |
2880 | mode.\r | |
2881 | \r | |
2882 | @param Index Index of PAL_GET_PSTATE within the list of PAL\r | |
2883 | procedures.\r | |
2884 | @param Type Type of performance_index value to be returned\r | |
2885 | by this procedure.See PAL_GET_PSTATE.Type above.\r | |
2886 | \r | |
2887 | @retval 1 Call completed without error, but accuracy\r | |
2888 | of performance index has been impacted by a\r | |
2889 | thermal throttling event, or a\r | |
2890 | hardware-initiated event.\r | |
2891 | @retval 0 Call completed without error\r | |
2892 | @retval -1 Unimplemented procedure\r | |
2893 | @retval -2 Invalid argument\r | |
2894 | @retval -3 Call completed with error.\r | |
2895 | @retval -9 Call requires PAL memory buffer.\r | |
2896 | \r | |
2897 | @return R9 Unsigned integer denoting the processor\r | |
2898 | performance for the time duration since the last\r | |
2899 | PAL_GET_PSTATE procedure call was made. The\r | |
2900 | value returned is between 0 and 100, and is\r | |
2901 | relative to the performance index of the highest\r | |
2902 | available P-state.\r | |
2903 | \r | |
2904 | **/\r | |
2905 | #define PAL_GET_PSTATE 262\r | |
2906 | \r | |
2907 | /**\r | |
2908 | \r | |
2909 | Layout of PAL_PSTATE_INFO.PStateBuffer\r | |
2910 | \r | |
2911 | **/\r | |
2912 | typedef struct {\r | |
2913 | UINT32 PerformanceIndex:7;\r | |
2914 | UINT32 Reserved1:5;\r | |
2915 | UINT32 TypicalPowerDissipation:20;\r | |
2916 | UINT32 TransitionLatency1;\r | |
2917 | UINT32 TransitionLatency2;\r | |
2918 | UINT32 Reserved2;\r | |
2919 | } PAL_PSTATE_INFO_BUFFER;\r | |
2920 | \r | |
2921 | \r | |
2922 | /**\r | |
2923 | PAL Procedure - PAL_PSTATE_INFO.\r | |
2924 | \r | |
2925 | Returns information about the P-states supported by the\r | |
1a2f870c | 2926 | processor. It is optional by Itanium processors. The PAL procedure supports\r |
a7b64584 | 2927 | the Static Registers calling convention. It could be called\r |
2928 | at physical and Virtual mode.\r | |
2929 | \r | |
2930 | @param Index Index of PAL_PSTATE_INFO within the list of PAL\r | |
2931 | procedures.\r | |
2932 | @param PStateBuffer 64-bit pointer to a 256-byte buffer\r | |
2933 | aligned on an 8-byte boundary. See\r | |
2934 | PAL_PSTATE_INFO_BUFFER above.\r | |
2935 | \r | |
2936 | @retval 0 Call completed without error\r | |
2937 | @retval -1 Unimplemented procedure\r | |
2938 | @retval -2 Invalid argument\r | |
2939 | @retval -3 Call completed with error.\r | |
2940 | \r | |
2941 | @return R9 Unsigned integer denoting the number of P-states\r | |
2942 | supported. The maximum value of this field is 16.\r | |
2943 | @return R10 Dependency domain information\r | |
2944 | \r | |
2945 | **/\r | |
2946 | #define PAL_PSTATE_INFO 44\r | |
2947 | \r | |
2948 | \r | |
2949 | /**\r | |
2950 | PAL Procedure - PAL_SET_PSTATE.\r | |
2951 | \r | |
2952 | To request a processor transition to a given P-state. It is\r | |
1a2f870c | 2953 | optional by Itanium processors. The PAL procedure supports the Stacked\r |
a7b64584 | 2954 | Registers calling convention. It could be called at physical\r |
2955 | and Virtual mode.\r | |
2956 | \r | |
2957 | @param Index Index of PAL_SET_PSTATE within the list of PAL\r | |
2958 | procedures.\r | |
2959 | @param PState Unsigned integer denoting the processor\r | |
2960 | P-state being requested.\r | |
2961 | @param ForcePState Unsigned integer denoting whether the\r | |
2962 | P-state change should be forced for the\r | |
2963 | logical processor.\r | |
2964 | \r | |
2965 | @retval 1 Call completed without error, but\r | |
2966 | transition request was not accepted\r | |
2967 | @retval 0 Call completed without error\r | |
2968 | @retval -1 Unimplemented procedure\r | |
2969 | @retval -2 Invalid argument\r | |
2970 | @retval -3 Call completed with error.\r | |
2971 | @retval -9 Call requires PAL memory buffer.\r | |
2972 | \r | |
2973 | **/\r | |
2974 | #define PAL_SET_PSTATE 263\r | |
2975 | \r | |
2976 | /**\r | |
2977 | PAL Procedure - PAL_SHUTDOWN.\r | |
2978 | \r | |
2979 | Put the logical processor into a low power state which can be\r | |
1a2f870c | 2980 | exited only by a reset event. It is optional by Itanium processors. The PAL\r |
a7b64584 | 2981 | procedure supports the Static Registers calling convention. It\r |
2982 | could be called at physical mode.\r | |
2983 | \r | |
2984 | @param Index Index of PAL_SHUTDOWN within the list of PAL\r | |
2985 | procedures.\r | |
2986 | @param NotifyPlatform 8-byte aligned physical address\r | |
2987 | pointer providing details on how to\r | |
2988 | optionally notify the platform that\r | |
2989 | the processor is entering a shutdown\r | |
2990 | state.\r | |
2991 | \r | |
2992 | @retval -1 Unimplemented procedure\r | |
2993 | @retval -2 Invalid argument\r | |
2994 | @retval -3 Call completed with error.\r | |
2995 | @retval -9 Call requires PAL memory buffer.\r | |
2996 | \r | |
2997 | **/\r | |
2998 | #define PAL_SHUTDOWN 45\r | |
2999 | \r | |
3000 | /**\r | |
3001 | \r | |
3002 | Layout of PAL_MEMORY_BUFFER.ControlWord\r | |
3003 | \r | |
3004 | **/\r | |
3005 | typedef struct {\r | |
3006 | UINT64 Registration:1;\r | |
3007 | UINT64 ProbeInterrupt:1;\r | |
3008 | UINT64 Reserved:62;\r | |
3009 | } PAL_MEMORY_CONTROL_WORD;\r | |
3010 | \r | |
3011 | /**\r | |
3012 | PAL Procedure - PAL_MEMORY_BUFFER.\r | |
3013 | \r | |
3014 | Provides cacheable memory to PAL for exclusive use during\r | |
1a2f870c | 3015 | runtime. It is optional by Itanium processors. The PAL procedure supports the\r |
a7b64584 | 3016 | Static Registers calling convention. It could be called at\r |
3017 | physical mode.\r | |
3018 | \r | |
3019 | @param Index Index of PAL_MEMORY_BUFFER within the list of PAL\r | |
3020 | procedures.\r | |
3021 | @param BaseAddress Physical address of the memory buffer\r | |
3022 | allocated for PAL use.\r | |
3023 | @param AllocSize Unsigned integer denoting the size of the\r | |
3024 | memory buffer.\r | |
3025 | @param ControlWord Formatted bit vector that provides control\r | |
3026 | options for this procedure. See\r | |
3027 | PAL_MEMORY_CONTROL_WORD above.\r | |
3028 | \r | |
3029 | @retval 1 Call has not completed a buffer relocation\r | |
3030 | due to a pending interrupt\r | |
3031 | @retval 0 Call completed without error\r | |
3032 | @retval -1 Unimplemented procedure\r | |
3033 | @retval -2 Invalid argument\r | |
3034 | @retval -3 Call completed with error.\r | |
3035 | @retval -9 Call requires PAL memory buffer.\r | |
3036 | \r | |
3037 | @return R9 Returns the minimum size of the memory buffer\r | |
3038 | required if the alloc_size input argument was\r | |
3039 | not large enough.\r | |
3040 | \r | |
3041 | **/\r | |
3042 | #define PAL_MEMORY_BUFFER 277\r | |
3043 | \r | |
3044 | \r | |
3045 | /**\r | |
3046 | PAL Procedure - PAL_VP_CREATE.\r | |
3047 | \r | |
3048 | Initializes a new vpd for the operation of a new virtual\r | |
1a2f870c | 3049 | processor in the virtual environment. It is optional by Itanium processors.\r |
a7b64584 | 3050 | The PAL procedure supports the Stacked Registers calling\r |
3051 | convention. It could be called at Virtual mode.\r | |
3052 | \r | |
3053 | @param Index Index of PAL_VP_CREATE within the list of PAL\r | |
3054 | procedures.\r | |
3055 | @param Vpd 64-bit host virtual pointer to the Virtual\r | |
3056 | Processor Descriptor (VPD).\r | |
3057 | @param HostIva 64-bit host virtual pointer to the host IVT\r | |
3058 | for the virtual processor\r | |
3059 | @param OptionalHandler 64-bit non-zero host-virtual pointer\r | |
3060 | to an optional handler for\r | |
3061 | virtualization intercepts.\r | |
3062 | \r | |
3063 | @retval 0 Call completed without error\r | |
3064 | @retval -1 Unimplemented procedure\r | |
3065 | @retval -2 Invalid argument\r | |
3066 | @retval -3 Call completed with error.\r | |
3067 | @retval -9 Call requires PAL memory buffer.\r | |
3068 | \r | |
3069 | **/\r | |
3070 | #define PAL_VP_CREATE 265\r | |
3071 | \r | |
3072 | /**\r | |
3073 | \r | |
3074 | Virtual Environment Information Parameter\r | |
3075 | \r | |
3076 | **/\r | |
3077 | typedef struct {\r | |
3078 | UINT64 Reserved1:8;\r | |
3079 | UINT64 Opcode:1;\r | |
3080 | UINT64 Reserved:53;\r | |
3081 | } PAL_VP_ENV_INFO_RETURN;\r | |
3082 | \r | |
3083 | /**\r | |
3084 | PAL Procedure - PAL_VP_ENV_INFO.\r | |
3085 | \r | |
3086 | Returns the parameters needed to enter a virtual environment.\r | |
1a2f870c | 3087 | It is optional by Itanium processors. The PAL procedure supports the Stacked\r |
a7b64584 | 3088 | Registers calling convention. It could be called at Virtual\r |
3089 | mode.\r | |
3090 | \r | |
3091 | @param Index Index of PAL_VP_ENV_INFO within the list of PAL\r | |
3092 | procedures.\r | |
3093 | @param Vpd 64-bit host virtual pointer to the Virtual\r | |
3094 | Processor Descriptor (VPD).\r | |
3095 | @param HostIva 64-bit host virtual pointer to the host IVT\r | |
3096 | for the virtual processor\r | |
3097 | @param OptionalHandler 64-bit non-zero host-virtual pointer\r | |
3098 | to an optional handler for\r | |
3099 | virtualization intercepts.\r | |
3100 | \r | |
3101 | @retval 0 Call completed without error\r | |
3102 | @retval -1 Unimplemented procedure\r | |
3103 | @retval -2 Invalid argument\r | |
3104 | @retval -3 Call completed with error.\r | |
3105 | @retval -9 Call requires PAL memory buffer.\r | |
3106 | \r | |
3107 | @return R9 Unsigned integer denoting the number of bytes\r | |
3108 | required by the PAL virtual environment buffer\r | |
3109 | during PAL_VP_INIT_ENV\r | |
3110 | @return R10 64-bit vector of virtual environment\r | |
3111 | information. See PAL_VP_ENV_INFO_RETURN.\r | |
3112 | \r | |
3113 | \r | |
3114 | **/\r | |
3115 | #define PAL_VP_ENV_INFO 266\r | |
3116 | \r | |
3117 | /**\r | |
3118 | PAL Procedure - PAL_VP_EXIT_ENV.\r | |
3119 | \r | |
3120 | Allows a logical processor to exit a virtual environment.\r | |
1a2f870c | 3121 | It is optional by Itanium processors. The PAL procedure supports the Stacked\r |
a7b64584 | 3122 | Registers calling convention. It could be called at Virtual\r |
3123 | mode.\r | |
3124 | \r | |
3125 | @param Index Index of PAL_VP_EXIT_ENV within the list of PAL\r | |
3126 | procedures.\r | |
3127 | @param Iva Optional 64-bit host virtual pointer to the IVT\r | |
3128 | when this procedure is done\r | |
3129 | \r | |
3130 | @retval 0 Call completed without error\r | |
3131 | @retval -1 Unimplemented procedure\r | |
3132 | @retval -2 Invalid argument\r | |
3133 | @retval -3 Call completed with error.\r | |
3134 | @retval -9 Call requires PAL memory buffer.\r | |
3135 | \r | |
3136 | **/\r | |
3137 | #define PAL_VP_EXIT_ENV 267\r | |
3138 | \r | |
3139 | \r | |
3140 | \r | |
3141 | /**\r | |
3142 | PAL Procedure - PAL_VP_INIT_ENV.\r | |
3143 | \r | |
3144 | Allows a logical processor to enter a virtual environment. It\r | |
1a2f870c | 3145 | is optional by Itanium processors. The PAL procedure supports the Stacked\r |
a7b64584 | 3146 | Registers calling convention. It could be called at Virtual\r |
3147 | mode.\r | |
3148 | \r | |
3149 | @param Index Index of PAL_VP_INIT_ENV within the list of PAL\r | |
3150 | procedures.\r | |
3151 | @param ConfigOptions 64-bit vector of global configuration\r | |
3152 | settings.\r | |
3153 | @param PhysicalBase Host physical base address of a block of\r | |
3154 | contiguous physical memory for the PAL\r | |
3155 | virtual environment buffer 1) This\r | |
3156 | memory area must be allocated by the VMM\r | |
3157 | and be 4K aligned. The first logical\r | |
3158 | processor to enter the environment will\r | |
3159 | initialize the physical block for\r | |
3160 | virtualization operations.\r | |
3161 | @param VirtualBase Host virtual base address of the\r | |
3162 | corresponding physical memory block for\r | |
3163 | the PAL virtual environment buffer : The\r | |
3164 | VMM must maintain the host virtual to host\r | |
3165 | physical data and instruction translations\r | |
3166 | in TRs for addresses within the allocated\r | |
3167 | address space. Logical processors in this\r | |
3168 | virtual environment will use this address\r | |
3169 | when transitioning to virtual mode\r | |
3170 | operations.\r | |
3171 | \r | |
3172 | @retval 0 Call completed without error\r | |
3173 | @retval -1 Unimplemented procedure\r | |
3174 | @retval -2 Invalid argument\r | |
3175 | @retval -3 Call completed with error.\r | |
3176 | @retval -9 Call requires PAL memory buffer.\r | |
3177 | \r | |
3178 | @return R9 Virtualization Service Address - VSA specifies\r | |
3179 | the virtual base address of the PAL\r | |
3180 | virtualization services in this virtual\r | |
3181 | environment.\r | |
3182 | \r | |
3183 | \r | |
3184 | **/\r | |
3185 | #define PAL_VP_INIT_ENV 268\r | |
3186 | \r | |
3187 | \r | |
3188 | /**\r | |
3189 | PAL Procedure - PAL_VP_REGISTER.\r | |
3190 | \r | |
3191 | Register a different host IVT and/or a different optional\r | |
3192 | virtualization intercept handler for the virtual processor\r | |
1a2f870c | 3193 | specified by vpd. It is optional by Itanium processors. The PAL procedure\r |
a7b64584 | 3194 | supports the Stacked Registers calling convention. It could be\r |
3195 | called at Virtual mode.\r | |
3196 | \r | |
3197 | @param Index Index of PAL_VP_REGISTER within the list of PAL\r | |
3198 | procedures.\r | |
3199 | @param Vpd 64-bit host virtual pointer to the Virtual\r | |
3200 | Processor Descriptor (VPD) host_iva 64-bit host\r | |
3201 | virtual pointer to the host IVT for the virtual\r | |
3202 | processor\r | |
3203 | @param OptionalHandler 64-bit non-zero host-virtual pointer\r | |
3204 | to an optional handler for\r | |
3205 | virtualization intercepts.\r | |
3206 | \r | |
3207 | @retval 0 Call completed without error\r | |
3208 | @retval -1 Unimplemented procedure\r | |
3209 | @retval -2 Invalid argument\r | |
3210 | @retval -3 Call completed with error.\r | |
3211 | @retval -9 Call requires PAL memory buffer.\r | |
3212 | \r | |
3213 | **/\r | |
3214 | #define PAL_VP_REGISTER 269\r | |
3215 | \r | |
3216 | \r | |
3217 | /**\r | |
3218 | PAL Procedure - PAL_VP_RESTORE.\r | |
3219 | \r | |
3220 | Restores virtual processor state for the specified vpd on the\r | |
1a2f870c | 3221 | logical processor. It is optional by Itanium processors. The PAL procedure\r |
a7b64584 | 3222 | supports the Stacked Registers calling convention. It could be\r |
3223 | called at Virtual mode.\r | |
3224 | \r | |
3225 | @param Index Index of PAL_VP_RESTORE within the list of PAL\r | |
3226 | procedures.\r | |
3227 | @param Vpd 64-bit host virtual pointer to the Virtual\r | |
3228 | Processor Descriptor (VPD) host_iva 64-bit host\r | |
3229 | virtual pointer to the host IVT for the virtual\r | |
3230 | processor\r | |
3231 | @param PalVector Vector specifies PAL procedure\r | |
3232 | implementation-specific state to be\r | |
3233 | restored.\r | |
3234 | \r | |
3235 | @retval 0 Call completed without error\r | |
3236 | @retval -1 Unimplemented procedure\r | |
3237 | @retval -2 Invalid argument\r | |
3238 | @retval -3 Call completed with error.\r | |
3239 | @retval -9 Call requires PAL memory buffer.\r | |
3240 | \r | |
3241 | **/\r | |
3242 | #define PAL_VP_RESTORE 270\r | |
3243 | \r | |
3244 | /**\r | |
3245 | PAL Procedure - PAL_VP_SAVE.\r | |
3246 | \r | |
3247 | Saves virtual processor state for the specified vpd on the\r | |
1a2f870c | 3248 | logical processor. It is optional by Itanium processors. The PAL procedure\r |
a7b64584 | 3249 | supports the Stacked Registers calling convention. It could be\r |
3250 | called at Virtual mode.\r | |
3251 | \r | |
3252 | @param Index Index of PAL_VP_SAVE within the list of PAL\r | |
3253 | procedures.\r | |
3254 | @param Vpd 64-bit host virtual pointer to the Virtual\r | |
3255 | Processor Descriptor (VPD) host_iva 64-bit host\r | |
3256 | virtual pointer to the host IVT for the virtual\r | |
3257 | processor\r | |
3258 | @param PalVector Vector specifies PAL procedure\r | |
3259 | implementation-specific state to be\r | |
3260 | restored.\r | |
3261 | \r | |
3262 | @retval 0 Call completed without error\r | |
3263 | @retval -1 Unimplemented procedure\r | |
3264 | @retval -2 Invalid argument\r | |
3265 | @retval -3 Call completed with error.\r | |
3266 | @retval -9 Call requires PAL memory buffer.\r | |
3267 | \r | |
3268 | **/\r | |
3269 | #define PAL_VP_SAVE 271\r | |
3270 | \r | |
3271 | \r | |
3272 | /**\r | |
3273 | PAL Procedure - PAL_VP_TERMINATE.\r | |
3274 | \r | |
3275 | Terminates operation for the specified virtual processor. It\r | |
1a2f870c | 3276 | is optional by Itanium processors. The PAL procedure supports the Stacked\r |
a7b64584 | 3277 | Registers calling convention. It could be called at Virtual\r |
3278 | mode.\r | |
3279 | \r | |
3280 | @param Index Index of PAL_VP_TERMINATE within the list of PAL\r | |
3281 | procedures.\r | |
3282 | @param Vpd 64-bit host virtual pointer to the Virtual\r | |
3283 | Processor Descriptor (VPD)\r | |
3284 | @param Iva Optional 64-bit host virtual pointer to the IVT\r | |
3285 | when this procedure is done.\r | |
3286 | \r | |
3287 | @retval 0 Call completed without error\r | |
3288 | @retval -1 Unimplemented procedure\r | |
3289 | @retval -2 Invalid argument\r | |
3290 | @retval -3 Call completed with error.\r | |
3291 | @retval -9 Call requires PAL memory buffer.\r | |
3292 | \r | |
3293 | **/\r | |
3294 | #define PAL_VP_TERMINATE 272\r | |
3295 | \r | |
3296 | #endif\r |