projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| a7ed1e2e | 1 | /** @file\r |
| 2 | Support for PCI 3.0 standard.\r | |
| 3 | \r | |
| 98642032 | 4 | Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r |
| 9df063a0 | 5 | This program and the accompanying materials \r |
| a7ed1e2e | 6 | are licensed and made available under the terms and conditions of the BSD License \r |
| 7 | which accompanies this distribution. The full text of the license may be found at \r | |
| 8 | http://opensource.org/licenses/bsd-license.php \r | |
| 9 | \r | |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
| 12 | \r | |
| a7ed1e2e | 13 | **/\r |
| 14 | \r | |
| 842f5579 A |
15 | #ifndef __PCI30_H__\r |
| 16 | #define __PCI30_H__\r | |
| a7ed1e2e | 17 | \r |
| bc14bdb3 | 18 | \r |
| 19 | #include <IndustryStandard/Pci23.h>\r | |
| 20 | \r | |
| 21 | ///\r | |
| 22 | /// Definitions of PCI class bytes and manipulation macros.\r | |
| 23 | ///\r | |
| a7ed1e2e | 24 | #define PCI_CLASS_MASS_STORAGE_SATADPA 0x06\r |
| bc14bdb3 | 25 | #define PCI_IF_MASS_STORAGE_SATA 0x00\r |
| 26 | #define PCI_IF_MASS_STORAGE_AHCI 0x01\r | |
| 27 | \r | |
| 98642032 | 28 | /** \r |
| 29 | Macro that checks whether device is a SATA controller.\r | |
| 30 | \r | |
| 31 | @param _p Specified device.\r | |
| 32 | \r | |
| 33 | @retval TRUE Device is a SATA controller.\r | |
| 34 | @retval FALSE Device is not a SATA controller.\r | |
| 35 | \r | |
| 36 | **/\r | |
| 37 | #define IS_PCI_SATADPA(_p) IS_CLASS2 (_p, PCI_CLASS_MASS_STORAGE, PCI_CLASS_MASS_STORAGE_SATADPA)\r | |
| 38 | \r | |
| bc14bdb3 | 39 | ///\r |
| 40 | /// PCI Capability List IDs and records\r | |
| 41 | ///\r | |
| 42 | #define EFI_PCI_CAPABILITY_ID_PCIEXP 0x10\r | |
| a7ed1e2e | 43 | \r |
| 766f4bc1 | 44 | #pragma pack(1)\r |
| 45 | \r | |
| bc14bdb3 | 46 | ///\r |
| 427987f5 | 47 | /// PCI Data Structure Format\r |
| 48 | /// Section 5.1.2, PCI Firmware Specification, Revision 3.0\r | |
| bc14bdb3 | 49 | ///\r |
| a7ed1e2e | 50 | typedef struct {\r |
| bc14bdb3 | 51 | UINT32 Signature; ///< "PCIR"\r |
| a7ed1e2e | 52 | UINT16 VendorId;\r |
| 53 | UINT16 DeviceId;\r | |
| 54 | UINT16 DeviceListOffset;\r | |
| 55 | UINT16 Length;\r | |
| 56 | UINT8 Revision;\r | |
| 57 | UINT8 ClassCode[3];\r | |
| 58 | UINT16 ImageLength;\r | |
| 59 | UINT16 CodeRevision;\r | |
| 60 | UINT8 CodeType;\r | |
| 61 | UINT8 Indicator;\r | |
| 62 | UINT16 MaxRuntimeImageLength;\r | |
| 63 | UINT16 ConfigUtilityCodeHeaderOffset;\r | |
| 64 | UINT16 DMTFCLPEntryPointOffset;\r | |
| 65 | } PCI_3_0_DATA_STRUCTURE;\r | |
| 66 | \r | |
| 766f4bc1 | 67 | #pragma pack()\r |
| 68 | \r | |
| a7ed1e2e | 69 | #endif\r |