projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 826a66d4 RN |
1 | /** @file\r |
| 2 | The file lists the PCI class codes only defined in PCI code and ID assignment specification\r | |
| 3 | revision 1.3.\r | |
| 4 | \r | |
| 9095d37b | 5 | Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.<BR>\r |
| 9344f092 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 826a66d4 RN |
7 | \r |
| 8 | **/\r | |
| 9 | \r | |
| 10 | #ifndef __PCI_CODE_ID_H__\r | |
| 11 | #define __PCI_CODE_ID_H__\r | |
| 12 | \r | |
| 13 | \r | |
| 14 | ///\r | |
| 15 | /// PCI_CLASS_MASS_STORAGE, Base Class 01h.\r | |
| 16 | ///\r | |
| 17 | ///@{\r | |
| 18 | #define PCI_IF_MASS_STORAGE_SCSI_VENDOR_SPECIFIC 0x00\r | |
| 19 | #define PCI_IF_MASS_STORAGE_SCSI_DEVICE_PQI 0x11\r | |
| 20 | #define PCI_IF_MASS_STORAGE_SCSI_CONTROLLER_PQI 0x12\r | |
| 21 | #define PCI_IF_MASS_STORAGE_SCSI_DEVICE_CONTROLLER_PQI 0x13\r | |
| 22 | #define PCI_IF_MASS_STORAGE_SCSI_DEVICE_NVM_EXPRESS 0x21\r | |
| 23 | #define PCI_IF_MASS_STORAGE_SATA_SERIAL_BUS 0x02\r | |
| 24 | #define PCI_CLASS_MASS_STORAGE_SAS 0x07\r | |
| 25 | #define PCI_IF_MASS_STORAGE_SAS 0x00\r | |
| 26 | #define PCI_IF_MASS_STORAGE_SAS_SERIAL_BUS 0x01\r | |
| 27 | #define PCI_CLASS_MASS_STORAGE_SOLID_STATE 0x08\r | |
| 28 | #define PCI_IF_MASS_STORAGE_SOLID_STATE 0x00\r | |
| 29 | #define PCI_IF_MASS_STORAGE_SOLID_STATE_NVMHCI 0x01\r | |
| 30 | #define PCI_IF_MASS_STORAGE_SOLID_STATE_ENTERPRISE_NVMHCI 0x02\r | |
| 31 | ///@}\r | |
| 32 | \r | |
| 33 | ///\r | |
| 34 | /// PCI_CLASS_NETWORK, Base Class 02h.\r | |
| 35 | ///\r | |
| 36 | ///@{\r | |
| 37 | #define PCI_CLASS_NETWORK_INFINIBAND 0x07\r | |
| 38 | ///@}\r | |
| 39 | \r | |
| 40 | ///\r | |
| 41 | /// PCI_CLASS_MEDIA, Base Class 04h.\r | |
| 42 | ///\r | |
| 43 | ///@{\r | |
| 44 | #define PCI_CLASS_MEDIA_MIXED_MODE 0x03\r | |
| 45 | ///@}\r | |
| 46 | \r | |
| 47 | ///\r | |
| 48 | /// PCI_CLASS_BRIDGE, Base Class 06h.\r | |
| 49 | ///\r | |
| 50 | ///@{\r | |
| 51 | #define PCI_CLASS_BRIDGE_ADVANCED_SWITCHING_TO_PCI 0x0B\r | |
| 52 | #define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_CUSTOM 0x00\r | |
| 53 | #define PCI_IF_BRIDGE_ADVANCED_SWITCHING_TO_PCI_ASI_SIG 0x01\r | |
| 54 | ///@}\r | |
| 55 | \r | |
| 56 | ///\r | |
| 57 | /// PCI_CLASS_SYSTEM_PERIPHERAL, Base Class 08h.\r | |
| 58 | ///\r | |
| 59 | ///@{\r | |
| 60 | #define PCI_IF_HPET 0x03\r | |
| 61 | #define PCI_SUBCLASS_SD_HOST_CONTROLLER 0x05\r | |
| 62 | #define PCI_SUBCLASS_IOMMU 0x06\r | |
| 63 | ///@}\r | |
| 64 | \r | |
| 65 | ///\r | |
| 66 | /// PCI_CLASS_PROCESSOR, Base Class 0Bh.\r | |
| 67 | ///\r | |
| 68 | ///@{\r | |
| 69 | #define PCI_SUBCLASS_PROC_OTHER 0x80\r | |
| 70 | ///@}\r | |
| 71 | \r | |
| 72 | ///\r | |
| 73 | /// PCI_CLASS_SERIAL, Base Class 0Ch.\r | |
| 74 | ///\r | |
| 75 | ///@{\r | |
| 76 | #define PCI_IF_XHCI 0x30\r | |
| 77 | #define PCI_CLASS_SERIAL_OTHER 0x80\r | |
| 78 | ///@}\r | |
| 79 | \r | |
| 80 | ///\r | |
| 81 | /// PCI_CLASS_SATELLITE, Base Class 0Fh.\r | |
| 82 | ///\r | |
| 83 | ///@{\r | |
| 84 | #define PCI_SUBCLASS_SATELLITE_OTHER 0x80\r | |
| 85 | ///@}\r | |
| 86 | \r | |
| 87 | ///\r | |
| 88 | /// PCI_CLASS_PROCESSING_ACCELERATOR, Base Class 12h.\r | |
| 89 | ///\r | |
| 90 | ///@{\r | |
| 91 | #define PCI_CLASS_PROCESSING_ACCELERATOR 0x12\r | |
| 92 | ///@}\r | |
| 93 | \r | |
| 94 | #endif\r |