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533403e6 | 1 | /** @file\r |
2 | Support for the latest PCI standard.\r | |
3 | \r | |
c9c27019 | 4 | Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r |
0a38a95a | 5 | (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR> \r |
9df063a0 | 6 | This program and the accompanying materials \r |
533403e6 | 7 | are licensed and made available under the terms and conditions of the BSD License \r |
8 | which accompanies this distribution. The full text of the license may be found at \r | |
9 | http://opensource.org/licenses/bsd-license.php \r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #ifndef _PCIEXPRESS21_H_\r | |
17 | #define _PCIEXPRESS21_H_\r | |
18 | \r | |
cbedba86 RN |
19 | #include <IndustryStandard/Pci30.h>\r |
20 | \r | |
c9c27019 RN |
21 | /**\r |
22 | Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an\r | |
23 | ECAM (Enhanced Configuration Access Mechanism) address. The unused upper bits\r | |
24 | of Bus, Device, Function and Register are stripped prior to the generation of\r | |
25 | the address.\r | |
26 | \r | |
27 | @param Bus PCI Bus number. Range 0..255.\r | |
28 | @param Device PCI Device number. Range 0..31.\r | |
29 | @param Function PCI Function number. Range 0..7.\r | |
30 | @param Register PCI Register number. Range 0..4095.\r | |
31 | \r | |
32 | @return The encode ECAM address.\r | |
33 | \r | |
34 | **/\r | |
35 | #define PCI_ECAM_ADDRESS(Bus,Device,Function,Offset) \\r | |
36 | (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r | |
37 | \r | |
cbedba86 RN |
38 | #pragma pack(1)\r |
39 | ///\r | |
40 | /// PCI Express Capability Structure\r | |
41 | ///\r | |
42 | typedef union {\r | |
43 | struct {\r | |
44 | UINT16 Version : 4;\r | |
45 | UINT16 DevicePortType : 4;\r | |
46 | UINT16 SlotImplemented : 1;\r | |
47 | UINT16 InterruptMessageNumber : 5;\r | |
48 | UINT16 Undefined : 1;\r | |
49 | UINT16 Reserved : 1;\r | |
50 | } Bits;\r | |
51 | UINT16 Uint16;\r | |
52 | } PCI_REG_PCIE_CAPABILITY;\r | |
53 | \r | |
54 | #define PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT 0\r | |
55 | #define PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT 1\r | |
56 | #define PCIE_DEVICE_PORT_TYPE_ROOT_PORT 4\r | |
57 | #define PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT 5\r | |
58 | #define PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT 6\r | |
59 | #define PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE 7\r | |
60 | #define PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE 8\r | |
61 | #define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT 9\r | |
62 | #define PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR 10\r | |
63 | \r | |
64 | typedef union {\r | |
65 | struct {\r | |
66 | UINT32 MaxPayloadSize : 3;\r | |
67 | UINT32 PhantomFunctions : 2;\r | |
68 | UINT32 ExtendedTagField : 1;\r | |
69 | UINT32 EndpointL0sAcceptableLatency : 3;\r | |
70 | UINT32 EndpointL1AcceptableLatency : 3;\r | |
71 | UINT32 Undefined : 3;\r | |
72 | UINT32 RoleBasedErrorReporting : 1;\r | |
73 | UINT32 Reserved : 2;\r | |
74 | UINT32 CapturedSlotPowerLimitValue : 8;\r | |
75 | UINT32 CapturedSlotPowerLimitScale : 2;\r | |
76 | UINT32 FunctionLevelReset : 1;\r | |
77 | UINT32 Reserved2 : 3;\r | |
78 | } Bits;\r | |
79 | UINT32 Uint32;\r | |
80 | } PCI_REG_PCIE_DEVICE_CAPABILITY;\r | |
81 | \r | |
82 | typedef union {\r | |
83 | struct {\r | |
84 | UINT16 CorrectableError : 1;\r | |
85 | UINT16 NonFatalError : 1;\r | |
86 | UINT16 FatalError : 1;\r | |
87 | UINT16 UnsupportedRequest : 1;\r | |
88 | UINT16 RelaxedOrdering : 1;\r | |
89 | UINT16 MaxPayloadSize : 3;\r | |
90 | UINT16 ExtendedTagField : 1;\r | |
91 | UINT16 PhantomFunctions : 1;\r | |
92 | UINT16 AuxPower : 1;\r | |
93 | UINT16 NoSnoop : 1;\r | |
94 | UINT16 MaxReadRequestSize : 3;\r | |
95 | UINT16 BridgeConfigurationRetryOrFunctionLevelReset : 1;\r | |
96 | } Bits;\r | |
97 | UINT16 Uint16;\r | |
98 | } PCI_REG_PCIE_DEVICE_CONTROL;\r | |
99 | \r | |
100 | typedef union {\r | |
101 | struct {\r | |
102 | UINT16 CorrectableError : 1;\r | |
103 | UINT16 NonFatalError : 1;\r | |
104 | UINT16 FatalError : 1;\r | |
105 | UINT16 UnsupportedRequest : 1;\r | |
106 | UINT16 AuxPower : 1;\r | |
107 | UINT16 TransactionsPending : 1;\r | |
108 | UINT16 Reserved : 10;\r | |
109 | } Bits;\r | |
110 | UINT16 Uint16;\r | |
111 | } PCI_REG_PCIE_DEVICE_STATUS;\r | |
112 | \r | |
113 | typedef union {\r | |
114 | struct {\r | |
115 | UINT32 MaxLinkSpeed : 4;\r | |
116 | UINT32 MaxLinkWidth : 6;\r | |
117 | UINT32 Aspm : 2;\r | |
118 | UINT32 L0sExitLatency : 3;\r | |
119 | UINT32 L1ExitLatency : 3;\r | |
120 | UINT32 ClockPowerManagement : 1;\r | |
121 | UINT32 SurpriseDownError : 1;\r | |
122 | UINT32 DataLinkLayerLinkActive : 1;\r | |
123 | UINT32 LinkBandwidthNotification : 1;\r | |
124 | UINT32 AspmOptionalityCompliance : 1;\r | |
125 | UINT32 Reserved : 1;\r | |
126 | UINT32 PortNumber : 8;\r | |
127 | } Bits;\r | |
128 | UINT32 Uint32;\r | |
129 | } PCI_REG_PCIE_LINK_CAPABILITY;\r | |
130 | \r | |
131 | #define PCIE_LINK_ASPM_L0S BIT0\r | |
132 | #define PCIE_LINK_ASPM_L1 BIT1\r | |
133 | \r | |
134 | typedef union {\r | |
135 | struct {\r | |
136 | UINT16 AspmControl : 2;\r | |
137 | UINT16 Reserved : 1;\r | |
138 | UINT16 ReadCompletionBoundary : 1;\r | |
139 | UINT16 LinkDisable : 1;\r | |
140 | UINT16 RetrainLink : 1;\r | |
141 | UINT16 CommonClockConfiguration : 1;\r | |
142 | UINT16 ExtendedSynch : 1;\r | |
143 | UINT16 ClockPowerManagement : 1;\r | |
144 | UINT16 HardwareAutonomousWidthDisable : 1;\r | |
145 | UINT16 LinkBandwidthManagementInterrupt : 1;\r | |
146 | UINT16 LinkAutonomousBandwidthInterrupt : 1;\r | |
147 | } Bits;\r | |
148 | UINT16 Uint16;\r | |
149 | } PCI_REG_PCIE_LINK_CONTROL;\r | |
150 | \r | |
151 | typedef union {\r | |
152 | struct {\r | |
153 | UINT16 CurrentLinkSpeed : 4;\r | |
154 | UINT16 NegotiatedLinkWidth : 6;\r | |
155 | UINT16 Undefined : 1;\r | |
156 | UINT16 LinkTraining : 1;\r | |
157 | UINT16 SlotClockConfiguration : 1;\r | |
158 | UINT16 DataLinkLayerLinkActive : 1;\r | |
159 | UINT16 LinkBandwidthManagement : 1;\r | |
160 | UINT16 LinkAutonomousBandwidth : 1;\r | |
161 | } Bits;\r | |
162 | UINT16 Uint16;\r | |
163 | } PCI_REG_PCIE_LINK_STATUS;\r | |
164 | \r | |
165 | typedef union {\r | |
166 | struct {\r | |
167 | UINT32 AttentionButton : 1;\r | |
168 | UINT32 PowerController : 1;\r | |
169 | UINT32 MrlSensor : 1;\r | |
170 | UINT32 AttentionIndicator : 1;\r | |
171 | UINT32 PowerIndicator : 1;\r | |
172 | UINT32 HotPlugSurprise : 1;\r | |
173 | UINT32 HotPlugCapable : 1;\r | |
174 | UINT32 SlotPowerLimitValue : 8;\r | |
175 | UINT32 SlotPowerLimitScale : 2;\r | |
176 | UINT32 ElectromechanicalInterlock : 1;\r | |
177 | UINT32 NoCommandCompleted : 1;\r | |
178 | UINT32 PhysicalSlotNumber : 13;\r | |
179 | } Bits;\r | |
180 | UINT32 Uint32;\r | |
181 | } PCI_REG_PCIE_SLOT_CAPABILITY;\r | |
182 | \r | |
183 | typedef union {\r | |
184 | struct {\r | |
185 | UINT32 AttentionButtonPressed : 1;\r | |
186 | UINT32 PowerFaultDetected : 1;\r | |
187 | UINT32 MrlSensorChanged : 1;\r | |
188 | UINT32 PresenceDetectChanged : 1;\r | |
189 | UINT32 CommandCompletedInterrupt : 1;\r | |
190 | UINT32 HotPlugInterrupt : 1;\r | |
191 | UINT32 AttentionIndicator : 2;\r | |
192 | UINT32 PowerIndicator : 2;\r | |
193 | UINT32 PowerController : 1;\r | |
194 | UINT32 ElectromechanicalInterlock : 1;\r | |
195 | UINT32 DataLinkLayerStateChanged : 1;\r | |
196 | UINT32 Reserved : 3;\r | |
197 | } Bits;\r | |
198 | UINT16 Uint16;\r | |
199 | } PCI_REG_PCIE_SLOT_CONTROL;\r | |
200 | \r | |
201 | typedef union {\r | |
202 | struct {\r | |
203 | UINT16 AttentionButtonPressed : 1;\r | |
204 | UINT16 PowerFaultDetected : 1;\r | |
205 | UINT16 MrlSensorChanged : 1;\r | |
206 | UINT16 PresenceDetectChanged : 1;\r | |
207 | UINT16 CommandCompleted : 1;\r | |
208 | UINT16 MrlSensor : 1;\r | |
209 | UINT16 PresenceDetect : 1;\r | |
210 | UINT16 ElectromechanicalInterlock : 1;\r | |
211 | UINT16 DataLinkLayerStateChanged : 1;\r | |
212 | UINT16 Reserved : 7;\r | |
213 | } Bits;\r | |
214 | UINT16 Uint16;\r | |
215 | } PCI_REG_PCIE_SLOT_STATUS;\r | |
216 | \r | |
217 | typedef union {\r | |
218 | struct {\r | |
219 | UINT16 SystemErrorOnCorrectableError : 1;\r | |
220 | UINT16 SystemErrorOnNonFatalError : 1;\r | |
221 | UINT16 SystemErrorOnFatalError : 1;\r | |
222 | UINT16 PmeInterrupt : 1;\r | |
223 | UINT16 CrsSoftwareVisibility : 1;\r | |
224 | UINT16 Reserved : 11;\r | |
225 | } Bits;\r | |
226 | UINT16 Uint16;\r | |
227 | } PCI_REG_PCIE_ROOT_CONTROL;\r | |
228 | \r | |
229 | typedef union {\r | |
230 | struct {\r | |
231 | UINT16 CrsSoftwareVisibility : 1;\r | |
232 | UINT16 Reserved : 15;\r | |
233 | } Bits;\r | |
234 | UINT16 Uint16;\r | |
235 | } PCI_REG_PCIE_ROOT_CAPABILITY;\r | |
236 | \r | |
237 | typedef union {\r | |
238 | struct {\r | |
239 | UINT32 PmeRequesterId : 16;\r | |
240 | UINT32 PmeStatus : 1;\r | |
241 | UINT32 PmePending : 1;\r | |
242 | UINT32 Reserved : 14;\r | |
243 | } Bits;\r | |
244 | UINT32 Uint32;\r | |
245 | } PCI_REG_PCIE_ROOT_STATUS;\r | |
246 | \r | |
247 | typedef union {\r | |
248 | struct {\r | |
249 | UINT32 CompletionTimeoutRanges : 4;\r | |
250 | UINT32 CompletionTimeoutDisable : 1;\r | |
251 | UINT32 AriForwarding : 1;\r | |
252 | UINT32 AtomicOpRouting : 1;\r | |
253 | UINT32 AtomicOp32Completer : 1;\r | |
254 | UINT32 AtomicOp64Completer : 1;\r | |
255 | UINT32 Cas128Completer : 1;\r | |
256 | UINT32 NoRoEnabledPrPrPassing : 1;\r | |
257 | UINT32 LtrMechanism : 1;\r | |
258 | UINT32 TphCompleter : 2;\r | |
259 | UINT32 Reserved : 4;\r | |
260 | UINT32 Obff : 2;\r | |
261 | UINT32 ExtendedFmtField : 1;\r | |
262 | UINT32 EndEndTlpPrefix : 1;\r | |
263 | UINT32 MaxEndEndTlpPrefixes : 2;\r | |
264 | UINT32 Reserved2 : 8;\r | |
265 | } Bits;\r | |
266 | UINT32 Uint32;\r | |
267 | } PCI_REG_PCIE_DEVICE_CAPABILITY2;\r | |
268 | \r | |
269 | #define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0\r | |
270 | #define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1\r | |
271 | \r | |
272 | typedef union {\r | |
273 | struct {\r | |
274 | UINT16 CompletionTimeoutValue : 4;\r | |
275 | UINT16 CompletionTimeoutDisable : 1;\r | |
276 | UINT16 AriForwarding : 1;\r | |
277 | UINT16 AtomicOpRequester : 1;\r | |
278 | UINT16 AtomicOpEgressBlocking : 1;\r | |
279 | UINT16 IdoRequest : 1;\r | |
280 | UINT16 IdoCompletion : 1;\r | |
281 | UINT16 LtrMechanism : 2;\r | |
282 | UINT16 Reserved : 2;\r | |
283 | UINT16 Obff : 2;\r | |
284 | UINT16 EndEndTlpPrefixBlocking : 1;\r | |
285 | } Bits;\r | |
286 | UINT16 Uint16;\r | |
287 | } PCI_REG_PCIE_DEVICE_CONTROL2;\r | |
288 | \r | |
289 | #define PCIE_COMPLETION_TIMEOUT_50US_50MS 0\r | |
290 | #define PCIE_COMPLETION_TIMEOUT_50US_100US 1\r | |
291 | #define PCIE_COMPLETION_TIMEOUT_1MS_10MS 2\r | |
292 | #define PCIE_COMPLETION_TIMEOUT_16MS_55MS 5\r | |
293 | #define PCIE_COMPLETION_TIMEOUT_65MS_210MS 6\r | |
294 | #define PCIE_COMPLETION_TIMEOUT_260MS_900MS 9\r | |
295 | #define PCIE_COMPLETION_TIMEOUT_1S_3_5S 10\r | |
296 | #define PCIE_COMPLETION_TIMEOUT_4S_13S 13\r | |
297 | #define PCIE_COMPLETION_TIMEOUT_17S_64S 14\r | |
298 | \r | |
299 | #define PCIE_DEVICE_CONTROL_OBFF_DISABLED 0\r | |
300 | #define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_A 1\r | |
301 | #define PCIE_DEVICE_CONTROL_OBFF_MESSAGE_B 2\r | |
302 | #define PCIE_DEVICE_CONTROL_OBFF_WAKE 3\r | |
303 | \r | |
304 | typedef union {\r | |
305 | struct {\r | |
306 | UINT32 Reserved : 1;\r | |
307 | UINT32 LinkSpeedsVector : 7;\r | |
308 | UINT32 Crosslink : 1;\r | |
309 | UINT32 Reserved2 : 23;\r | |
310 | } Bits;\r | |
311 | UINT32 Uint32;\r | |
312 | } PCI_REG_PCIE_LINK_CAPABILITY2;\r | |
313 | \r | |
314 | typedef union {\r | |
315 | struct {\r | |
316 | UINT16 TargetLinkSpeed : 4;\r | |
317 | UINT16 EnterCompliance : 1;\r | |
318 | UINT16 HardwareAutonomousSpeedDisable : 1;\r | |
319 | UINT16 SelectableDeemphasis : 1;\r | |
320 | UINT16 TransmitMargin : 3;\r | |
321 | UINT16 EnterModifiedCompliance : 1;\r | |
322 | UINT16 ComplianceSos : 1;\r | |
323 | UINT16 CompliancePresetDeemphasis : 4;\r | |
324 | } Bits;\r | |
325 | UINT16 Uint16;\r | |
326 | } PCI_REG_PCIE_LINK_CONTROL2;\r | |
327 | \r | |
328 | typedef union {\r | |
329 | struct {\r | |
330 | UINT16 CurrentDeemphasisLevel : 1;\r | |
331 | UINT16 EqualizationComplete : 1;\r | |
332 | UINT16 EqualizationPhase1Successful : 1;\r | |
333 | UINT16 EqualizationPhase2Successful : 1;\r | |
334 | UINT16 EqualizationPhase3Successful : 1;\r | |
335 | UINT16 LinkEqualizationRequest : 1;\r | |
336 | UINT16 Reserved : 10;\r | |
337 | } Bits;\r | |
338 | UINT16 Uint16;\r | |
339 | } PCI_REG_PCIE_LINK_STATUS2;\r | |
340 | \r | |
341 | typedef struct {\r | |
342 | EFI_PCI_CAPABILITY_HDR Hdr;\r | |
343 | PCI_REG_PCIE_CAPABILITY Capability;\r | |
344 | PCI_REG_PCIE_DEVICE_CAPABILITY DeviceCapability;\r | |
345 | PCI_REG_PCIE_DEVICE_CONTROL DeviceControl;\r | |
346 | PCI_REG_PCIE_DEVICE_STATUS DeviceStatus;\r | |
347 | PCI_REG_PCIE_LINK_CAPABILITY LinkCapability;\r | |
348 | PCI_REG_PCIE_LINK_CONTROL LinkControl;\r | |
349 | PCI_REG_PCIE_LINK_STATUS LinkStatus;\r | |
350 | PCI_REG_PCIE_SLOT_CAPABILITY SlotCapability;\r | |
351 | PCI_REG_PCIE_SLOT_CONTROL SlotControl;\r | |
352 | PCI_REG_PCIE_SLOT_STATUS SlotStatus;\r | |
353 | PCI_REG_PCIE_ROOT_CONTROL RootControl;\r | |
354 | PCI_REG_PCIE_ROOT_CAPABILITY RootCapability;\r | |
355 | PCI_REG_PCIE_ROOT_STATUS RootStatus;\r | |
356 | PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCapability2;\r | |
357 | PCI_REG_PCIE_DEVICE_CONTROL2 DeviceControl2;\r | |
358 | UINT16 DeviceStatus2;\r | |
359 | PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2;\r | |
360 | PCI_REG_PCIE_LINK_CONTROL2 LinkControl2;\r | |
361 | PCI_REG_PCIE_LINK_STATUS2 LinkStatus2;\r | |
362 | UINT32 SlotCapability2;\r | |
363 | UINT16 SlotControl2;\r | |
364 | UINT16 SlotStatus2;\r | |
365 | } PCI_CAPABILITY_PCIEXP;\r | |
366 | \r | |
533403e6 | 367 | #define EFI_PCIE_CAPABILITY_BASE_OFFSET 0x100\r |
368 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL_ARI_HIERARCHY 0x10\r | |
369 | #define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_OFFSET 0x24\r | |
370 | #define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING 0x20\r | |
371 | #define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET 0x28\r | |
372 | #define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_ARI_FORWARDING 0x20\r | |
373 | \r | |
374 | //\r | |
375 | // for SR-IOV\r | |
376 | //\r | |
377 | #define EFI_PCIE_CAPABILITY_ID_ARI 0x0E\r | |
378 | #define EFI_PCIE_CAPABILITY_ID_ATS 0x0F\r | |
379 | #define EFI_PCIE_CAPABILITY_ID_SRIOV 0x10\r | |
380 | #define EFI_PCIE_CAPABILITY_ID_MRIOV 0x11\r | |
381 | \r | |
382 | typedef struct {\r | |
383 | UINT32 CapabilityHeader;\r | |
384 | UINT32 Capability;\r | |
385 | UINT16 Control;\r | |
386 | UINT16 Status;\r | |
387 | UINT16 InitialVFs;\r | |
388 | UINT16 TotalVFs;\r | |
389 | UINT16 NumVFs;\r | |
390 | UINT8 FunctionDependencyLink;\r | |
391 | UINT8 Reserved0;\r | |
392 | UINT16 FirstVFOffset;\r | |
393 | UINT16 VFStride;\r | |
394 | UINT16 Reserved1;\r | |
395 | UINT16 VFDeviceID;\r | |
396 | UINT32 SupportedPageSize;\r | |
397 | UINT32 SystemPageSize;\r | |
398 | UINT32 VFBar[6];\r | |
399 | UINT32 VFMigrationStateArrayOffset;\r | |
400 | } SR_IOV_CAPABILITY_REGISTER;\r | |
401 | \r | |
402 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_CAPABILITIES 0x04\r | |
403 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_CONTROL 0x08\r | |
404 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_STATUS 0x0A\r | |
405 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_INITIALVFS 0x0C\r | |
406 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_TOTALVFS 0x0E\r | |
407 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_NUMVFS 0x10\r | |
408 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_FUNCTION_DEPENDENCY_LINK 0x12\r | |
409 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_FIRSTVF 0x14\r | |
410 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_VFSTRIDE 0x16\r | |
411 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_VFDEVICEID 0x1A\r | |
412 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_SUPPORTED_PAGE_SIZE 0x1C\r | |
413 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_SYSTEM_PAGE_SIZE 0x20\r | |
414 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR0 0x24\r | |
415 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR1 0x28\r | |
416 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR2 0x2C\r | |
417 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR3 0x30\r | |
418 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR4 0x34\r | |
419 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5 0x38\r | |
420 | #define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE 0x3C\r | |
421 | \r | |
a1d20250 JC |
422 | typedef struct {\r |
423 | UINT32 CapabilityId:16;\r | |
424 | UINT32 CapabilityVersion:4;\r | |
425 | UINT32 NextCapabilityOffset:12;\r | |
426 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER;\r | |
427 | \r | |
428 | #define PCI_EXP_EXT_HDR PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER\r | |
429 | \r | |
430 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID 0x0001\r | |
431 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 0x1\r | |
432 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2\r | |
433 | \r | |
cbedba86 RN |
434 | typedef union {\r |
435 | struct {\r | |
436 | UINT32 Undefined : 1;\r | |
437 | UINT32 Reserved : 3;\r | |
438 | UINT32 DataLinkProtocolError : 1;\r | |
439 | UINT32 SurpriseDownError : 1;\r | |
440 | UINT32 Reserved2 : 6;\r | |
441 | UINT32 PoisonedTlp : 1;\r | |
442 | UINT32 FlowControlProtocolError : 1;\r | |
443 | UINT32 CompletionTimeout : 1;\r | |
444 | UINT32 CompleterAbort : 1;\r | |
445 | UINT32 UnexpectedCompletion : 1;\r | |
446 | UINT32 ReceiverOverflow : 1;\r | |
447 | UINT32 MalformedTlp : 1;\r | |
448 | UINT32 EcrcError : 1;\r | |
449 | UINT32 UnsupportedRequestError : 1;\r | |
450 | UINT32 AcsVoilation : 1;\r | |
451 | UINT32 UncorrectableInternalError : 1;\r | |
452 | UINT32 McBlockedTlp : 1;\r | |
453 | UINT32 AtomicOpEgressBlocked : 1;\r | |
454 | UINT32 TlpPrefixBlockedError : 1;\r | |
455 | UINT32 Reserved3 : 6;\r | |
456 | } Bits;\r | |
457 | UINT32 Uint32;\r | |
458 | } PCI_EXPRESS_REG_UNCORRECTABLE_ERROR;\r | |
459 | \r | |
a1d20250 JC |
460 | typedef struct {\r |
461 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
cbedba86 RN |
462 | PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorStatus;\r |
463 | PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorMask;\r | |
464 | PCI_EXPRESS_REG_UNCORRECTABLE_ERROR UncorrectableErrorSeverity;\r | |
a1d20250 JC |
465 | UINT32 CorrectableErrorStatus;\r |
466 | UINT32 CorrectableErrorMask;\r | |
467 | UINT32 AdvancedErrorCapabilitiesAndControl;\r | |
0a38a95a | 468 | UINT32 HeaderLog[4];\r |
a1d20250 JC |
469 | UINT32 RootErrorCommand;\r |
470 | UINT32 RootErrorStatus;\r | |
471 | UINT16 ErrorSourceIdentification;\r | |
472 | UINT16 CorrectableErrorSourceIdentification;\r | |
473 | UINT32 TlpPrefixLog[4];\r | |
474 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING;\r | |
475 | \r | |
476 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID 0x0002\r | |
477 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_MFVC 0x0009\r | |
478 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_VER1 0x1\r | |
479 | \r | |
480 | typedef struct {\r | |
481 | UINT32 VcResourceCapability:24;\r | |
482 | UINT32 PortArbTableOffset:8;\r | |
483 | UINT32 VcResourceControl;\r | |
484 | UINT16 Reserved1;\r | |
485 | UINT16 VcResourceStatus;\r | |
486 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC;\r | |
487 | \r | |
488 | typedef struct {\r | |
489 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
490 | UINT32 ExtendedVcCount:3;\r | |
491 | UINT32 PortVcCapability1:29;\r | |
492 | UINT32 PortVcCapability2:24;\r | |
493 | UINT32 VcArbTableOffset:8;\r | |
494 | UINT16 PortVcControl;\r | |
495 | UINT16 PortVcStatus;\r | |
496 | PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC Capability[1];\r | |
497 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY;\r | |
498 | \r | |
499 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID 0x0003\r | |
500 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_VER1 0x1\r | |
501 | \r | |
502 | typedef struct {\r | |
503 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
504 | UINT64 SerialNumber;\r | |
505 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER;\r | |
506 | \r | |
507 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID 0x0005\r | |
508 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_VER1 0x1\r | |
509 | \r | |
510 | typedef struct {\r | |
511 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
512 | UINT32 ElementSelfDescription;\r | |
513 | UINT32 Reserved;\r | |
514 | UINT32 LinkEntry[1];\r | |
515 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION;\r | |
516 | \r | |
517 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(LINK_DECLARATION) (UINT8)(((LINK_DECLARATION->ElementSelfDescription)&0x0000ff00)>>8)\r | |
518 | \r | |
519 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID 0x0006\r | |
520 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_VER1 0x1\r | |
521 | \r | |
522 | typedef struct {\r | |
523 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
524 | UINT32 RootComplexLinkCapabilities;\r | |
525 | UINT16 RootComplexLinkControl;\r | |
526 | UINT16 RootComplexLinkStatus;\r | |
527 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL;\r | |
528 | \r | |
529 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID 0x0004\r | |
530 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_VER1 0x1\r | |
531 | \r | |
532 | typedef struct {\r | |
533 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
534 | UINT32 DataSelect:8;\r | |
535 | UINT32 Reserved:24;\r | |
536 | UINT32 Data;\r | |
537 | UINT32 PowerBudgetCapability:1;\r | |
538 | UINT32 Reserved2:7;\r | |
539 | UINT32 Reserved3:24;\r | |
540 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING;\r | |
541 | \r | |
542 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID 0x000D\r | |
543 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_VER1 0x1\r | |
544 | \r | |
545 | typedef struct {\r | |
546 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
547 | UINT16 AcsCapability;\r | |
548 | UINT16 AcsControl;\r | |
549 | UINT8 EgressControlVectorArray[1];\r | |
550 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED;\r | |
551 | \r | |
552 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x00000020))\r | |
553 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(ACS_EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x0000FF00))\r | |
554 | \r | |
555 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID 0x0007\r | |
556 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_VER1 0x1\r | |
557 | \r | |
558 | typedef struct {\r | |
559 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
560 | UINT32 AssociationBitmap;\r | |
561 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION;\r | |
562 | \r | |
563 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID 0x0008\r | |
564 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_VER1 0x1\r | |
565 | \r | |
566 | typedef PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTI_FUNCTION_VIRTUAL_CHANNEL_CAPABILITY;\r | |
567 | \r | |
568 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID 0x000B\r | |
569 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_VER1 0x1\r | |
570 | \r | |
571 | typedef struct {\r | |
572 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
573 | UINT32 VendorSpecificHeader;\r | |
574 | UINT8 VendorSpecific[1];\r | |
575 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC;\r | |
576 | \r | |
577 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(VENDOR) (UINT16)(((VENDOR->VendorSpecificHeader)&0xFFF00000)>>20)\r | |
578 | \r | |
579 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID 0x000A\r | |
580 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_VER1 0x1\r | |
581 | \r | |
582 | typedef struct {\r | |
583 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
584 | UINT16 VendorId;\r | |
585 | UINT16 DeviceId;\r | |
586 | UINT32 RcrbCapabilities;\r | |
587 | UINT32 RcrbControl;\r | |
588 | UINT32 Reserved;\r | |
589 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER;\r | |
590 | \r | |
591 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID 0x0012\r | |
592 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_VER1 0x1\r | |
593 | \r | |
594 | typedef struct {\r | |
595 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
596 | UINT16 MultiCastCapability;\r | |
597 | UINT16 MulticastControl;\r | |
598 | UINT64 McBaseAddress;\r | |
599 | UINT64 McReceiveAddress;\r | |
600 | UINT64 McBlockAll;\r | |
601 | UINT64 McBlockUntranslated;\r | |
602 | UINT64 McOverlayBar;\r | |
603 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST;\r | |
604 | \r | |
605 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID 0x0015\r | |
606 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_VER1 0x1\r | |
607 | \r | |
608 | typedef struct {\r | |
609 | UINT32 ResizableBarCapability;\r | |
610 | UINT16 ResizableBarControl;\r | |
611 | UINT16 Reserved;\r | |
612 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY;\r | |
613 | \r | |
614 | typedef struct {\r | |
615 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
616 | PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Capability[1];\r | |
617 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR;\r | |
618 | \r | |
e1c9edd6 JC |
619 | #define GET_NUMBER_RESIZABLE_BARS(x) (((x->Capability[0].ResizableBarControl) & 0xE0) >> 5)\r |
620 | \r | |
a1d20250 JC |
621 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID 0x000E\r |
622 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_VER1 0x1\r | |
623 | \r | |
624 | typedef struct {\r | |
625 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
626 | UINT16 AriCapability;\r | |
627 | UINT16 AriControl;\r | |
628 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY;\r | |
629 | \r | |
630 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID 0x0016\r | |
631 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_VER1 0x1\r | |
632 | \r | |
633 | typedef struct {\r | |
634 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
635 | UINT32 DpaCapability;\r | |
636 | UINT32 DpaLatencyIndicator;\r | |
637 | UINT16 DpaStatus;\r | |
638 | UINT16 DpaControl;\r | |
639 | UINT8 DpaPowerAllocationArray[1];\r | |
640 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION;\r | |
641 | \r | |
642 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_MAX(POWER) (UINT16)(((POWER->DpaCapability)&0x0000000F))\r | |
643 | \r | |
644 | \r | |
645 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID 0x0018\r | |
646 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_VER1 0x1\r | |
647 | \r | |
648 | typedef struct {\r | |
649 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
650 | UINT16 MaxSnoopLatency;\r | |
651 | UINT16 MaxNoSnoopLatency;\r | |
652 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING;\r | |
653 | \r | |
654 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID 0x0017\r | |
655 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_VER1 0x1\r | |
656 | \r | |
657 | typedef struct {\r | |
658 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
659 | UINT32 TphRequesterCapability;\r | |
660 | UINT32 TphRequesterControl;\r | |
661 | UINT16 TphStTable[1];\r | |
662 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH;\r | |
663 | \r | |
e1c9edd6 JC |
664 | #define GET_TPH_TABLE_SIZE(x) ((x->TphRequesterCapability & 0x7FF0000)>>16) * sizeof(UINT16)\r |
665 | \r | |
cbedba86 RN |
666 | #pragma pack()\r |
667 | \r | |
533403e6 | 668 | #endif\r |