projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| a1d20250 JC |
1 | /** @file\r |
| 2 | Support for the PCI Express 3.0 standard.\r | |
| 3 | \r | |
| 4 | This header file may not define all structures. Please extend as required.\r | |
| 5 | \r | |
| cbedba86 | 6 | Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>\r |
| a1d20250 JC |
7 | This program and the accompanying materials \r |
| 8 | are licensed and made available under the terms and conditions of the BSD License \r | |
| 9 | which accompanies this distribution. The full text of the license may be found at \r | |
| 10 | http://opensource.org/licenses/bsd-license.php \r | |
| 11 | \r | |
| 12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
| 13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
| 14 | \r | |
| 15 | **/\r | |
| 16 | \r | |
| 17 | #ifndef _PCIEXPRESS30_H_\r | |
| 18 | #define _PCIEXPRESS30_H_\r | |
| 19 | \r | |
| cbedba86 RN |
20 | #include <IndustryStandard/PciExpress21.h>\r |
| 21 | \r | |
| 22 | #pragma pack(1)\r | |
| a1d20250 JC |
23 | \r |
| 24 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID 0x0019\r | |
| 25 | #define PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_VER1 0x1\r | |
| 26 | \r | |
| cbedba86 RN |
27 | typedef union {\r |
| 28 | struct {\r | |
| 29 | UINT32 PerformEqualization : 1;\r | |
| 30 | UINT32 LinkEqualizationRequestInterruptEnable : 1;\r | |
| 31 | UINT32 Reserved : 30;\r | |
| 32 | } Bits;\r | |
| 33 | UINT32 Uint32;\r | |
| 34 | } PCI_EXPRESS_REG_LINK_CONTROL3;\r | |
| 35 | \r | |
| 36 | typedef union {\r | |
| 37 | struct {\r | |
| 38 | UINT16 DownstreamPortTransmitterPreset : 4;\r | |
| 39 | UINT16 DownstreamPortReceiverPresetHint : 3;\r | |
| 40 | UINT16 Reserved : 1;\r | |
| 41 | UINT16 UpstreamPortTransmitterPreset : 4;\r | |
| 42 | UINT16 UpstreamPortReceiverPresetHint : 3;\r | |
| 43 | UINT16 Reserved2 : 1;\r | |
| 44 | } Bits;\r | |
| 45 | UINT16 Uint16;\r | |
| 46 | } PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL;\r | |
| 47 | \r | |
| a1d20250 JC |
48 | typedef struct {\r |
| 49 | PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;\r | |
| cbedba86 | 50 | PCI_EXPRESS_REG_LINK_CONTROL3 LinkControl3;\r |
| a1d20250 | 51 | UINT32 LaneErrorStatus;\r |
| cbedba86 | 52 | PCI_EXPRESS_REG_LANE_EQUALIZATION_CONTROL EqualizationControl[2];\r |
| a1d20250 JC |
53 | } PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE;\r |
| 54 | \r | |
| cbedba86 RN |
55 | #pragma pack()\r |
| 56 | \r | |
| a1d20250 | 57 | #endif\r |