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540dfc26 1/** @file\r
2 Main SAL API's defined in SAL 3.0 specification. \r
3\r
4 Copyright (c) 2006, Intel Corporation \r
5 All rights reserved. This program and the accompanying materials \r
6 are licensed and made available under the terms and conditions of the BSD License \r
7 which accompanies this distribution. The full text of the license may be found at \r
8 http://opensource.org/licenses/bsd-license.php \r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
12\r
540dfc26 13**/\r
14\r
15#ifndef __SAL_API_H__\r
16#define __SAL_API_H__\r
17\r
18//\r
19// FIT Types \r
20// Table 2-2 of Intel Itanium Processor Family System Abstraction Layer Specification December 2003\r
21//\r
22#define EFI_SAL_FIT_FIT_HEADER_TYPE 0x00\r
23#define EFI_SAL_FIT_PAL_B_TYPE 0x01\r
24//\r
25// type from 0x02 to 0x0E is reserved.\r
26//\r
27#define EFI_SAL_FIT_PAL_A_TYPE 0x0F\r
28//\r
29// OEM-defined type range is from 0x10 to 0x7E. Here we defined the PEI_CORE type as 0x10\r
30//\r
31#define EFI_SAL_FIT_PEI_CORE_TYPE 0x10\r
32#define EFI_SAL_FIT_UNUSED_TYPE 0x7F\r
33\r
34//\r
35// EFI_SAL_STATUS \r
36//\r
37typedef UINTN EFI_SAL_STATUS;\r
38\r
39#define EFI_SAL_SUCCESS ((EFI_SAL_STATUS) 0)\r
40#define EFI_SAL_MORE_RECORDS ((EFI_SAL_STATUS) 3)\r
41#define EFI_SAL_NOT_IMPLEMENTED ((EFI_SAL_STATUS) - 1)\r
42#define EFI_SAL_INVALID_ARGUMENT ((EFI_SAL_STATUS) - 2)\r
43#define EFI_SAL_ERROR ((EFI_SAL_STATUS) - 3)\r
44#define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)\r
45#define EFI_SAL_NO_INFORMATION ((EFI_SAL_STATUS) - 5)\r
46#define EFI_SAL_NOT_ENOUGH_SCRATCH ((EFI_SAL_STATUS) - 9)\r
47\r
48//\r
49// Return values from SAL\r
50//\r
51typedef struct {\r
52 EFI_SAL_STATUS Status; // register r8\r
53 UINTN r9;\r
54 UINTN r10;\r
55 UINTN r11;\r
56} SAL_RETURN_REGS;\r
57\r
58//\r
59// Delivery Mode of IPF CPU.\r
60//\r
61typedef enum {\r
62 EFI_DELIVERY_MODE_INT,\r
63 EFI_DELIVERY_MODE_MPreserved1,\r
64 EFI_DELIVERY_MODE_PMI,\r
65 EFI_DELIVERY_MODE_MPreserved2,\r
66 EFI_DELIVERY_MODE_NMI,\r
67 EFI_DELIVERY_MODE_INIT,\r
68 EFI_DELIVERY_MODE_MPreserved3,\r
69 EFI_DELIVERY_MODE_ExtINT\r
70} EFI_DELIVERY_MODE;\r
71\r
72typedef SAL_RETURN_REGS (EFIAPI *SAL_PROC)\r
73 (\r
74 IN UINT64 FunctionId,\r
75 IN UINT64 Arg2,\r
76 IN UINT64 Arg3,\r
77 IN UINT64 Arg4,\r
78 IN UINT64 Arg5,\r
79 IN UINT64 Arg6,\r
80 IN UINT64 Arg7,\r
81 IN UINT64 Arg8\r
82 );\r
83\r
84//\r
85// SAL Procedure FunctionId definition\r
86//\r
87#define EFI_SAL_SET_VECTORS 0x01000000\r
88#define EFI_SAL_GET_STATE_INFO 0x01000001\r
89#define EFI_SAL_GET_STATE_INFO_SIZE 0x01000002\r
90#define EFI_SAL_CLEAR_STATE_INFO 0x01000003\r
91#define EFI_SAL_MC_RENDEZ 0x01000004\r
92#define EFI_SAL_MC_SET_PARAMS 0x01000005\r
93#define EFI_SAL_REGISTER_PHYSICAL_ADDR 0x01000006\r
94#define EFI_SAL_CACHE_FLUSH 0x01000008\r
95#define EFI_SAL_CACHE_INIT 0x01000009\r
96#define EFI_SAL_PCI_CONFIG_READ 0x01000010\r
97#define EFI_SAL_PCI_CONFIG_WRITE 0x01000011\r
98#define EFI_SAL_FREQ_BASE 0x01000012\r
9c8403b3 99#define EFI_SAL_PHYSICAL_ID_INFO 0x01000013\r
540dfc26 100#define EFI_SAL_UPDATE_PAL 0x01000020\r
101\r
102#define EFI_SAL_FUNCTION_ID_MASK 0x0000ffff\r
103#define EFI_SAL_MAX_SAL_FUNCTION_ID 0x00000021\r
104\r
105//\r
106// SAL Procedure parameter definitions\r
107// Not much point in using typedefs or enums because all params\r
108// are UINT64 and the entry point is common\r
109//\r
110// EFI_SAL_SET_VECTORS\r
111//\r
112#define EFI_SAL_SET_MCA_VECTOR 0x0\r
113#define EFI_SAL_SET_INIT_VECTOR 0x1\r
114#define EFI_SAL_SET_BOOT_RENDEZ_VECTOR 0x2\r
115\r
116typedef struct {\r
117 UINT64 Length : 32;\r
118 UINT64 ChecksumValid : 1;\r
119 UINT64 Reserved1 : 7;\r
120 UINT64 ByteChecksum : 8;\r
121 UINT64 Reserved2 : 16;\r
122} SAL_SET_VECTORS_CS_N;\r
123\r
124//\r
125// EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE,\r
126// EFI_SAL_CLEAR_STATE_INFO\r
127//\r
128#define EFI_SAL_MCA_STATE_INFO 0x0\r
129#define EFI_SAL_INIT_STATE_INFO 0x1\r
130#define EFI_SAL_CMC_STATE_INFO 0x2\r
131#define EFI_SAL_CP_STATE_INFO 0x3\r
132\r
133//\r
134// EFI_SAL_MC_SET_PARAMS\r
135//\r
136#define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1\r
137#define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2\r
138#define EFI_SAL_MC_SET_CPE_PARAM 0x3\r
139\r
140#define EFI_SAL_MC_SET_INTR_PARAM 0x1\r
141#define EFI_SAL_MC_SET_MEM_PARAM 0x2\r
142\r
143//\r
144// EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR\r
145//\r
146#define EFI_SAL_REGISTER_PAL_ADDR 0x0\r
147\r
148//\r
149// EFI_SAL_CACHE_FLUSH\r
150//\r
151#define EFI_SAL_FLUSH_I_CACHE 0x01\r
152#define EFI_SAL_FLUSH_D_CACHE 0x02\r
153#define EFI_SAL_FLUSH_BOTH_CACHE 0x03\r
154#define EFI_SAL_FLUSH_MAKE_COHERENT 0x04\r
155\r
156//\r
157// EFI_SAL_PCI_CONFIG_READ, EFI_SAL_PCI_CONFIG_WRITE\r
158//\r
159#define EFI_SAL_PCI_CONFIG_ONE_BYTE 0x1\r
160#define EFI_SAL_PCI_CONFIG_TWO_BYTES 0x2\r
161#define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4\r
162\r
163typedef struct {\r
164 UINT64 Register : 8;\r
165 UINT64 Function : 3;\r
166 UINT64 Device : 5;\r
167 UINT64 Bus : 8;\r
168 UINT64 Segment : 8;\r
169 UINT64 Reserved : 32;\r
170} SAL_PCI_ADDRESS;\r
171\r
172//\r
173// EFI_SAL_FREQ_BASE\r
174//\r
175#define EFI_SAL_CPU_INPUT_FREQ_BASE 0x0\r
176#define EFI_SAL_PLATFORM_IT_FREQ_BASE 0x1\r
177#define EFI_SAL_PLATFORM_RTC_FREQ_BASE 0x2\r
178\r
179//\r
180// EFI_SAL_UPDATE_PAL\r
181//\r
182#define EFI_SAL_UPDATE_BAD_PAL_VERSION ((UINT64) -1)\r
183#define EFI_SAL_UPDATE_PAL_AUTH_FAIL ((UINT64) -2)\r
184#define EFI_SAL_UPDATE_PAL_BAD_TYPE ((UINT64) -3)\r
185#define EFI_SAL_UPDATE_PAL_READONLY ((UINT64) -4)\r
186#define EFI_SAL_UPDATE_PAL_WRITE_FAIL ((UINT64) -10)\r
187#define EFI_SAL_UPDATE_PAL_ERASE_FAIL ((UINT64) -11)\r
188#define EFI_SAL_UPDATE_PAL_READ_FAIL ((UINT64) -12)\r
189#define EFI_SAL_UPDATE_PAL_CANT_FIT ((UINT64) -13)\r
190\r
191typedef struct {\r
192 UINT32 Size;\r
193 UINT32 MmddyyyyDate;\r
194 UINT16 Version;\r
195 UINT8 Type;\r
196 UINT8 Reserved[5];\r
197 UINT64 FwVendorId;\r
198} SAL_UPDATE_PAL_DATA_BLOCK;\r
199\r
200typedef struct _SAL_UPDATE_PAL_INFO_BLOCK {\r
201 struct _SAL_UPDATE_PAL_INFO_BLOCK *Next;\r
202 struct SAL_UPDATE_PAL_DATA_BLOCK *DataBlock;\r
203 UINT8 StoreChecksum;\r
204 UINT8 Reserved[15];\r
205} SAL_UPDATE_PAL_INFO_BLOCK;\r
206\r
207//\r
208// SAL System Table Definitions\r
209//\r
210#pragma pack(1)\r
211typedef struct {\r
212 UINT32 Signature;\r
213 UINT32 Length;\r
214 UINT16 SalRevision;\r
215 UINT16 EntryCount;\r
216 UINT8 CheckSum;\r
217 UINT8 Reserved[7];\r
218 UINT16 SalAVersion;\r
219 UINT16 SalBVersion;\r
220 UINT8 OemId[32];\r
221 UINT8 ProductId[32];\r
222 UINT8 Reserved2[8];\r
223} SAL_SYSTEM_TABLE_HEADER;\r
224#pragma pack()\r
225\r
226#define EFI_SAL_ST_HEADER_SIGNATURE "SST_"\r
227#define EFI_SAL_REVISION 0x0300\r
228//\r
229// SAL System Types\r
230//\r
231#define EFI_SAL_ST_ENTRY_POINT 0\r
232#define EFI_SAL_ST_MEMORY_DESCRIPTOR 1\r
233#define EFI_SAL_ST_PLATFORM_FEATURES 2\r
234#define EFI_SAL_ST_TR_USAGE 3\r
235#define EFI_SAL_ST_PTC 4\r
236#define EFI_SAL_ST_AP_WAKEUP 5\r
237\r
238#pragma pack(1)\r
239typedef struct {\r
240 UINT8 Type; // Type == 0\r
241 UINT8 Reserved[7];\r
242 UINT64 PalProcEntry;\r
243 UINT64 SalProcEntry;\r
244 UINT64 SalGlobalDataPointer;\r
245 UINT64 Reserved2[2];\r
246} SAL_ST_ENTRY_POINT_DESCRIPTOR;\r
247\r
248//\r
249// Not needed for Itanium-based OS boot\r
250//\r
251typedef struct {\r
252 UINT8 Type; // Type == 1\r
253 UINT8 NeedVirtualRegistration;\r
254 UINT8 MemoryAttributes;\r
255 UINT8 PageAccessRights;\r
256 UINT8 SupportedAttributes;\r
257 UINT8 Reserved;\r
258 UINT8 MemoryType;\r
259 UINT8 MemoryUsage;\r
260 UINT64 PhysicalMemoryAddress;\r
261 UINT32 Length;\r
262 UINT32 Reserved1;\r
263 UINT64 OemReserved;\r
264} SAL_ST_MEMORY_DESCRIPTOR_ENTRY;\r
265\r
266#pragma pack()\r
267//\r
268// Memory Attributes\r
269//\r
270#define SAL_MDT_ATTRIB_WB 0x00\r
271//\r
272// #define SAL_MDT_ATTRIB_UC 0x02\r
273//\r
274#define SAL_MDT_ATTRIB_UC 0x04\r
275#define SAL_MDT_ATTRIB_UCE 0x05\r
276#define SAL_MDT_ATTRIB_WC 0x06\r
277\r
278//\r
279// Supported memory Attributes\r
280//\r
281#define SAL_MDT_SUPPORT_WB 0x1\r
282#define SAL_MDT_SUPPORT_UC 0x2\r
283#define SAL_MDT_SUPPORT_UCE 0x4\r
284#define SAL_MDT_SUPPORT_WC 0x8\r
285\r
286//\r
287// Virtual address registration\r
288//\r
289#define SAL_MDT_NO_VA 0x00\r
290#define SAL_MDT_NEED_VA 0x01\r
291//\r
292// MemoryType info\r
293//\r
294#define SAL_REGULAR_MEMORY 0x0000\r
295#define SAL_MMIO_MAPPING 0x0001\r
296#define SAL_SAPIC_IPI_BLOCK 0x0002\r
297#define SAL_IO_PORT_MAPPING 0x0003\r
298#define SAL_FIRMWARE_MEMORY 0x0004\r
299#define SAL_BLACK_HOLE 0x000A\r
300//\r
301// Memory Usage info\r
302//\r
303#define SAL_MDT_USAGE_UNSPECIFIED 0x00\r
304#define SAL_PAL_CODE 0x01\r
305#define SAL_BOOTSERVICE_CODE 0x02\r
306#define SAL_BOOTSERVICE_DATA 0x03\r
307#define SAL_RUNTIMESERVICE_CODE 0x04\r
308#define SAL_RUNTIMESERVICE_DATA 0x05\r
309#define SAL_IA32_OPTIONROM 0x06\r
310#define SAL_IA32_SYSTEMROM 0x07\r
311#define SAL_PMI_CODE 0x0a\r
312#define SAL_PMI_DATA 0x0b\r
313\r
314#pragma pack(1)\r
315typedef struct {\r
316 UINT8 Type; // Type == 2\r
317 UINT8 PlatformFeatures;\r
318 UINT8 Reserved[14];\r
319} SAL_ST_PLATFORM_FEATURES;\r
320#pragma pack()\r
321\r
322#define SAL_PLAT_FEAT_BUS_LOCK 0x01\r
323#define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02\r
324#define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04\r
325\r
326#pragma pack(1)\r
327typedef struct {\r
328 UINT8 Type; // Type == 3\r
329 UINT8 TRType;\r
330 UINT8 TRNumber;\r
331 UINT8 Reserved[5];\r
332 UINT64 VirtualAddress;\r
333 UINT64 EncodedPageSize;\r
334 UINT64 Reserved1;\r
335} SAL_ST_TR_DECRIPTOR;\r
336#pragma pack()\r
337\r
338#define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00\r
339#define EFI_SAL_ST_TR_USAGE_DATA 01\r
340\r
341#pragma pack(1)\r
342typedef struct {\r
343 UINT64 NumberOfProcessors;\r
344 UINT64 LocalIDRegister;\r
345} SAL_COHERENCE_DOMAIN_INFO;\r
346#pragma pack()\r
347\r
348#pragma pack(1)\r
349typedef struct {\r
350 UINT8 Type; // Type == 4\r
351 UINT8 Reserved[3];\r
352 UINT32 NumberOfDomains;\r
353 SAL_COHERENCE_DOMAIN_INFO *DomainInformation;\r
354} SAL_ST_CACHE_COHERENCE_DECRIPTOR;\r
355#pragma pack()\r
356\r
357#pragma pack(1)\r
358typedef struct {\r
359 UINT8 Type; // Type == 5\r
360 UINT8 WakeUpType;\r
361 UINT8 Reserved[6];\r
362 UINT64 ExternalInterruptVector;\r
363} SAL_ST_AP_WAKEUP_DECRIPTOR;\r
364#pragma pack()\r
365//\r
366// FIT Entry\r
367//\r
368#define EFI_SAL_FIT_ENTRY_PTR (0x100000000 - 32) // 4GB - 24\r
369#define EFI_SAL_FIT_PALA_ENTRY (0x100000000 - 48) // 4GB - 32\r
370#define EFI_SAL_FIT_PALB_TYPE 01\r
371\r
372typedef struct {\r
373 UINT64 Address;\r
374 UINT8 Size[3];\r
375 UINT8 Reserved;\r
376 UINT16 Revision;\r
377 UINT8 Type : 7;\r
378 UINT8 CheckSumValid : 1;\r
379 UINT8 CheckSum;\r
380} EFI_SAL_FIT_ENTRY;\r
381\r
382//\r
383// SAL Common Record Header\r
384//\r
385typedef struct {\r
386 UINT16 Length;\r
387 UINT8 Data[1024];\r
388} SAL_OEM_DATA;\r
389\r
390typedef struct {\r
391 UINT8 Seconds;\r
392 UINT8 Minutes;\r
393 UINT8 Hours;\r
394 UINT8 Reserved;\r
395 UINT8 Day;\r
396 UINT8 Month;\r
397 UINT8 Year;\r
398 UINT8 Century;\r
399} SAL_TIME_STAMP;\r
400\r
401typedef struct {\r
402 UINT64 RecordId;\r
403 UINT16 Revision;\r
404 UINT8 ErrorSeverity;\r
405 UINT8 ValidationBits;\r
406 UINT32 RecordLength;\r
407 SAL_TIME_STAMP TimeStamp;\r
408 UINT8 OemPlatformId[16];\r
409} SAL_RECORD_HEADER;\r
410\r
411typedef struct {\r
412 GUID Guid;\r
413 UINT16 Revision;\r
414 UINT8 ErrorRecoveryInfo;\r
415 UINT8 Reserved;\r
416 UINT32 SectionLength;\r
417} SAL_SEC_HEADER;\r
418\r
419//\r
420// SAL Processor Record\r
421//\r
422#define SAL_PROCESSOR_ERROR_RECORD_INFO \\r
423 { \\r
424 0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
425 }\r
426\r
427#define CHECK_INFO_VALID_BIT_MASK 0x1\r
428#define REQUESTOR_ID_VALID_BIT_MASK 0x2\r
429#define RESPONDER_ID_VALID_BIT_MASK 0x4\r
430#define TARGER_ID_VALID_BIT_MASK 0x8\r
431#define PRECISE_IP_VALID_BIT_MASK 0x10\r
432\r
433typedef struct {\r
434 UINT64 InfoValid : 1;\r
435 UINT64 ReqValid : 1;\r
436 UINT64 RespValid : 1;\r
437 UINT64 TargetValid : 1;\r
438 UINT64 IpValid : 1;\r
439 UINT64 Reserved : 59;\r
440 UINT64 Info;\r
441 UINT64 Req;\r
442 UINT64 Resp;\r
443 UINT64 Target;\r
444 UINT64 Ip;\r
445} MOD_ERROR_INFO;\r
446\r
447typedef struct {\r
448 UINT8 CpuidInfo[40];\r
449 UINT8 Reserved;\r
450} CPUID_INFO;\r
451\r
452typedef struct {\r
453 UINT64 FrLow;\r
454 UINT64 FrHigh;\r
455} FR_STRUCT;\r
456\r
457#define MIN_STATE_VALID_BIT_MASK 0x1\r
458#define BR_VALID_BIT_MASK 0x2\r
459#define CR_VALID_BIT_MASK 0x4\r
460#define AR_VALID_BIT_MASK 0x8\r
461#define RR_VALID_BIT_MASK 0x10\r
462#define FR_VALID_BIT_MASK 0x20\r
463\r
464typedef struct {\r
465 UINT64 ValidFieldBits;\r
466 UINT8 MinStateInfo[1024];\r
467 UINT64 Br[8];\r
468 UINT64 Cr[128];\r
469 UINT64 Ar[128];\r
470 UINT64 Rr[8];\r
471 FR_STRUCT Fr[128];\r
472} PSI_STATIC_STRUCT;\r
473\r
474#define PROC_ERROR_MAP_VALID_BIT_MASK 0x1\r
475#define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2\r
476#define PROC_CR_LID_VALID_BIT_MASK 0x4\r
477#define PROC_STATIC_STRUCT_VALID_BIT_MASK 0x8\r
478#define CPU_INFO_VALID_BIT_MASK 0x1000000\r
479\r
480typedef struct {\r
481 SAL_SEC_HEADER SectionHeader;\r
482 UINT64 ValidationBits;\r
483 UINT64 ProcErrorMap;\r
484 UINT64 ProcStateParameter;\r
485 UINT64 ProcCrLid;\r
486 MOD_ERROR_INFO CacheError[15];\r
487 MOD_ERROR_INFO TlbError[15];\r
488 MOD_ERROR_INFO BusError[15];\r
489 MOD_ERROR_INFO RegFileCheck[15];\r
490 MOD_ERROR_INFO MsCheck[15];\r
491 CPUID_INFO CpuInfo;\r
492 PSI_STATIC_STRUCT PsiValidData;\r
493} SAL_PROCESSOR_ERROR_RECORD;\r
494\r
495//\r
496// Sal Platform memory Error Record\r
497//\r
498#define SAL_MEMORY_ERROR_RECORD_INFO \\r
499 { \\r
500 0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
501 }\r
502\r
503#define MEMORY_ERROR_STATUS_VALID_BIT_MASK 0x1\r
504#define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK 0x2\r
505#define MEMORY_ADDR_BIT_MASK 0x4\r
506#define MEMORY_NODE_VALID_BIT_MASK 0x8\r
507#define MEMORY_CARD_VALID_BIT_MASK 0x10\r
508#define MEMORY_MODULE_VALID_BIT_MASK 0x20\r
509#define MEMORY_BANK_VALID_BIT_MASK 0x40\r
510#define MEMORY_DEVICE_VALID_BIT_MASK 0x80\r
511#define MEMORY_ROW_VALID_BIT_MASK 0x100\r
512#define MEMORY_COLUMN_VALID_BIT_MASK 0x200\r
513#define MEMORY_BIT_POSITION_VALID_BIT_MASK 0x400\r
514#define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x800\r
515#define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x1000\r
516#define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK 0x2000\r
517#define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK 0x4000\r
518#define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK 0x8000\r
519#define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x10000\r
520\r
521typedef struct {\r
522 SAL_SEC_HEADER SectionHeader;\r
523 UINT64 ValidationBits;\r
524 UINT64 MemErrorStatus;\r
525 UINT64 MemPhysicalAddress;\r
526 UINT64 MemPhysicalAddressMask;\r
527 UINT16 MemNode;\r
528 UINT16 MemCard;\r
529 UINT16 MemModule;\r
530 UINT16 MemBank;\r
531 UINT16 MemDevice;\r
532 UINT16 MemRow;\r
533 UINT16 MemColumn;\r
534 UINT16 MemBitPosition;\r
535 UINT64 ModRequestorId;\r
536 UINT64 ModResponderId;\r
537 UINT64 ModTargetId;\r
538 UINT64 BusSpecificData;\r
539 UINT8 MemPlatformOemId[16];\r
540} SAL_MEMORY_ERROR_RECORD;\r
541\r
542//\r
543// PCI BUS Errors\r
544//\r
545#define SAL_PCI_BUS_ERROR_RECORD_INFO \\r
546 { \\r
547 0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
548 }\r
549\r
550#define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK 0x1\r
551#define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK 0x2\r
552#define PCI_BUS_ID_VALID_BIT_MASK 0x4\r
553#define PCI_BUS_ADDRESS_VALID_BIT_MASK 0x8\r
554#define PCI_BUS_DATA_VALID_BIT_MASK 0x10\r
555#define PCI_BUS_CMD_VALID_BIT_MASK 0x20\r
556#define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK 0x40\r
557#define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK 0x80\r
558#define PCI_BUS_TARGET_VALID_BIT_MASK 0x100\r
559#define PCI_BUS_OEM_ID_VALID_BIT_MASK 0x200\r
560#define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK 0x400\r
561\r
562typedef struct {\r
563 UINT8 BusNumber;\r
564 UINT8 SegmentNumber;\r
565} PCI_BUS_ID;\r
566\r
567typedef struct {\r
568 SAL_SEC_HEADER SectionHeader;\r
569 UINT64 ValidationBits;\r
570 UINT64 PciBusErrorStatus;\r
571 UINT16 PciBusErrorType;\r
572 PCI_BUS_ID PciBusId;\r
573 UINT32 Reserved;\r
574 UINT64 PciBusAddress;\r
575 UINT64 PciBusData;\r
576 UINT64 PciBusCommand;\r
577 UINT64 PciBusRequestorId;\r
578 UINT64 PciBusResponderId;\r
579 UINT64 PciBusTargetId;\r
580 UINT8 PciBusOemId[16];\r
581} SAL_PCI_BUS_ERROR_RECORD;\r
582\r
583//\r
584// PCI Component Errors\r
585//\r
586#define SAL_PCI_COMP_ERROR_RECORD_INFO \\r
587 { \\r
588 0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
589 }\r
590\r
591#define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK 0x1\r
592#define PCI_COMP_INFO_VALID_BIT_MASK 0x2\r
593#define PCI_COMP_MEM_NUM_VALID_BIT_MASK 0x4\r
594#define PCI_COMP_IO_NUM_VALID_BIT_MASK 0x8\r
595#define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK 0x10\r
596#define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20\r
597\r
598typedef struct {\r
599 UINT16 VendorId;\r
600 UINT16 DeviceId;\r
601 UINT8 ClassCode[3];\r
602 UINT8 FunctionNumber;\r
603 UINT8 DeviceNumber;\r
604 UINT8 BusNumber;\r
605 UINT8 SegmentNumber;\r
606 UINT8 Reserved[5];\r
607} PCI_COMP_INFO;\r
608\r
609typedef struct {\r
610 SAL_SEC_HEADER SectionHeader;\r
611 UINT64 ValidationBits;\r
612 UINT64 PciComponentErrorStatus;\r
613 PCI_COMP_INFO PciComponentInfo;\r
614 UINT32 PciComponentMemNum;\r
615 UINT32 PciComponentIoNum;\r
616 UINT8 PciBusOemId[16];\r
617} SAL_PCI_COMPONENT_ERROR_RECORD;\r
618\r
619//\r
620// Sal Device Errors Info.\r
621//\r
622#define SAL_DEVICE_ERROR_RECORD_INFO \\r
623 { \\r
624 0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
625 }\r
626\r
627#define SEL_RECORD_ID_VALID_BIT_MASK 0x1;\r
628#define SEL_RECORD_TYPE_VALID_BIT_MASK 0x2;\r
629#define SEL_GENERATOR_ID_VALID_BIT_MASK 0x4;\r
630#define SEL_EVM_REV_VALID_BIT_MASK 0x8;\r
631#define SEL_SENSOR_TYPE_VALID_BIT_MASK 0x10;\r
632#define SEL_SENSOR_NUM_VALID_BIT_MASK 0x20;\r
633#define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;\r
634#define SEL_EVENT_DATA1_VALID_BIT_MASK 0x80;\r
635#define SEL_EVENT_DATA2_VALID_BIT_MASK 0x100;\r
636#define SEL_EVENT_DATA3_VALID_BIT_MASK 0x200;\r
637\r
638typedef struct {\r
639 SAL_SEC_HEADER SectionHeader;\r
640 UINT64 ValidationBits;\r
641 UINT16 SelRecordId;\r
642 UINT8 SelRecordType;\r
643 UINT32 TimeStamp;\r
644 UINT16 GeneratorId;\r
645 UINT8 EvmRevision;\r
646 UINT8 SensorType;\r
647 UINT8 SensorNum;\r
648 UINT8 EventDirType;\r
649 UINT8 Data1;\r
650 UINT8 Data2;\r
651 UINT8 Data3;\r
652} SAL_DEVICE_ERROR_RECORD;\r
653\r
654//\r
655// Sal SMBIOS Device Errors Info.\r
656//\r
657#define SAL_SMBIOS_ERROR_RECORD_INFO \\r
658 { \\r
659 0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
660 }\r
661\r
662#define SMBIOS_EVENT_TYPE_VALID_BIT_MASK 0x1\r
663#define SMBIOS_LENGTH_VALID_BIT_MASK 0x2\r
664#define SMBIOS_TIME_STAMP_VALID_BIT_MASK 0x4\r
665#define SMBIOS_DATA_VALID_BIT_MASK 0x8\r
666\r
667typedef struct {\r
668 SAL_SEC_HEADER SectionHeader;\r
669 UINT64 ValidationBits;\r
670 UINT8 SmbiosEventType;\r
671 UINT8 SmbiosLength;\r
672 UINT8 SmbiosBcdTimeStamp[6];\r
673} SAL_SMBIOS_DEVICE_ERROR_RECORD;\r
674\r
675//\r
676// Sal Platform Specific Errors Info.\r
677//\r
678#define SAL_PLATFORM_ERROR_RECORD_INFO \\r
679 { \\r
680 0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
681 }\r
682\r
683#define PLATFORM_ERROR_STATUS_VALID_BIT_MASK 0x1\r
684#define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x2\r
685#define PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x4\r
686#define PLATFORM_TARGET_VALID_BIT_MASK 0x8\r
687#define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK 0x10\r
688#define PLATFORM_OEM_ID_VALID_BIT_MASK 0x20\r
689#define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40\r
690#define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80\r
691\r
692typedef struct {\r
693 SAL_SEC_HEADER SectionHeader;\r
694 UINT64 ValidationBits;\r
695 UINT64 PlatformErrorStatus;\r
696 UINT64 PlatformRequestorId;\r
697 UINT64 PlatformResponderId;\r
698 UINT64 PlatformTargetId;\r
699 UINT64 PlatformBusSpecificData;\r
700 UINT8 OemComponentId[16];\r
701} SAL_PLATFORM_SPECIFIC_ERROR_RECORD;\r
702\r
703//\r
704// Union of all the possible Sal Record Types\r
705//\r
706typedef union {\r
707 SAL_RECORD_HEADER *RecordHeader;\r
708 SAL_PROCESSOR_ERROR_RECORD *SalProcessorRecord;\r
709 SAL_PCI_BUS_ERROR_RECORD *SalPciBusRecord;\r
710 SAL_PCI_COMPONENT_ERROR_RECORD *SalPciComponentRecord;\r
711 SAL_DEVICE_ERROR_RECORD *ImpiRecord;\r
712 SAL_SMBIOS_DEVICE_ERROR_RECORD *SmbiosRecord;\r
713 SAL_PLATFORM_SPECIFIC_ERROR_RECORD *PlatformRecord;\r
714 SAL_MEMORY_ERROR_RECORD *MemoryRecord;\r
715 UINT8 *Raw;\r
716} SAL_ERROR_RECORDS_POINTERS;\r
717\r
718#pragma pack()\r
719\r
720#endif\r
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