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Fix ECC issue.
[mirror_edk2.git] / MdePkg / Include / IndustryStandard / Sal.h
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540dfc26 1/** @file\r
2 Main SAL API's defined in SAL 3.0 specification. \r
3\r
4 Copyright (c) 2006, Intel Corporation \r
5 All rights reserved. This program and the accompanying materials \r
6 are licensed and made available under the terms and conditions of the BSD License \r
7 which accompanies this distribution. The full text of the license may be found at \r
8 http://opensource.org/licenses/bsd-license.php \r
9\r
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
12\r
540dfc26 13**/\r
14\r
15#ifndef __SAL_API_H__\r
16#define __SAL_API_H__\r
17\r
1bc5d021 18///\r
19/// FIT Types \r
20/// Table 2-2 of Intel Itanium Processor Family System Abstraction Layer Specification December 2003\r
21///\r
540dfc26 22#define EFI_SAL_FIT_FIT_HEADER_TYPE 0x00\r
23#define EFI_SAL_FIT_PAL_B_TYPE 0x01\r
1bc5d021 24\r
25///\r
26/// type from 0x02 to 0x0E is reserved.\r
27///\r
540dfc26 28#define EFI_SAL_FIT_PAL_A_TYPE 0x0F\r
1bc5d021 29\r
30///\r
31/// OEM-defined type range is from 0x10 to 0x7E. Here we defined the PEI_CORE type as 0x10\r
32///\r
540dfc26 33#define EFI_SAL_FIT_PEI_CORE_TYPE 0x10\r
34#define EFI_SAL_FIT_UNUSED_TYPE 0x7F\r
35\r
1bc5d021 36///\r
37/// EFI_SAL_STATUS \r
38///\r
540dfc26 39typedef UINTN EFI_SAL_STATUS;\r
40\r
41#define EFI_SAL_SUCCESS ((EFI_SAL_STATUS) 0)\r
42#define EFI_SAL_MORE_RECORDS ((EFI_SAL_STATUS) 3)\r
43#define EFI_SAL_NOT_IMPLEMENTED ((EFI_SAL_STATUS) - 1)\r
44#define EFI_SAL_INVALID_ARGUMENT ((EFI_SAL_STATUS) - 2)\r
45#define EFI_SAL_ERROR ((EFI_SAL_STATUS) - 3)\r
46#define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)\r
47#define EFI_SAL_NO_INFORMATION ((EFI_SAL_STATUS) - 5)\r
48#define EFI_SAL_NOT_ENOUGH_SCRATCH ((EFI_SAL_STATUS) - 9)\r
49\r
50//\r
51// Return values from SAL\r
52//\r
53typedef struct {\r
54 EFI_SAL_STATUS Status; // register r8\r
55 UINTN r9;\r
56 UINTN r10;\r
57 UINTN r11;\r
58} SAL_RETURN_REGS;\r
59\r
1bc5d021 60///\r
61/// Delivery Mode of IPF CPU.\r
62///\r
540dfc26 63typedef enum {\r
64 EFI_DELIVERY_MODE_INT,\r
65 EFI_DELIVERY_MODE_MPreserved1,\r
66 EFI_DELIVERY_MODE_PMI,\r
67 EFI_DELIVERY_MODE_MPreserved2,\r
68 EFI_DELIVERY_MODE_NMI,\r
69 EFI_DELIVERY_MODE_INIT,\r
70 EFI_DELIVERY_MODE_MPreserved3,\r
71 EFI_DELIVERY_MODE_ExtINT\r
72} EFI_DELIVERY_MODE;\r
73\r
74typedef SAL_RETURN_REGS (EFIAPI *SAL_PROC)\r
75 (\r
76 IN UINT64 FunctionId,\r
77 IN UINT64 Arg2,\r
78 IN UINT64 Arg3,\r
79 IN UINT64 Arg4,\r
80 IN UINT64 Arg5,\r
81 IN UINT64 Arg6,\r
82 IN UINT64 Arg7,\r
83 IN UINT64 Arg8\r
84 );\r
85\r
86//\r
87// SAL Procedure FunctionId definition\r
88//\r
89#define EFI_SAL_SET_VECTORS 0x01000000\r
90#define EFI_SAL_GET_STATE_INFO 0x01000001\r
91#define EFI_SAL_GET_STATE_INFO_SIZE 0x01000002\r
92#define EFI_SAL_CLEAR_STATE_INFO 0x01000003\r
93#define EFI_SAL_MC_RENDEZ 0x01000004\r
94#define EFI_SAL_MC_SET_PARAMS 0x01000005\r
95#define EFI_SAL_REGISTER_PHYSICAL_ADDR 0x01000006\r
96#define EFI_SAL_CACHE_FLUSH 0x01000008\r
97#define EFI_SAL_CACHE_INIT 0x01000009\r
98#define EFI_SAL_PCI_CONFIG_READ 0x01000010\r
99#define EFI_SAL_PCI_CONFIG_WRITE 0x01000011\r
100#define EFI_SAL_FREQ_BASE 0x01000012\r
9c8403b3 101#define EFI_SAL_PHYSICAL_ID_INFO 0x01000013\r
540dfc26 102#define EFI_SAL_UPDATE_PAL 0x01000020\r
103\r
104#define EFI_SAL_FUNCTION_ID_MASK 0x0000ffff\r
105#define EFI_SAL_MAX_SAL_FUNCTION_ID 0x00000021\r
106\r
107//\r
108// SAL Procedure parameter definitions\r
109// Not much point in using typedefs or enums because all params\r
110// are UINT64 and the entry point is common\r
111//\r
112// EFI_SAL_SET_VECTORS\r
113//\r
114#define EFI_SAL_SET_MCA_VECTOR 0x0\r
115#define EFI_SAL_SET_INIT_VECTOR 0x1\r
116#define EFI_SAL_SET_BOOT_RENDEZ_VECTOR 0x2\r
117\r
118typedef struct {\r
119 UINT64 Length : 32;\r
120 UINT64 ChecksumValid : 1;\r
121 UINT64 Reserved1 : 7;\r
122 UINT64 ByteChecksum : 8;\r
123 UINT64 Reserved2 : 16;\r
124} SAL_SET_VECTORS_CS_N;\r
125\r
126//\r
127// EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE,\r
128// EFI_SAL_CLEAR_STATE_INFO\r
129//\r
130#define EFI_SAL_MCA_STATE_INFO 0x0\r
131#define EFI_SAL_INIT_STATE_INFO 0x1\r
132#define EFI_SAL_CMC_STATE_INFO 0x2\r
133#define EFI_SAL_CP_STATE_INFO 0x3\r
134\r
135//\r
136// EFI_SAL_MC_SET_PARAMS\r
137//\r
138#define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1\r
139#define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2\r
140#define EFI_SAL_MC_SET_CPE_PARAM 0x3\r
141\r
142#define EFI_SAL_MC_SET_INTR_PARAM 0x1\r
143#define EFI_SAL_MC_SET_MEM_PARAM 0x2\r
144\r
145//\r
146// EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR\r
147//\r
148#define EFI_SAL_REGISTER_PAL_ADDR 0x0\r
149\r
150//\r
151// EFI_SAL_CACHE_FLUSH\r
152//\r
153#define EFI_SAL_FLUSH_I_CACHE 0x01\r
154#define EFI_SAL_FLUSH_D_CACHE 0x02\r
155#define EFI_SAL_FLUSH_BOTH_CACHE 0x03\r
156#define EFI_SAL_FLUSH_MAKE_COHERENT 0x04\r
157\r
158//\r
159// EFI_SAL_PCI_CONFIG_READ, EFI_SAL_PCI_CONFIG_WRITE\r
160//\r
161#define EFI_SAL_PCI_CONFIG_ONE_BYTE 0x1\r
162#define EFI_SAL_PCI_CONFIG_TWO_BYTES 0x2\r
163#define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4\r
164\r
165typedef struct {\r
166 UINT64 Register : 8;\r
167 UINT64 Function : 3;\r
168 UINT64 Device : 5;\r
169 UINT64 Bus : 8;\r
170 UINT64 Segment : 8;\r
171 UINT64 Reserved : 32;\r
172} SAL_PCI_ADDRESS;\r
173\r
174//\r
175// EFI_SAL_FREQ_BASE\r
176//\r
177#define EFI_SAL_CPU_INPUT_FREQ_BASE 0x0\r
178#define EFI_SAL_PLATFORM_IT_FREQ_BASE 0x1\r
179#define EFI_SAL_PLATFORM_RTC_FREQ_BASE 0x2\r
180\r
181//\r
182// EFI_SAL_UPDATE_PAL\r
183//\r
184#define EFI_SAL_UPDATE_BAD_PAL_VERSION ((UINT64) -1)\r
185#define EFI_SAL_UPDATE_PAL_AUTH_FAIL ((UINT64) -2)\r
186#define EFI_SAL_UPDATE_PAL_BAD_TYPE ((UINT64) -3)\r
187#define EFI_SAL_UPDATE_PAL_READONLY ((UINT64) -4)\r
188#define EFI_SAL_UPDATE_PAL_WRITE_FAIL ((UINT64) -10)\r
189#define EFI_SAL_UPDATE_PAL_ERASE_FAIL ((UINT64) -11)\r
190#define EFI_SAL_UPDATE_PAL_READ_FAIL ((UINT64) -12)\r
191#define EFI_SAL_UPDATE_PAL_CANT_FIT ((UINT64) -13)\r
192\r
193typedef struct {\r
194 UINT32 Size;\r
195 UINT32 MmddyyyyDate;\r
196 UINT16 Version;\r
197 UINT8 Type;\r
198 UINT8 Reserved[5];\r
199 UINT64 FwVendorId;\r
200} SAL_UPDATE_PAL_DATA_BLOCK;\r
201\r
202typedef struct _SAL_UPDATE_PAL_INFO_BLOCK {\r
203 struct _SAL_UPDATE_PAL_INFO_BLOCK *Next;\r
204 struct SAL_UPDATE_PAL_DATA_BLOCK *DataBlock;\r
205 UINT8 StoreChecksum;\r
206 UINT8 Reserved[15];\r
207} SAL_UPDATE_PAL_INFO_BLOCK;\r
208\r
209//\r
210// SAL System Table Definitions\r
211//\r
212#pragma pack(1)\r
213typedef struct {\r
214 UINT32 Signature;\r
215 UINT32 Length;\r
216 UINT16 SalRevision;\r
217 UINT16 EntryCount;\r
218 UINT8 CheckSum;\r
219 UINT8 Reserved[7];\r
220 UINT16 SalAVersion;\r
221 UINT16 SalBVersion;\r
222 UINT8 OemId[32];\r
223 UINT8 ProductId[32];\r
224 UINT8 Reserved2[8];\r
225} SAL_SYSTEM_TABLE_HEADER;\r
226#pragma pack()\r
227\r
228#define EFI_SAL_ST_HEADER_SIGNATURE "SST_"\r
229#define EFI_SAL_REVISION 0x0300\r
230//\r
231// SAL System Types\r
232//\r
233#define EFI_SAL_ST_ENTRY_POINT 0\r
234#define EFI_SAL_ST_MEMORY_DESCRIPTOR 1\r
235#define EFI_SAL_ST_PLATFORM_FEATURES 2\r
236#define EFI_SAL_ST_TR_USAGE 3\r
237#define EFI_SAL_ST_PTC 4\r
238#define EFI_SAL_ST_AP_WAKEUP 5\r
239\r
809177f5 240//\r
241// SAL System Type Sizes\r
242//\r
243#define EFI_SAL_ST_ENTRY_POINT_SIZE 48\r
244#define EFI_SAL_ST_MEMORY_DESCRIPTOR_SIZE 32\r
245#define EFI_SAL_ST_PLATFORM_FEATURES_SIZE 16\r
246#define EFI_SAL_ST_TR_USAGE_SIZE 32\r
247#define EFI_SAL_ST_PTC_SIZE 16\r
248#define EFI_SAL_ST_AP_WAKEUP_SIZE 16\r
249\r
540dfc26 250#pragma pack(1)\r
251typedef struct {\r
252 UINT8 Type; // Type == 0\r
253 UINT8 Reserved[7];\r
254 UINT64 PalProcEntry;\r
255 UINT64 SalProcEntry;\r
256 UINT64 SalGlobalDataPointer;\r
257 UINT64 Reserved2[2];\r
258} SAL_ST_ENTRY_POINT_DESCRIPTOR;\r
259\r
540dfc26 260#pragma pack(1)\r
261typedef struct {\r
262 UINT8 Type; // Type == 2\r
263 UINT8 PlatformFeatures;\r
264 UINT8 Reserved[14];\r
265} SAL_ST_PLATFORM_FEATURES;\r
266#pragma pack()\r
267\r
268#define SAL_PLAT_FEAT_BUS_LOCK 0x01\r
269#define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02\r
270#define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04\r
271\r
272#pragma pack(1)\r
273typedef struct {\r
274 UINT8 Type; // Type == 3\r
275 UINT8 TRType;\r
276 UINT8 TRNumber;\r
277 UINT8 Reserved[5];\r
278 UINT64 VirtualAddress;\r
279 UINT64 EncodedPageSize;\r
280 UINT64 Reserved1;\r
281} SAL_ST_TR_DECRIPTOR;\r
282#pragma pack()\r
283\r
284#define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00\r
285#define EFI_SAL_ST_TR_USAGE_DATA 01\r
286\r
287#pragma pack(1)\r
288typedef struct {\r
289 UINT64 NumberOfProcessors;\r
290 UINT64 LocalIDRegister;\r
291} SAL_COHERENCE_DOMAIN_INFO;\r
292#pragma pack()\r
293\r
294#pragma pack(1)\r
295typedef struct {\r
296 UINT8 Type; // Type == 4\r
297 UINT8 Reserved[3];\r
298 UINT32 NumberOfDomains;\r
299 SAL_COHERENCE_DOMAIN_INFO *DomainInformation;\r
300} SAL_ST_CACHE_COHERENCE_DECRIPTOR;\r
301#pragma pack()\r
302\r
303#pragma pack(1)\r
304typedef struct {\r
305 UINT8 Type; // Type == 5\r
306 UINT8 WakeUpType;\r
307 UINT8 Reserved[6];\r
308 UINT64 ExternalInterruptVector;\r
309} SAL_ST_AP_WAKEUP_DECRIPTOR;\r
310#pragma pack()\r
311//\r
312// FIT Entry\r
313//\r
314#define EFI_SAL_FIT_ENTRY_PTR (0x100000000 - 32) // 4GB - 24\r
315#define EFI_SAL_FIT_PALA_ENTRY (0x100000000 - 48) // 4GB - 32\r
316#define EFI_SAL_FIT_PALB_TYPE 01\r
317\r
318typedef struct {\r
319 UINT64 Address;\r
320 UINT8 Size[3];\r
321 UINT8 Reserved;\r
322 UINT16 Revision;\r
323 UINT8 Type : 7;\r
324 UINT8 CheckSumValid : 1;\r
325 UINT8 CheckSum;\r
326} EFI_SAL_FIT_ENTRY;\r
327\r
328//\r
329// SAL Common Record Header\r
330//\r
331typedef struct {\r
332 UINT16 Length;\r
333 UINT8 Data[1024];\r
334} SAL_OEM_DATA;\r
335\r
336typedef struct {\r
337 UINT8 Seconds;\r
338 UINT8 Minutes;\r
339 UINT8 Hours;\r
340 UINT8 Reserved;\r
341 UINT8 Day;\r
342 UINT8 Month;\r
343 UINT8 Year;\r
344 UINT8 Century;\r
345} SAL_TIME_STAMP;\r
346\r
347typedef struct {\r
348 UINT64 RecordId;\r
349 UINT16 Revision;\r
350 UINT8 ErrorSeverity;\r
351 UINT8 ValidationBits;\r
352 UINT32 RecordLength;\r
353 SAL_TIME_STAMP TimeStamp;\r
354 UINT8 OemPlatformId[16];\r
355} SAL_RECORD_HEADER;\r
356\r
357typedef struct {\r
358 GUID Guid;\r
359 UINT16 Revision;\r
360 UINT8 ErrorRecoveryInfo;\r
361 UINT8 Reserved;\r
362 UINT32 SectionLength;\r
363} SAL_SEC_HEADER;\r
364\r
365//\r
366// SAL Processor Record\r
367//\r
368#define SAL_PROCESSOR_ERROR_RECORD_INFO \\r
369 { \\r
370 0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
371 }\r
372\r
373#define CHECK_INFO_VALID_BIT_MASK 0x1\r
374#define REQUESTOR_ID_VALID_BIT_MASK 0x2\r
375#define RESPONDER_ID_VALID_BIT_MASK 0x4\r
376#define TARGER_ID_VALID_BIT_MASK 0x8\r
377#define PRECISE_IP_VALID_BIT_MASK 0x10\r
378\r
379typedef struct {\r
380 UINT64 InfoValid : 1;\r
381 UINT64 ReqValid : 1;\r
382 UINT64 RespValid : 1;\r
383 UINT64 TargetValid : 1;\r
384 UINT64 IpValid : 1;\r
385 UINT64 Reserved : 59;\r
386 UINT64 Info;\r
387 UINT64 Req;\r
388 UINT64 Resp;\r
389 UINT64 Target;\r
390 UINT64 Ip;\r
391} MOD_ERROR_INFO;\r
392\r
393typedef struct {\r
394 UINT8 CpuidInfo[40];\r
395 UINT8 Reserved;\r
396} CPUID_INFO;\r
397\r
398typedef struct {\r
399 UINT64 FrLow;\r
400 UINT64 FrHigh;\r
401} FR_STRUCT;\r
402\r
403#define MIN_STATE_VALID_BIT_MASK 0x1\r
404#define BR_VALID_BIT_MASK 0x2\r
405#define CR_VALID_BIT_MASK 0x4\r
406#define AR_VALID_BIT_MASK 0x8\r
407#define RR_VALID_BIT_MASK 0x10\r
408#define FR_VALID_BIT_MASK 0x20\r
409\r
410typedef struct {\r
411 UINT64 ValidFieldBits;\r
412 UINT8 MinStateInfo[1024];\r
413 UINT64 Br[8];\r
414 UINT64 Cr[128];\r
415 UINT64 Ar[128];\r
416 UINT64 Rr[8];\r
417 FR_STRUCT Fr[128];\r
418} PSI_STATIC_STRUCT;\r
419\r
420#define PROC_ERROR_MAP_VALID_BIT_MASK 0x1\r
421#define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2\r
422#define PROC_CR_LID_VALID_BIT_MASK 0x4\r
423#define PROC_STATIC_STRUCT_VALID_BIT_MASK 0x8\r
424#define CPU_INFO_VALID_BIT_MASK 0x1000000\r
425\r
426typedef struct {\r
427 SAL_SEC_HEADER SectionHeader;\r
428 UINT64 ValidationBits;\r
429 UINT64 ProcErrorMap;\r
430 UINT64 ProcStateParameter;\r
431 UINT64 ProcCrLid;\r
432 MOD_ERROR_INFO CacheError[15];\r
433 MOD_ERROR_INFO TlbError[15];\r
434 MOD_ERROR_INFO BusError[15];\r
435 MOD_ERROR_INFO RegFileCheck[15];\r
436 MOD_ERROR_INFO MsCheck[15];\r
437 CPUID_INFO CpuInfo;\r
438 PSI_STATIC_STRUCT PsiValidData;\r
439} SAL_PROCESSOR_ERROR_RECORD;\r
440\r
441//\r
442// Sal Platform memory Error Record\r
443//\r
444#define SAL_MEMORY_ERROR_RECORD_INFO \\r
445 { \\r
446 0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
447 }\r
448\r
449#define MEMORY_ERROR_STATUS_VALID_BIT_MASK 0x1\r
450#define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK 0x2\r
451#define MEMORY_ADDR_BIT_MASK 0x4\r
452#define MEMORY_NODE_VALID_BIT_MASK 0x8\r
453#define MEMORY_CARD_VALID_BIT_MASK 0x10\r
454#define MEMORY_MODULE_VALID_BIT_MASK 0x20\r
455#define MEMORY_BANK_VALID_BIT_MASK 0x40\r
456#define MEMORY_DEVICE_VALID_BIT_MASK 0x80\r
457#define MEMORY_ROW_VALID_BIT_MASK 0x100\r
458#define MEMORY_COLUMN_VALID_BIT_MASK 0x200\r
459#define MEMORY_BIT_POSITION_VALID_BIT_MASK 0x400\r
460#define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x800\r
461#define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x1000\r
462#define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK 0x2000\r
463#define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK 0x4000\r
464#define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK 0x8000\r
465#define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x10000\r
466\r
467typedef struct {\r
468 SAL_SEC_HEADER SectionHeader;\r
469 UINT64 ValidationBits;\r
470 UINT64 MemErrorStatus;\r
471 UINT64 MemPhysicalAddress;\r
472 UINT64 MemPhysicalAddressMask;\r
473 UINT16 MemNode;\r
474 UINT16 MemCard;\r
475 UINT16 MemModule;\r
476 UINT16 MemBank;\r
477 UINT16 MemDevice;\r
478 UINT16 MemRow;\r
479 UINT16 MemColumn;\r
480 UINT16 MemBitPosition;\r
481 UINT64 ModRequestorId;\r
482 UINT64 ModResponderId;\r
483 UINT64 ModTargetId;\r
484 UINT64 BusSpecificData;\r
485 UINT8 MemPlatformOemId[16];\r
486} SAL_MEMORY_ERROR_RECORD;\r
487\r
488//\r
489// PCI BUS Errors\r
490//\r
491#define SAL_PCI_BUS_ERROR_RECORD_INFO \\r
492 { \\r
493 0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
494 }\r
495\r
496#define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK 0x1\r
497#define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK 0x2\r
498#define PCI_BUS_ID_VALID_BIT_MASK 0x4\r
499#define PCI_BUS_ADDRESS_VALID_BIT_MASK 0x8\r
500#define PCI_BUS_DATA_VALID_BIT_MASK 0x10\r
501#define PCI_BUS_CMD_VALID_BIT_MASK 0x20\r
502#define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK 0x40\r
503#define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK 0x80\r
504#define PCI_BUS_TARGET_VALID_BIT_MASK 0x100\r
505#define PCI_BUS_OEM_ID_VALID_BIT_MASK 0x200\r
506#define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK 0x400\r
507\r
508typedef struct {\r
509 UINT8 BusNumber;\r
510 UINT8 SegmentNumber;\r
511} PCI_BUS_ID;\r
512\r
513typedef struct {\r
514 SAL_SEC_HEADER SectionHeader;\r
515 UINT64 ValidationBits;\r
516 UINT64 PciBusErrorStatus;\r
517 UINT16 PciBusErrorType;\r
518 PCI_BUS_ID PciBusId;\r
519 UINT32 Reserved;\r
520 UINT64 PciBusAddress;\r
521 UINT64 PciBusData;\r
522 UINT64 PciBusCommand;\r
523 UINT64 PciBusRequestorId;\r
524 UINT64 PciBusResponderId;\r
525 UINT64 PciBusTargetId;\r
526 UINT8 PciBusOemId[16];\r
527} SAL_PCI_BUS_ERROR_RECORD;\r
528\r
529//\r
530// PCI Component Errors\r
531//\r
532#define SAL_PCI_COMP_ERROR_RECORD_INFO \\r
533 { \\r
534 0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
535 }\r
536\r
537#define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK 0x1\r
538#define PCI_COMP_INFO_VALID_BIT_MASK 0x2\r
539#define PCI_COMP_MEM_NUM_VALID_BIT_MASK 0x4\r
540#define PCI_COMP_IO_NUM_VALID_BIT_MASK 0x8\r
541#define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK 0x10\r
542#define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20\r
543\r
544typedef struct {\r
545 UINT16 VendorId;\r
546 UINT16 DeviceId;\r
547 UINT8 ClassCode[3];\r
548 UINT8 FunctionNumber;\r
549 UINT8 DeviceNumber;\r
550 UINT8 BusNumber;\r
551 UINT8 SegmentNumber;\r
552 UINT8 Reserved[5];\r
553} PCI_COMP_INFO;\r
554\r
555typedef struct {\r
556 SAL_SEC_HEADER SectionHeader;\r
557 UINT64 ValidationBits;\r
558 UINT64 PciComponentErrorStatus;\r
559 PCI_COMP_INFO PciComponentInfo;\r
560 UINT32 PciComponentMemNum;\r
561 UINT32 PciComponentIoNum;\r
562 UINT8 PciBusOemId[16];\r
563} SAL_PCI_COMPONENT_ERROR_RECORD;\r
564\r
565//\r
566// Sal Device Errors Info.\r
567//\r
568#define SAL_DEVICE_ERROR_RECORD_INFO \\r
569 { \\r
570 0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
571 }\r
572\r
573#define SEL_RECORD_ID_VALID_BIT_MASK 0x1;\r
574#define SEL_RECORD_TYPE_VALID_BIT_MASK 0x2;\r
575#define SEL_GENERATOR_ID_VALID_BIT_MASK 0x4;\r
576#define SEL_EVM_REV_VALID_BIT_MASK 0x8;\r
577#define SEL_SENSOR_TYPE_VALID_BIT_MASK 0x10;\r
578#define SEL_SENSOR_NUM_VALID_BIT_MASK 0x20;\r
579#define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;\r
580#define SEL_EVENT_DATA1_VALID_BIT_MASK 0x80;\r
581#define SEL_EVENT_DATA2_VALID_BIT_MASK 0x100;\r
582#define SEL_EVENT_DATA3_VALID_BIT_MASK 0x200;\r
583\r
584typedef struct {\r
585 SAL_SEC_HEADER SectionHeader;\r
586 UINT64 ValidationBits;\r
587 UINT16 SelRecordId;\r
588 UINT8 SelRecordType;\r
589 UINT32 TimeStamp;\r
590 UINT16 GeneratorId;\r
591 UINT8 EvmRevision;\r
592 UINT8 SensorType;\r
593 UINT8 SensorNum;\r
594 UINT8 EventDirType;\r
595 UINT8 Data1;\r
596 UINT8 Data2;\r
597 UINT8 Data3;\r
598} SAL_DEVICE_ERROR_RECORD;\r
599\r
600//\r
601// Sal SMBIOS Device Errors Info.\r
602//\r
603#define SAL_SMBIOS_ERROR_RECORD_INFO \\r
604 { \\r
605 0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
606 }\r
607\r
608#define SMBIOS_EVENT_TYPE_VALID_BIT_MASK 0x1\r
609#define SMBIOS_LENGTH_VALID_BIT_MASK 0x2\r
610#define SMBIOS_TIME_STAMP_VALID_BIT_MASK 0x4\r
611#define SMBIOS_DATA_VALID_BIT_MASK 0x8\r
612\r
613typedef struct {\r
614 SAL_SEC_HEADER SectionHeader;\r
615 UINT64 ValidationBits;\r
616 UINT8 SmbiosEventType;\r
617 UINT8 SmbiosLength;\r
618 UINT8 SmbiosBcdTimeStamp[6];\r
619} SAL_SMBIOS_DEVICE_ERROR_RECORD;\r
620\r
1bc5d021 621///\r
622/// Sal Platform Specific Errors Info.\r
623///\r
540dfc26 624#define SAL_PLATFORM_ERROR_RECORD_INFO \\r
625 { \\r
626 0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
627 }\r
628\r
629#define PLATFORM_ERROR_STATUS_VALID_BIT_MASK 0x1\r
630#define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x2\r
631#define PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x4\r
632#define PLATFORM_TARGET_VALID_BIT_MASK 0x8\r
633#define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK 0x10\r
634#define PLATFORM_OEM_ID_VALID_BIT_MASK 0x20\r
635#define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40\r
636#define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80\r
637\r
638typedef struct {\r
639 SAL_SEC_HEADER SectionHeader;\r
640 UINT64 ValidationBits;\r
641 UINT64 PlatformErrorStatus;\r
642 UINT64 PlatformRequestorId;\r
643 UINT64 PlatformResponderId;\r
644 UINT64 PlatformTargetId;\r
645 UINT64 PlatformBusSpecificData;\r
646 UINT8 OemComponentId[16];\r
647} SAL_PLATFORM_SPECIFIC_ERROR_RECORD;\r
648\r
1bc5d021 649///\r
650/// Union of all the possible Sal Record Types\r
651///\r
540dfc26 652typedef union {\r
653 SAL_RECORD_HEADER *RecordHeader;\r
654 SAL_PROCESSOR_ERROR_RECORD *SalProcessorRecord;\r
655 SAL_PCI_BUS_ERROR_RECORD *SalPciBusRecord;\r
656 SAL_PCI_COMPONENT_ERROR_RECORD *SalPciComponentRecord;\r
657 SAL_DEVICE_ERROR_RECORD *ImpiRecord;\r
658 SAL_SMBIOS_DEVICE_ERROR_RECORD *SmbiosRecord;\r
659 SAL_PLATFORM_SPECIFIC_ERROR_RECORD *PlatformRecord;\r
660 SAL_MEMORY_ERROR_RECORD *MemoryRecord;\r
661 UINT8 *Raw;\r
662} SAL_ERROR_RECORDS_POINTERS;\r
663\r
664#pragma pack()\r
665\r
666#endif\r
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