projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 42eedea9 | 1 | /** @file\r |
| 568eb0cb | 2 | This file contains definitions for the SPD fields on an SDRAM.\r |
| 3 | \r | |
| 9df063a0 HT |
4 | Copyright (c) 2007 - 2008, Intel Corporation. All rights reserved.<BR>\r |
| 5 | This program and the accompanying materials \r | |
| 568eb0cb | 6 | are licensed and made available under the terms and conditions of the BSD License \r |
| 7 | which accompanies this distribution. The full text of the license may be found at \r | |
| 8 | http://opensource.org/licenses/bsd-license.php \r | |
| 9 | \r | |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
| 12 | **/\r | |
| 13 | \r | |
| 42eedea9 | 14 | #ifndef _SDRAM_SPD_H_\r |
| 15 | #define _SDRAM_SPD_H_\r | |
| 568eb0cb | 16 | \r |
| 17 | //\r | |
| 18 | // SDRAM SPD field definitions\r | |
| 19 | //\r | |
| 20 | #define SPD_MEMORY_TYPE 2\r | |
| 21 | #define SPD_SDRAM_ROW_ADDR 3\r | |
| 22 | #define SPD_SDRAM_COL_ADDR 4\r | |
| 23 | #define SPD_SDRAM_MODULE_ROWS 5\r | |
| 24 | #define SPD_SDRAM_MODULE_DATA_WIDTH_LSB 6\r | |
| 25 | #define SPD_SDRAM_MODULE_DATA_WIDTH_MSB 7\r | |
| 26 | #define SPD_SDRAM_ECC_SUPPORT 11\r | |
| 27 | #define SPD_SDRAM_REFRESH 12\r | |
| 28 | #define SPD_SDRAM_WIDTH 13\r | |
| 29 | #define SPD_SDRAM_ERROR_WIDTH 14\r | |
| 30 | #define SPD_SDRAM_BURST_LENGTH 16\r | |
| 31 | #define SPD_SDRAM_NO_OF_BANKS 17\r | |
| 32 | #define SPD_SDRAM_CAS_LATENCY 18\r | |
| 33 | #define SPD_SDRAM_MODULE_ATTR 21\r | |
| 34 | \r | |
| 4135253b | 35 | #define SPD_SDRAM_TCLK1_PULSE 9 ///< cycle time for highest cas latency\r |
| 36 | #define SPD_SDRAM_TAC1_PULSE 10 ///< access time for highest cas latency\r | |
| 37 | #define SPD_SDRAM_TCLK2_PULSE 23 ///< cycle time for 2nd highest cas latency\r | |
| 38 | #define SPD_SDRAM_TAC2_PULSE 24 ///< access time for 2nd highest cas latency\r | |
| 39 | #define SPD_SDRAM_TCLK3_PULSE 25 ///< cycle time for 3rd highest cas latency\r | |
| 40 | #define SPD_SDRAM_TAC3_PULSE 26 ///< access time for 3rd highest cas latency\r | |
| 568eb0cb | 41 | #define SPD_SDRAM_MIN_PRECHARGE 27\r |
| 42 | #define SPD_SDRAM_ACTIVE_MIN 28\r | |
| 43 | #define SPD_SDRAM_RAS_CAS 29\r | |
| 44 | #define SPD_SDRAM_RAS_PULSE 30\r | |
| 45 | #define SPD_SDRAM_DENSITY 31\r | |
| 46 | \r | |
| 47 | //\r | |
| 48 | // Memory Type Definitions\r | |
| 49 | //\r | |
| 4135253b | 50 | #define SPD_VAL_SDR_TYPE 4 ///< SDR SDRAM memory\r |
| 51 | #define SPD_VAL_DDR_TYPE 7 ///< DDR SDRAM memory\r | |
| 52 | #define SPD_VAL_DDR2_TYPE 8 ///< DDR2 SDRAM memory\r | |
| 568eb0cb | 53 | //\r |
| 54 | // ECC Type Definitions\r | |
| 55 | //\r | |
| 4135253b | 56 | #define SPD_ECC_TYPE_NONE 0x00 ///< No error checking\r |
| 57 | #define SPD_ECC_TYPE_PARITY 0x01 ///< No error checking\r | |
| 58 | #define SPD_ECC_TYPE_ECC 0x02 ///< Error checking only\r | |
| 568eb0cb | 59 | //\r |
| 60 | // Module Attributes (Bit positions)\r | |
| 61 | //\r | |
| 62 | #define SPD_BUFFERED 0x01\r | |
| 63 | #define SPD_REGISTERED 0x02\r | |
| 64 | \r | |
| 65 | #endif\r |