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6a82ceb6 LG |
1 | /** @file\r |
2 | This file contains definitions for SPD DDR3.\r | |
3 | \r | |
4 | Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r | |
9344f092 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
6a82ceb6 LG |
6 | \r |
7 | @par Revision Reference:\r | |
8 | - Serial Presence Detect (SPD) for DDR3 SDRAM Modules Document Release 6\r | |
9 | http://www.jedec.org/sites/default/files/docs/4_01_02_11R21A.pdf\r | |
10 | **/\r | |
11 | \r | |
12 | #ifndef _SDRAM_SPD_DDR3_H_\r | |
13 | #define _SDRAM_SPD_DDR3_H_\r | |
14 | \r | |
15 | #pragma pack (push, 1)\r | |
16 | \r | |
17 | typedef union {\r | |
18 | struct {\r | |
2f88bd3a MK |
19 | UINT8 BytesUsed : 4; ///< Bits 3:0\r |
20 | UINT8 BytesTotal : 3; ///< Bits 6:4\r | |
21 | UINT8 CrcCoverage : 1; ///< Bits 7:7\r | |
6a82ceb6 | 22 | } Bits;\r |
2f88bd3a | 23 | UINT8 Data;\r |
6a82ceb6 LG |
24 | } SPD3_DEVICE_DESCRIPTION_STRUCT;\r |
25 | \r | |
26 | typedef union {\r | |
27 | struct {\r | |
2f88bd3a MK |
28 | UINT8 Minor : 4; ///< Bits 3:0\r |
29 | UINT8 Major : 4; ///< Bits 7:4\r | |
6a82ceb6 | 30 | } Bits;\r |
2f88bd3a | 31 | UINT8 Data;\r |
6a82ceb6 LG |
32 | } SPD3_REVISION_STRUCT;\r |
33 | \r | |
34 | typedef union {\r | |
35 | struct {\r | |
2f88bd3a | 36 | UINT8 Type : 8; ///< Bits 7:0\r |
6a82ceb6 | 37 | } Bits;\r |
2f88bd3a | 38 | UINT8 Data;\r |
6a82ceb6 LG |
39 | } SPD3_DRAM_DEVICE_TYPE_STRUCT;\r |
40 | \r | |
41 | typedef union {\r | |
42 | struct {\r | |
2f88bd3a MK |
43 | UINT8 ModuleType : 4; ///< Bits 3:0\r |
44 | UINT8 Reserved : 4; ///< Bits 7:4\r | |
6a82ceb6 | 45 | } Bits;\r |
2f88bd3a | 46 | UINT8 Data;\r |
6a82ceb6 LG |
47 | } SPD3_MODULE_TYPE_STRUCT;\r |
48 | \r | |
49 | typedef union {\r | |
50 | struct {\r | |
2f88bd3a MK |
51 | UINT8 Density : 4; ///< Bits 3:0\r |
52 | UINT8 BankAddress : 3; ///< Bits 6:4\r | |
53 | UINT8 Reserved : 1; ///< Bits 7:7\r | |
6a82ceb6 | 54 | } Bits;\r |
2f88bd3a | 55 | UINT8 Data;\r |
6a82ceb6 LG |
56 | } SPD3_SDRAM_DENSITY_BANKS_STRUCT;\r |
57 | \r | |
58 | typedef union {\r | |
59 | struct {\r | |
2f88bd3a MK |
60 | UINT8 ColumnAddress : 3; ///< Bits 2:0\r |
61 | UINT8 RowAddress : 3; ///< Bits 5:3\r | |
62 | UINT8 Reserved : 2; ///< Bits 7:6\r | |
6a82ceb6 | 63 | } Bits;\r |
2f88bd3a | 64 | UINT8 Data;\r |
6a82ceb6 LG |
65 | } SPD3_SDRAM_ADDRESSING_STRUCT;\r |
66 | \r | |
67 | typedef union {\r | |
68 | struct {\r | |
2f88bd3a MK |
69 | UINT8 OperationAt1_50 : 1; ///< Bits 0:0\r |
70 | UINT8 OperationAt1_35 : 1; ///< Bits 1:1\r | |
71 | UINT8 OperationAt1_25 : 1; ///< Bits 2:2\r | |
72 | UINT8 Reserved : 5; ///< Bits 7:3\r | |
6a82ceb6 | 73 | } Bits;\r |
2f88bd3a | 74 | UINT8 Data;\r |
6a82ceb6 LG |
75 | } SPD3_MODULE_NOMINAL_VOLTAGE_STRUCT;\r |
76 | \r | |
77 | typedef union {\r | |
78 | struct {\r | |
2f88bd3a MK |
79 | UINT8 SdramDeviceWidth : 3; ///< Bits 2:0\r |
80 | UINT8 RankCount : 3; ///< Bits 5:3\r | |
81 | UINT8 Reserved : 2; ///< Bits 7:6\r | |
6a82ceb6 | 82 | } Bits;\r |
2f88bd3a | 83 | UINT8 Data;\r |
6a82ceb6 LG |
84 | } SPD3_MODULE_ORGANIZATION_STRUCT;\r |
85 | \r | |
86 | typedef union {\r | |
87 | struct {\r | |
2f88bd3a MK |
88 | UINT8 PrimaryBusWidth : 3; ///< Bits 2:0\r |
89 | UINT8 BusWidthExtension : 2; ///< Bits 4:3\r | |
90 | UINT8 Reserved : 3; ///< Bits 7:5\r | |
6a82ceb6 | 91 | } Bits;\r |
2f88bd3a | 92 | UINT8 Data;\r |
6a82ceb6 LG |
93 | } SPD3_MODULE_MEMORY_BUS_WIDTH_STRUCT;\r |
94 | \r | |
95 | typedef union {\r | |
96 | struct {\r | |
2f88bd3a MK |
97 | UINT8 Divisor : 4; ///< Bits 3:0\r |
98 | UINT8 Dividend : 4; ///< Bits 7:4\r | |
6a82ceb6 | 99 | } Bits;\r |
2f88bd3a | 100 | UINT8 Data;\r |
6a82ceb6 LG |
101 | } SPD3_FINE_TIMEBASE_STRUCT;\r |
102 | \r | |
103 | typedef union {\r | |
104 | struct {\r | |
2f88bd3a | 105 | UINT8 Dividend : 8; ///< Bits 7:0\r |
6a82ceb6 | 106 | } Bits;\r |
2f88bd3a | 107 | UINT8 Data;\r |
6a82ceb6 LG |
108 | } SPD3_MEDIUM_TIMEBASE_DIVIDEND_STRUCT;\r |
109 | \r | |
110 | typedef union {\r | |
111 | struct {\r | |
2f88bd3a | 112 | UINT8 Divisor : 8; ///< Bits 7:0\r |
6a82ceb6 | 113 | } Bits;\r |
2f88bd3a | 114 | UINT8 Data;\r |
6a82ceb6 LG |
115 | } SPD3_MEDIUM_TIMEBASE_DIVISOR_STRUCT;\r |
116 | \r | |
117 | typedef struct {\r | |
2f88bd3a MK |
118 | SPD3_MEDIUM_TIMEBASE_DIVIDEND_STRUCT Dividend; ///< Medium Timebase (MTB) Dividend\r |
119 | SPD3_MEDIUM_TIMEBASE_DIVISOR_STRUCT Divisor; ///< Medium Timebase (MTB) Divisor\r | |
6a82ceb6 LG |
120 | } SPD3_MEDIUM_TIMEBASE;\r |
121 | \r | |
122 | typedef union {\r | |
123 | struct {\r | |
2f88bd3a | 124 | UINT8 tCKmin : 8; ///< Bits 7:0\r |
6a82ceb6 | 125 | } Bits;\r |
2f88bd3a | 126 | UINT8 Data;\r |
6a82ceb6 LG |
127 | } SPD3_TCK_MIN_MTB_STRUCT;\r |
128 | \r | |
129 | typedef union {\r | |
130 | struct {\r | |
2f88bd3a MK |
131 | UINT16 Cl4 : 1; ///< Bits 0:0\r |
132 | UINT16 Cl5 : 1; ///< Bits 1:1\r | |
133 | UINT16 Cl6 : 1; ///< Bits 2:2\r | |
134 | UINT16 Cl7 : 1; ///< Bits 3:3\r | |
135 | UINT16 Cl8 : 1; ///< Bits 4:4\r | |
136 | UINT16 Cl9 : 1; ///< Bits 5:5\r | |
137 | UINT16 Cl10 : 1; ///< Bits 6:6\r | |
138 | UINT16 Cl11 : 1; ///< Bits 7:7\r | |
139 | UINT16 Cl12 : 1; ///< Bits 8:8\r | |
140 | UINT16 Cl13 : 1; ///< Bits 9:9\r | |
141 | UINT16 Cl14 : 1; ///< Bits 10:10\r | |
142 | UINT16 Cl15 : 1; ///< Bits 11:11\r | |
143 | UINT16 Cl16 : 1; ///< Bits 12:12\r | |
144 | UINT16 Cl17 : 1; ///< Bits 13:13\r | |
145 | UINT16 Cl18 : 1; ///< Bits 14:14\r | |
146 | UINT16 Reserved : 1; ///< Bits 15:15\r | |
147 | } Bits;\r | |
148 | UINT16 Data;\r | |
149 | UINT8 Data8[2];\r | |
6a82ceb6 LG |
150 | } SPD3_CAS_LATENCIES_SUPPORTED_STRUCT;\r |
151 | \r | |
152 | typedef union {\r | |
153 | struct {\r | |
2f88bd3a | 154 | UINT8 tAAmin : 8; ///< Bits 7:0\r |
6a82ceb6 | 155 | } Bits;\r |
2f88bd3a | 156 | UINT8 Data;\r |
6a82ceb6 LG |
157 | } SPD3_TAA_MIN_MTB_STRUCT;\r |
158 | \r | |
159 | typedef union {\r | |
160 | struct {\r | |
2f88bd3a | 161 | UINT8 tWRmin : 8; ///< Bits 7:0\r |
6a82ceb6 | 162 | } Bits;\r |
2f88bd3a | 163 | UINT8 Data;\r |
6a82ceb6 LG |
164 | } SPD3_TWR_MIN_MTB_STRUCT;\r |
165 | \r | |
166 | typedef union {\r | |
167 | struct {\r | |
2f88bd3a | 168 | UINT8 tRCDmin : 8; ///< Bits 7:0\r |
6a82ceb6 | 169 | } Bits;\r |
2f88bd3a | 170 | UINT8 Data;\r |
6a82ceb6 LG |
171 | } SPD3_TRCD_MIN_MTB_STRUCT;\r |
172 | \r | |
173 | typedef union {\r | |
174 | struct {\r | |
2f88bd3a | 175 | UINT8 tRRDmin : 8; ///< Bits 7:0\r |
6a82ceb6 | 176 | } Bits;\r |
2f88bd3a | 177 | UINT8 Data;\r |
6a82ceb6 LG |
178 | } SPD3_TRRD_MIN_MTB_STRUCT;\r |
179 | \r | |
180 | typedef union {\r | |
181 | struct {\r | |
2f88bd3a | 182 | UINT8 tRPmin : 8; ///< Bits 7:0\r |
6a82ceb6 | 183 | } Bits;\r |
2f88bd3a | 184 | UINT8 Data;\r |
6a82ceb6 LG |
185 | } SPD3_TRP_MIN_MTB_STRUCT;\r |
186 | \r | |
187 | typedef union {\r | |
188 | struct {\r | |
2f88bd3a MK |
189 | UINT8 tRASminUpper : 4; ///< Bits 3:0\r |
190 | UINT8 tRCminUpper : 4; ///< Bits 7:4\r | |
6a82ceb6 | 191 | } Bits;\r |
2f88bd3a | 192 | UINT8 Data;\r |
6a82ceb6 LG |
193 | } SPD3_TRAS_TRC_MIN_MTB_STRUCT;\r |
194 | \r | |
195 | typedef union {\r | |
196 | struct {\r | |
2f88bd3a | 197 | UINT8 tRASmin : 8; ///< Bits 7:0\r |
6a82ceb6 | 198 | } Bits;\r |
2f88bd3a | 199 | UINT8 Data;\r |
6a82ceb6 LG |
200 | } SPD3_TRAS_MIN_MTB_STRUCT;\r |
201 | \r | |
202 | typedef union {\r | |
203 | struct {\r | |
2f88bd3a | 204 | UINT8 tRCmin : 8; ///< Bits 7:0\r |
6a82ceb6 | 205 | } Bits;\r |
2f88bd3a | 206 | UINT8 Data;\r |
6a82ceb6 LG |
207 | } SPD3_TRC_MIN_MTB_STRUCT;\r |
208 | \r | |
209 | typedef union {\r | |
210 | struct {\r | |
2f88bd3a | 211 | UINT16 tRFCmin : 16; ///< Bits 15:0\r |
6a82ceb6 | 212 | } Bits;\r |
2f88bd3a MK |
213 | UINT16 Data;\r |
214 | UINT8 Data8[2];\r | |
6a82ceb6 LG |
215 | } SPD3_TRFC_MIN_MTB_STRUCT;\r |
216 | \r | |
217 | typedef union {\r | |
218 | struct {\r | |
2f88bd3a | 219 | UINT8 tWTRmin : 8; ///< Bits 7:0\r |
6a82ceb6 | 220 | } Bits;\r |
2f88bd3a | 221 | UINT8 Data;\r |
6a82ceb6 LG |
222 | } SPD3_TWTR_MIN_MTB_STRUCT;\r |
223 | \r | |
224 | typedef union {\r | |
225 | struct {\r | |
2f88bd3a | 226 | UINT8 tRTPmin : 8; ///< Bits 7:0\r |
6a82ceb6 | 227 | } Bits;\r |
2f88bd3a | 228 | UINT8 Data;\r |
6a82ceb6 LG |
229 | } SPD3_TRTP_MIN_MTB_STRUCT;\r |
230 | \r | |
231 | typedef union {\r | |
232 | struct {\r | |
2f88bd3a MK |
233 | UINT8 tFAWminUpper : 4; ///< Bits 3:0\r |
234 | UINT8 Reserved : 4; ///< Bits 7:4\r | |
6a82ceb6 | 235 | } Bits;\r |
2f88bd3a | 236 | UINT8 Data;\r |
6a82ceb6 LG |
237 | } SPD3_TFAW_MIN_MTB_UPPER_STRUCT;\r |
238 | \r | |
239 | typedef union {\r | |
240 | struct {\r | |
2f88bd3a | 241 | UINT8 tFAWmin : 8; ///< Bits 7:0\r |
6a82ceb6 | 242 | } Bits;\r |
2f88bd3a | 243 | UINT8 Data;\r |
6a82ceb6 LG |
244 | } SPD3_TFAW_MIN_MTB_STRUCT;\r |
245 | \r | |
246 | typedef union {\r | |
247 | struct {\r | |
2f88bd3a MK |
248 | UINT8 Rzq6 : 1; ///< Bits 0:0\r |
249 | UINT8 Rzq7 : 1; ///< Bits 1:1\r | |
250 | UINT8 Reserved : 5; ///< Bits 6:2\r | |
251 | UINT8 DllOff : 1; ///< Bits 7:7\r | |
6a82ceb6 | 252 | } Bits;\r |
2f88bd3a | 253 | UINT8 Data;\r |
6a82ceb6 LG |
254 | } SPD3_SDRAM_OPTIONAL_FEATURES_STRUCT;\r |
255 | \r | |
256 | typedef union {\r | |
257 | struct {\r | |
2f88bd3a MK |
258 | UINT8 ExtendedTemperatureRange : 1; ///< Bits 0:0\r |
259 | UINT8 ExtendedTemperatureRefreshRate : 1; ///< Bits 1:1\r | |
260 | UINT8 AutoSelfRefresh : 1; ///< Bits 2:2\r | |
261 | UINT8 OnDieThermalSensor : 1; ///< Bits 3:3\r | |
262 | UINT8 Reserved : 3; ///< Bits 6:4\r | |
263 | UINT8 PartialArraySelfRefresh : 1; ///< Bits 7:7\r | |
6a82ceb6 | 264 | } Bits;\r |
2f88bd3a | 265 | UINT8 Data;\r |
6a82ceb6 LG |
266 | } SPD3_SDRAM_THERMAL_REFRESH_STRUCT;\r |
267 | \r | |
268 | typedef union {\r | |
269 | struct {\r | |
2f88bd3a MK |
270 | UINT8 ThermalSensorAccuracy : 7; ///< Bits 6:0\r |
271 | UINT8 ThermalSensorPresence : 1; ///< Bits 7:7\r | |
6a82ceb6 | 272 | } Bits;\r |
2f88bd3a | 273 | UINT8 Data;\r |
6a82ceb6 LG |
274 | } SPD3_MODULE_THERMAL_SENSOR_STRUCT;\r |
275 | \r | |
276 | typedef union {\r | |
277 | struct {\r | |
2f88bd3a MK |
278 | UINT8 SignalLoading : 2; ///< Bits 1:0\r |
279 | UINT8 Reserved : 2; ///< Bits 3:2\r | |
280 | UINT8 DieCount : 3; ///< Bits 6:4\r | |
281 | UINT8 SdramDeviceType : 1; ///< Bits 7:7\r | |
6a82ceb6 | 282 | } Bits;\r |
2f88bd3a | 283 | UINT8 Data;\r |
6a82ceb6 LG |
284 | } SPD3_SDRAM_DEVICE_TYPE_STRUCT;\r |
285 | \r | |
286 | typedef union {\r | |
287 | struct {\r | |
2f88bd3a | 288 | INT8 tCKminFine : 8; ///< Bits 7:0\r |
6a82ceb6 | 289 | } Bits;\r |
2f88bd3a | 290 | INT8 Data;\r |
6a82ceb6 LG |
291 | } SPD3_TCK_MIN_FTB_STRUCT;\r |
292 | \r | |
293 | typedef union {\r | |
294 | struct {\r | |
2f88bd3a | 295 | INT8 tAAminFine : 8; ///< Bits 7:0\r |
6a82ceb6 | 296 | } Bits;\r |
2f88bd3a | 297 | INT8 Data;\r |
6a82ceb6 LG |
298 | } SPD3_TAA_MIN_FTB_STRUCT;\r |
299 | \r | |
300 | typedef union {\r | |
301 | struct {\r | |
2f88bd3a | 302 | INT8 tRCDminFine : 8; ///< Bits 7:0\r |
6a82ceb6 | 303 | } Bits;\r |
2f88bd3a | 304 | INT8 Data;\r |
6a82ceb6 LG |
305 | } SPD3_TRCD_MIN_FTB_STRUCT;\r |
306 | \r | |
307 | typedef union {\r | |
308 | struct {\r | |
2f88bd3a | 309 | INT8 tRPminFine : 8; ///< Bits 7:0\r |
6a82ceb6 | 310 | } Bits;\r |
2f88bd3a | 311 | INT8 Data;\r |
6a82ceb6 LG |
312 | } SPD3_TRP_MIN_FTB_STRUCT;\r |
313 | \r | |
314 | typedef union {\r | |
315 | struct {\r | |
2f88bd3a | 316 | INT8 tRCminFine : 8; ///< Bits 7:0\r |
6a82ceb6 | 317 | } Bits;\r |
2f88bd3a | 318 | INT8 Data;\r |
6a82ceb6 LG |
319 | } SPD3_TRC_MIN_FTB_STRUCT;\r |
320 | \r | |
321 | typedef union {\r | |
322 | struct {\r | |
2f88bd3a MK |
323 | UINT8 MaximumActivateCount : 4; ///< Bits 3:0\r |
324 | UINT8 MaximumActivateWindow : 2; ///< Bits 5:4\r | |
325 | UINT8 VendorSpecific : 2; ///< Bits 7:6\r | |
6a82ceb6 | 326 | } Bits;\r |
2f88bd3a | 327 | UINT8 Data;\r |
6a82ceb6 LG |
328 | } SPD3_MAXIMUM_ACTIVE_COUNT_STRUCT;\r |
329 | \r | |
330 | typedef union {\r | |
331 | struct {\r | |
2f88bd3a MK |
332 | UINT8 Height : 5; ///< Bits 4:0\r |
333 | UINT8 RawCardExtension : 3; ///< Bits 7:5\r | |
6a82ceb6 | 334 | } Bits;\r |
2f88bd3a | 335 | UINT8 Data;\r |
6a82ceb6 LG |
336 | } SPD3_UNBUF_MODULE_NOMINAL_HEIGHT;\r |
337 | \r | |
338 | typedef union {\r | |
339 | struct {\r | |
2f88bd3a MK |
340 | UINT8 FrontThickness : 4; ///< Bits 3:0\r |
341 | UINT8 BackThickness : 4; ///< Bits 7:4\r | |
6a82ceb6 | 342 | } Bits;\r |
2f88bd3a | 343 | UINT8 Data;\r |
6a82ceb6 LG |
344 | } SPD3_UNBUF_MODULE_NOMINAL_THICKNESS;\r |
345 | \r | |
346 | typedef union {\r | |
347 | struct {\r | |
2f88bd3a MK |
348 | UINT8 Card : 5; ///< Bits 4:0\r |
349 | UINT8 Revision : 2; ///< Bits 6:5\r | |
350 | UINT8 Extension : 1; ///< Bits 7:7\r | |
6a82ceb6 | 351 | } Bits;\r |
2f88bd3a | 352 | UINT8 Data;\r |
6a82ceb6 LG |
353 | } SPD3_UNBUF_REFERENCE_RAW_CARD;\r |
354 | \r | |
355 | typedef union {\r | |
356 | struct {\r | |
2f88bd3a MK |
357 | UINT8 MappingRank1 : 1; ///< Bits 0:0\r |
358 | UINT8 Reserved : 7; ///< Bits 7:1\r | |
6a82ceb6 | 359 | } Bits;\r |
2f88bd3a | 360 | UINT8 Data;\r |
6a82ceb6 LG |
361 | } SPD3_UNBUF_ADDRESS_MAPPING;\r |
362 | \r | |
363 | typedef union {\r | |
364 | struct {\r | |
2f88bd3a MK |
365 | UINT8 Height : 5; ///< Bits 4:0\r |
366 | UINT8 Reserved : 3; ///< Bits 7:5\r | |
6a82ceb6 | 367 | } Bits;\r |
2f88bd3a | 368 | UINT8 Data;\r |
6a82ceb6 LG |
369 | } SPD3_RDIMM_MODULE_NOMINAL_HEIGHT;\r |
370 | \r | |
371 | typedef union {\r | |
372 | struct {\r | |
2f88bd3a MK |
373 | UINT8 FrontThickness : 4; ///< Bits 3:0\r |
374 | UINT8 BackThickness : 4; ///< Bits 7:4\r | |
6a82ceb6 | 375 | } Bits;\r |
2f88bd3a | 376 | UINT8 Data;\r |
6a82ceb6 LG |
377 | } SPD3_RDIMM_MODULE_NOMINAL_THICKNESS;\r |
378 | \r | |
379 | typedef union {\r | |
380 | struct {\r | |
2f88bd3a MK |
381 | UINT8 Card : 5; ///< Bits 4:0\r |
382 | UINT8 Revision : 2; ///< Bits 6:5\r | |
383 | UINT8 Extension : 1; ///< Bits 7:7\r | |
6a82ceb6 | 384 | } Bits;\r |
2f88bd3a | 385 | UINT8 Data;\r |
6a82ceb6 LG |
386 | } SPD3_RDIMM_REFERENCE_RAW_CARD;\r |
387 | \r | |
388 | typedef union {\r | |
389 | struct {\r | |
2f88bd3a MK |
390 | UINT8 RegisterCount : 2; ///< Bits 1:0\r |
391 | UINT8 DramRowCount : 2; ///< Bits 3:2\r | |
392 | UINT8 RegisterType : 4; ///< Bits 7:4\r | |
6a82ceb6 | 393 | } Bits;\r |
2f88bd3a | 394 | UINT8 Data;\r |
6a82ceb6 LG |
395 | } SPD3_RDIMM_MODULE_ATTRIBUTES;\r |
396 | \r | |
397 | typedef union {\r | |
398 | struct {\r | |
2f88bd3a MK |
399 | UINT8 HeatSpreaderThermalCharacteristics : 7; ///< Bits 6:0\r |
400 | UINT8 HeatSpreaderSolution : 1; ///< Bits 7:7\r | |
6a82ceb6 | 401 | } Bits;\r |
2f88bd3a | 402 | UINT8 Data;\r |
6a82ceb6 LG |
403 | } SPD3_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION;\r |
404 | \r | |
405 | typedef union {\r | |
406 | struct {\r | |
2f88bd3a MK |
407 | UINT16 ContinuationCount : 7; ///< Bits 6:0\r |
408 | UINT16 ContinuationParity : 1; ///< Bits 7:7\r | |
409 | UINT16 LastNonZeroByte : 8; ///< Bits 15:8\r | |
6a82ceb6 | 410 | } Bits;\r |
2f88bd3a MK |
411 | UINT16 Data;\r |
412 | UINT8 Data8[2];\r | |
6a82ceb6 LG |
413 | } SPD3_MANUFACTURER_ID_CODE;\r |
414 | \r | |
415 | typedef union {\r | |
416 | struct {\r | |
2f88bd3a | 417 | UINT8 RegisterRevisionNumber; ///< Bits 7:0\r |
6a82ceb6 | 418 | } Bits;\r |
2f88bd3a | 419 | UINT8 Data;\r |
6a82ceb6 LG |
420 | } SPD3_RDIMM_REGISTER_REVISION_NUMBER;\r |
421 | \r | |
422 | typedef union {\r | |
423 | struct {\r | |
2f88bd3a MK |
424 | UINT8 Bit0 : 1; ///< Bits 0:0\r |
425 | UINT8 Bit1 : 1; ///< Bits 1:1\r | |
426 | UINT8 Bit2 : 1; ///< Bits 2:2\r | |
427 | UINT8 Reserved : 5; ///< Bits 7:3\r | |
6a82ceb6 | 428 | } Bits;\r |
2f88bd3a | 429 | UINT8 Data;\r |
6a82ceb6 LG |
430 | } SPD3_RDIMM_REGISTER_TYPE;\r |
431 | \r | |
432 | typedef union {\r | |
433 | struct {\r | |
2f88bd3a MK |
434 | UINT8 Reserved : 4; ///< Bits 0:3\r |
435 | UINT8 CommandAddressAOutputs : 2; ///< Bits 5:4\r | |
436 | UINT8 CommandAddressBOutputs : 2; ///< Bits 7:6\r | |
6a82ceb6 | 437 | } Bits;\r |
2f88bd3a | 438 | UINT8 Data;\r |
6a82ceb6 LG |
439 | } SPD3_RDIMM_REGISTER_CONTROL_COMMAND_ADDRESS;\r |
440 | \r | |
441 | typedef union {\r | |
442 | struct {\r | |
2f88bd3a MK |
443 | UINT8 ControlSignalsAOutputs : 2; ///< Bits 0:1\r |
444 | UINT8 ControlSignalsBOutputs : 2; ///< Bits 3:2\r | |
445 | UINT8 Y1Y3ClockOutputs : 2; ///< Bits 5:4\r | |
446 | UINT8 Y0Y2ClockOutputs : 2; ///< Bits 7:6\r | |
6a82ceb6 | 447 | } Bits;\r |
2f88bd3a | 448 | UINT8 Data;\r |
6a82ceb6 LG |
449 | } SPD3_RDIMM_REGISTER_CONTROL_CONTROL_CLOCK;\r |
450 | \r | |
451 | typedef union {\r | |
452 | struct {\r | |
2f88bd3a MK |
453 | UINT8 Reserved0 : 4; ///< Bits 0:3\r |
454 | UINT8 Reserved1 : 4; ///< Bits 7:4\r | |
6a82ceb6 | 455 | } Bits;\r |
2f88bd3a | 456 | UINT8 Data;\r |
6a82ceb6 LG |
457 | } SPD3_RDIMM_REGISTER_CONTROL_RESERVED;\r |
458 | \r | |
459 | typedef union {\r | |
460 | struct {\r | |
2f88bd3a MK |
461 | UINT8 Height : 5; ///< Bits 4:0\r |
462 | UINT8 Reserved : 3; ///< Bits 7:5\r | |
6a82ceb6 | 463 | } Bits;\r |
2f88bd3a | 464 | UINT8 Data;\r |
6a82ceb6 LG |
465 | } SPD3_LRDIMM_MODULE_NOMINAL_HEIGHT;\r |
466 | \r | |
467 | typedef union {\r | |
468 | struct {\r | |
2f88bd3a MK |
469 | UINT8 FrontThickness : 4; ///< Bits 3:0\r |
470 | UINT8 BackThickness : 4; ///< Bits 7:4\r | |
6a82ceb6 | 471 | } Bits;\r |
2f88bd3a | 472 | UINT8 Data;\r |
6a82ceb6 LG |
473 | } SPD3_LRDIMM_MODULE_NOMINAL_THICKNESS;\r |
474 | \r | |
475 | typedef union {\r | |
476 | struct {\r | |
2f88bd3a MK |
477 | UINT8 Card : 5; ///< Bits 4:0\r |
478 | UINT8 Revision : 2; ///< Bits 6:5\r | |
479 | UINT8 Extension : 1; ///< Bits 7:7\r | |
6a82ceb6 | 480 | } Bits;\r |
2f88bd3a | 481 | UINT8 Data;\r |
6a82ceb6 LG |
482 | } SPD3_LRDIMM_REFERENCE_RAW_CARD;\r |
483 | \r | |
484 | typedef union {\r | |
485 | struct {\r | |
2f88bd3a MK |
486 | UINT8 RegisterCount : 2; ///< Bits 1:0\r |
487 | UINT8 DramRowCount : 2; ///< Bits 3:2\r | |
488 | UINT8 RegisterType : 4; ///< Bits 7:4\r | |
6a82ceb6 | 489 | } Bits;\r |
2f88bd3a | 490 | UINT8 Data;\r |
6a82ceb6 LG |
491 | } SPD3_LRDIMM_MODULE_ATTRIBUTES;\r |
492 | \r | |
493 | typedef union {\r | |
494 | struct {\r | |
2f88bd3a MK |
495 | UINT8 AddressCommandPrelaunch : 1; ///< Bits 0:0\r |
496 | UINT8 Rank1Rank5Swap : 1; ///< Bits 1:1\r | |
497 | UINT8 Reserved0 : 1; ///< Bits 2:2\r | |
498 | UINT8 Reserved1 : 1; ///< Bits 3:3\r | |
499 | UINT8 AddressCommandOutputs : 2; ///< Bits 5:4\r | |
500 | UINT8 QxCS_nOutputs : 2; ///< Bits 7:6\r | |
6a82ceb6 | 501 | } Bits;\r |
2f88bd3a | 502 | UINT8 Data;\r |
6a82ceb6 LG |
503 | } SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH;\r |
504 | \r | |
505 | typedef union {\r | |
506 | struct {\r | |
2f88bd3a MK |
507 | UINT8 QxOdtOutputs : 2; ///< Bits 1:0\r |
508 | UINT8 QxCkeOutputs : 2; ///< Bits 3:2\r | |
509 | UINT8 Y1Y3ClockOutputs : 2; ///< Bits 5:4\r | |
510 | UINT8 Y0Y2ClockOutputs : 2; ///< Bits 7:6\r | |
6a82ceb6 | 511 | } Bits;\r |
2f88bd3a | 512 | UINT8 Data;\r |
6a82ceb6 LG |
513 | } SPD3_LRDIMM_TIMING_DRIVE_STRENGTH;\r |
514 | \r | |
515 | typedef union {\r | |
516 | struct {\r | |
2f88bd3a MK |
517 | UINT8 YExtendedDelay : 2; ///< Bits 1:0\r |
518 | UINT8 QxCS_n : 2; ///< Bits 3:2\r | |
519 | UINT8 QxOdt : 2; ///< Bits 5:4\r | |
520 | UINT8 QxCke : 2; ///< Bits 7:6\r | |
6a82ceb6 | 521 | } Bits;\r |
2f88bd3a | 522 | UINT8 Data;\r |
6a82ceb6 LG |
523 | } SPD3_LRDIMM_EXTENDED_DELAY;\r |
524 | \r | |
525 | typedef union {\r | |
526 | struct {\r | |
2f88bd3a MK |
527 | UINT8 DelayY : 3; ///< Bits 2:0\r |
528 | UINT8 Reserved : 1; ///< Bits 3:3\r | |
529 | UINT8 QxCS_n : 4; ///< Bits 7:4\r | |
6a82ceb6 | 530 | } Bits;\r |
2f88bd3a | 531 | UINT8 Data;\r |
6a82ceb6 LG |
532 | } SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXCS_N_QXCA;\r |
533 | \r | |
534 | typedef union {\r | |
535 | struct {\r | |
2f88bd3a MK |
536 | UINT8 QxCS_n : 4; ///< Bits 3:0\r |
537 | UINT8 QxOdt : 4; ///< Bits 7:4\r | |
6a82ceb6 | 538 | } Bits;\r |
2f88bd3a | 539 | UINT8 Data;\r |
6a82ceb6 LG |
540 | } SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXODT_QXCKE;\r |
541 | \r | |
542 | typedef union {\r | |
543 | struct {\r | |
2f88bd3a MK |
544 | UINT8 RC8MdqOdtStrength : 3; ///< Bits 2:0\r |
545 | UINT8 RC8Reserved : 1; ///< Bits 3:3\r | |
546 | UINT8 RC9MdqOdtStrength : 3; ///< Bits 6:4\r | |
547 | UINT8 RC9Reserved : 1; ///< Bits 7:7\r | |
6a82ceb6 | 548 | } Bits;\r |
2f88bd3a | 549 | UINT8 Data;\r |
6a82ceb6 LG |
550 | } SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH;\r |
551 | \r | |
552 | typedef union {\r | |
553 | struct {\r | |
2f88bd3a MK |
554 | UINT8 RC10DA3ValueR0 : 1; ///< Bits 0:0\r |
555 | UINT8 RC10DA4ValueR0 : 1; ///< Bits 1:1\r | |
556 | UINT8 RC10DA3ValueR1 : 1; ///< Bits 2:2\r | |
557 | UINT8 RC10DA4ValueR1 : 1; ///< Bits 3:3\r | |
558 | UINT8 RC11DA3ValueR0 : 1; ///< Bits 4:4\r | |
559 | UINT8 RC11DA4ValueR0 : 1; ///< Bits 5:5\r | |
560 | UINT8 RC11DA3ValueR1 : 1; ///< Bits 6:6\r | |
561 | UINT8 RC11DA4ValueR1 : 1; ///< Bits 7:7\r | |
6a82ceb6 | 562 | } Bits;\r |
2f88bd3a | 563 | UINT8 Data;\r |
6a82ceb6 LG |
564 | } SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL;\r |
565 | \r | |
566 | typedef union {\r | |
567 | struct {\r | |
2f88bd3a MK |
568 | UINT8 Driver_Impedance : 2; ///< Bits 1:0\r |
569 | UINT8 Rtt_Nom : 3; ///< Bits 4:2\r | |
570 | UINT8 Reserved : 1; ///< Bits 5:5\r | |
571 | UINT8 Rtt_WR : 2; ///< Bits 7:6\r | |
6a82ceb6 | 572 | } Bits;\r |
2f88bd3a | 573 | UINT8 Data;\r |
6a82ceb6 LG |
574 | } SPD3_LRDIMM_MR_1_2;\r |
575 | \r | |
576 | typedef union {\r | |
577 | struct {\r | |
2f88bd3a MK |
578 | UINT8 MinimumDelayTime : 7; ///< Bits 0:6\r |
579 | UINT8 Reserved : 1; ///< Bits 7:7\r | |
6a82ceb6 | 580 | } Bits;\r |
2f88bd3a | 581 | UINT8 Data;\r |
6a82ceb6 LG |
582 | } SPD3_LRDIMM_MODULE_DELAY_TIME;\r |
583 | \r | |
584 | typedef struct {\r | |
2f88bd3a MK |
585 | UINT8 Year; ///< Year represented in BCD (00h = 2000)\r |
586 | UINT8 Week; ///< Year represented in BCD (47h = week 47)\r | |
6a82ceb6 LG |
587 | } SPD3_MANUFACTURING_DATE;\r |
588 | \r | |
589 | typedef union {\r | |
2f88bd3a MK |
590 | UINT32 Data;\r |
591 | UINT16 SerialNumber16[2];\r | |
592 | UINT8 SerialNumber8[4];\r | |
6a82ceb6 LG |
593 | } SPD3_MANUFACTURER_SERIAL_NUMBER;\r |
594 | \r | |
595 | typedef struct {\r | |
2f88bd3a | 596 | UINT8 Location; ///< Module Manufacturing Location\r |
6a82ceb6 LG |
597 | } SPD3_MANUFACTURING_LOCATION;\r |
598 | \r | |
599 | typedef struct {\r | |
2f88bd3a MK |
600 | SPD3_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code\r |
601 | SPD3_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location\r | |
602 | SPD3_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255)\r | |
603 | SPD3_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number\r | |
6a82ceb6 LG |
604 | } SPD3_UNIQUE_MODULE_ID;\r |
605 | \r | |
606 | typedef union {\r | |
2f88bd3a MK |
607 | UINT16 Crc[1];\r |
608 | UINT8 Data8[2];\r | |
6a82ceb6 LG |
609 | } SPD3_CYCLIC_REDUNDANCY_CODE;\r |
610 | \r | |
611 | typedef struct {\r | |
2f88bd3a MK |
612 | SPD3_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2\r |
613 | SPD3_REVISION_STRUCT Revision; ///< 1 SPD Revision\r | |
614 | SPD3_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type\r | |
615 | SPD3_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type\r | |
616 | SPD3_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks\r | |
617 | SPD3_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing\r | |
618 | SPD3_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 6 Module Nominal Voltage, VDD\r | |
619 | SPD3_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 7 Module Organization\r | |
620 | SPD3_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 8 Module Memory Bus Width\r | |
621 | SPD3_FINE_TIMEBASE_STRUCT FineTimebase; ///< 9 Fine Timebase (FTB) Dividend / Divisor\r | |
622 | SPD3_MEDIUM_TIMEBASE MediumTimebase; ///< 10-11 Medium Timebase (MTB) Dividend\r | |
623 | SPD3_TCK_MIN_MTB_STRUCT tCKmin; ///< 12 SDRAM Minimum Cycle Time (tCKmin)\r | |
624 | UINT8 Reserved0; ///< 13 Reserved\r | |
625 | SPD3_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 14-15 CAS Latencies Supported\r | |
626 | SPD3_TAA_MIN_MTB_STRUCT tAAmin; ///< 16 Minimum CAS Latency Time (tAAmin)\r | |
627 | SPD3_TWR_MIN_MTB_STRUCT tWRmin; ///< 17 Minimum Write Recovery Time (tWRmin)\r | |
628 | SPD3_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 18 Minimum RAS# to CAS# Delay Time (tRCDmin)\r | |
629 | SPD3_TRRD_MIN_MTB_STRUCT tRRDmin; ///< 19 Minimum Row Active to Row Active Delay Time (tRRDmin)\r | |
630 | SPD3_TRP_MIN_MTB_STRUCT tRPmin; ///< 20 Minimum Row Precharge Delay Time (tRPmin)\r | |
631 | SPD3_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 21 Upper Nibbles for tRAS and tRC\r | |
632 | SPD3_TRAS_MIN_MTB_STRUCT tRASmin; ///< 22 Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte\r | |
633 | SPD3_TRC_MIN_MTB_STRUCT tRCmin; ///< 23 Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte\r | |
634 | SPD3_TRFC_MIN_MTB_STRUCT tRFCmin; ///< 24-25 Minimum Refresh Recovery Delay Time (tRFCmin)\r | |
635 | SPD3_TWTR_MIN_MTB_STRUCT tWTRmin; ///< 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)\r | |
636 | SPD3_TRTP_MIN_MTB_STRUCT tRTPmin; ///< 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin)\r | |
637 | SPD3_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 28 Upper Nibble for tFAW\r | |
638 | SPD3_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 29 Minimum Four Activate Window Delay Time (tFAWmin)\r | |
639 | SPD3_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 30 SDRAM Optional Features\r | |
640 | SPD3_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 31 SDRAM Thermal And Refresh Options\r | |
641 | SPD3_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 32 Module Thermal Sensor\r | |
642 | SPD3_SDRAM_DEVICE_TYPE_STRUCT SdramDeviceType; ///< 33 SDRAM Device Type\r | |
643 | SPD3_TCK_MIN_FTB_STRUCT tCKminFine; ///< 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)\r | |
644 | SPD3_TAA_MIN_FTB_STRUCT tAAminFine; ///< 35 Fine Offset for Minimum CAS Latency Time (tAAmin)\r | |
645 | SPD3_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 36 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)\r | |
646 | SPD3_TRP_MIN_FTB_STRUCT tRPminFine; ///< 37 Minimum Row Precharge Delay Time (tRPmin)\r | |
647 | SPD3_TRC_MIN_FTB_STRUCT tRCminFine; ///< 38 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin)\r | |
648 | UINT8 Reserved1[40 - 39 + 1]; ///< 39 - 40 Reserved\r | |
649 | SPD3_MAXIMUM_ACTIVE_COUNT_STRUCT MacValue; ///< 41 SDRAM Maximum Active Count (MAC) Value\r | |
650 | UINT8 Reserved2[59 - 42 + 1]; ///< 42 - 59 Reserved\r | |
6a82ceb6 LG |
651 | } SPD3_BASE_SECTION;\r |
652 | \r | |
653 | typedef struct {\r | |
2f88bd3a MK |
654 | SPD3_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height\r |
655 | SPD3_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness\r | |
656 | SPD3_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used\r | |
657 | SPD3_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 63 Address Mapping from Edge Connector to DRAM\r | |
658 | UINT8 Reserved[116 - 64 + 1]; ///< 64-116 Reserved\r | |
6a82ceb6 LG |
659 | } SPD3_MODULE_UNBUFFERED;\r |
660 | \r | |
661 | typedef struct {\r | |
2f88bd3a MK |
662 | SPD3_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height\r |
663 | SPD3_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness\r | |
664 | SPD3_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used\r | |
665 | SPD3_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 63 DIMM Module Attributes\r | |
666 | SPD3_RDIMM_THERMAL_HEAT_SPREADER_SOLUTION ThermalHeatSpreaderSolution; ///< 64 RDIMM Thermal Heat Spreader Solution\r | |
667 | SPD3_MANUFACTURER_ID_CODE RegisterManufacturerIdCode; ///< 65-66 Register Manufacturer ID Code\r | |
668 | SPD3_RDIMM_REGISTER_REVISION_NUMBER RegisterRevisionNumber; ///< 67 Register Revision Number\r | |
669 | SPD3_RDIMM_REGISTER_TYPE RegisterType; ///< 68 Register Type\r | |
670 | SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc1Rc0; ///< 69 RC1 (MS Nibble) / RC0 (LS Nibble) - Reserved\r | |
671 | SPD3_RDIMM_REGISTER_CONTROL_COMMAND_ADDRESS Rc3Rc2; ///< 70 RC3 (MS Nibble) / RC2 (LS Nibble) - Drive Strength, Command/Address\r | |
672 | SPD3_RDIMM_REGISTER_CONTROL_CONTROL_CLOCK Rc5Rc4; ///< 71 RC5 (MS Nibble) / RC4 (LS Nibble) - Drive Strength, Control and Clock\r | |
673 | SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc7Rc6; ///< 72 RC7 (MS Nibble) / RC6 (LS Nibble) - Reserved for Register Vendor\r | |
674 | SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc9Rc8; ///< 73 RC9 (MS Nibble) / RC8 (LS Nibble) - Reserved\r | |
675 | SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc11Rc10; ///< 74 RC11 (MS Nibble) / RC10 (LS Nibble) - Reserved\r | |
676 | SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc13Rc12; ///< 75 RC12 (MS Nibble) / RC12 (LS Nibble) - Reserved\r | |
677 | SPD3_RDIMM_REGISTER_CONTROL_RESERVED Rc15Rc14; ///< 76 RC15 (MS Nibble) / RC14 (LS Nibble) - Reserved\r | |
678 | UINT8 Reserved[116 - 77 + 1]; ///< 77-116 Reserved\r | |
6a82ceb6 LG |
679 | } SPD3_MODULE_REGISTERED;\r |
680 | \r | |
681 | typedef struct {\r | |
2f88bd3a MK |
682 | SPD3_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height\r |
683 | SPD3_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness\r | |
684 | SPD3_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used\r | |
685 | UINT8 Reserved[116 - 63 + 1]; ///< 63-116 Reserved\r | |
6a82ceb6 LG |
686 | } SPD3_MODULE_CLOCKED;\r |
687 | \r | |
688 | typedef struct {\r | |
2f88bd3a MK |
689 | SPD3_LRDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Module Nominal Height\r |
690 | SPD3_LRDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Module Maximum Thickness\r | |
691 | SPD3_LRDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Reference Raw Card Used\r | |
692 | SPD3_LRDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 63 Module Attributes\r | |
693 | UINT8 MemoryBufferRevisionNumber; ///< 64 Memory Buffer Revision Number\r | |
694 | SPD3_MANUFACTURER_ID_CODE ManufacturerIdCode; ///< 65-66 Memory Buffer Manufacturer ID Code\r | |
695 | SPD3_LRDIMM_TIMING_CONTROL_DRIVE_STRENGTH TimingControlDriveStrengthCaCs; ///< 67 F0RC3 / F0RC2 - Timing Control & Drive Strength, CA & CS\r | |
696 | SPD3_LRDIMM_TIMING_DRIVE_STRENGTH DriveStrength; ///< 68 F0RC5 / F0RC4 - Drive Strength, ODT & CKE and Y\r | |
697 | SPD3_LRDIMM_EXTENDED_DELAY ExtendedDelay; ///< 69 F1RC11 / F1RC8 - Extended Delay for Y, CS and ODT & CKE\r | |
698 | SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXCS_N_QXCA AdditiveDelayForCsCa; ///< 70 F1RC13 / F1RC12 - Additive Delay for CS and CA\r | |
699 | SPD3_LRDIMM_ADDITIVE_DELAY_FOR_QXODT_QXCKE AdditiveDelayForOdtCke; ///< 71 F1RC15 / F1RC14 - Additive Delay for ODT & CKE\r | |
700 | SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor800_1066; ///< 72 F1RC15 / F1RC14 - Additive Delay for ODT & CKE\r | |
701 | SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor800_1066; ///< 73 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066\r | |
702 | SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor800_1066; ///< 74 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066\r | |
703 | SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor800_1066; ///< 75 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066\r | |
704 | SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor800_1066; ///< 76 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066\r | |
705 | SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor800_1066; ///< 77 MR1,2 Registers for 800 & 1066\r | |
6a82ceb6 | 706 | SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor1333_1600; ///< 78 F1RC15 / F1RC14 - Additive Delay for ODT & CKE\r |
2f88bd3a MK |
707 | SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor1333_1600; ///< 79 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066\r |
708 | SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor1333_1600; ///< 80 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066\r | |
709 | SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor1333_1600; ///< 81 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066\r | |
710 | SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor1333_1600; ///< 82 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066\r | |
711 | SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor1333_1600; ///< 83 MR1,2 Registers for 800 & 1066\r | |
6a82ceb6 | 712 | SPD3_LRDIMM_MDQ_TERMINATION_DRIVE_STRENGTH MdqTerminationDriveStrengthFor1866_2133; ///< 84 F1RC15 / F1RC14 - Additive Delay for ODT & CKE\r |
2f88bd3a MK |
713 | SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_0_1QxOdtControlFor1866_2133; ///< 85 F[3,4]RC11 / F[3,4]RC10 - Rank 0 & 1 RD & WR QxODT Control for 800 & 1066\r |
714 | SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_2_3QxOdtControlFor1866_2133; ///< 86 F[5,6]RC11 / F[5,6]RC10 - Rank 2 & 3 RD & WR QxODT Control for 800 & 1066\r | |
715 | SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_4_5QxOdtControlFor1866_2133; ///< 87 F[7,8]RC11 / F[7,8]RC10 - Rank 4 & 5 RD & WR QxODT Control for 800 & 1066\r | |
716 | SPD3_LRDIMM_RANK_READ_WRITE_QXODT_CONTROL Rank_6_7QxOdtControlFor1866_2133; ///< 88 F[9,10]RC11 / F[9,10]RC10 - Rank 6 & 7 RD & WR QxODT Control for 800 & 1066\r | |
717 | SPD3_LRDIMM_MR_1_2 MR_1_2RegistersFor1866_2133; ///< 89 MR1,2 Registers for 800 & 1066\r | |
718 | SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_5V; ///< 90 Minimum Module Delay Time for 1.5 V\r | |
719 | SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_5V; ///< 91 Maximum Module Delay Time for 1.5 V\r | |
720 | SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_35V; ///< 92 Minimum Module Delay Time for 1.35 V\r | |
721 | SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_35V; ///< 93 Maximum Module Delay Time for 1.35 V\r | |
722 | SPD3_LRDIMM_MODULE_DELAY_TIME MinimumModuleDelayTimeFor1_25V; ///< 94 Minimum Module Delay Time for 1.25 V\r | |
723 | SPD3_LRDIMM_MODULE_DELAY_TIME MaximumModuleDelayTimeFor1_25V; ///< 95 Maximum Module Delay Time for 1.25 V\r | |
724 | UINT8 Reserved[101 - 96 + 1]; ///< 96-101 Reserved\r | |
725 | UINT8 PersonalityByte[116 - 102 + 1]; ///< 102-116 Memory Buffer Personality Bytes\r | |
6a82ceb6 LG |
726 | } SPD3_MODULE_LOADREDUCED;\r |
727 | \r | |
728 | typedef union {\r | |
2f88bd3a MK |
729 | SPD3_MODULE_UNBUFFERED Unbuffered; ///< 128-255 Unbuffered Memory Module Types\r |
730 | SPD3_MODULE_REGISTERED Registered; ///< 128-255 Registered Memory Module Types\r | |
731 | SPD3_MODULE_CLOCKED Clocked; ///< 128-255 Registered Memory Module Types\r | |
732 | SPD3_MODULE_LOADREDUCED LoadReduced; ///< 128-255 Load Reduced Memory Module Types\r | |
6a82ceb6 LG |
733 | } SPD3_MODULE_SPECIFIC;\r |
734 | \r | |
735 | typedef struct {\r | |
2f88bd3a | 736 | UINT8 ModulePartNumber[145 - 128 + 1]; ///< 128-145 Module Part Number\r |
6a82ceb6 LG |
737 | } SPD3_MODULE_PART_NUMBER;\r |
738 | \r | |
739 | typedef struct {\r | |
2f88bd3a | 740 | UINT8 ModuleRevisionCode[147 - 146 + 1]; ///< 146-147 Module Revision Code\r |
6a82ceb6 LG |
741 | } SPD3_MODULE_REVISION_CODE;\r |
742 | \r | |
743 | typedef struct {\r | |
2f88bd3a | 744 | UINT8 ManufacturerSpecificData[175 - 150 + 1]; ///< 150-175 Manufacturer's Specific Data\r |
6a82ceb6 LG |
745 | } SPD3_MANUFACTURER_SPECIFIC;\r |
746 | \r | |
747 | ///\r | |
748 | /// DDR3 Serial Presence Detect structure\r | |
749 | ///\r | |
750 | typedef struct {\r | |
2f88bd3a MK |
751 | SPD3_BASE_SECTION General; ///< 0-59 General Section\r |
752 | SPD3_MODULE_SPECIFIC Module; ///< 60-116 Module-Specific Section\r | |
753 | SPD3_UNIQUE_MODULE_ID ModuleId; ///< 117-125 Unique Module ID\r | |
754 | SPD3_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC)\r | |
755 | SPD3_MODULE_PART_NUMBER ModulePartNumber; ///< 128-145 Module Part Number\r | |
756 | SPD3_MODULE_REVISION_CODE ModuleRevisionCode; ///< 146-147 Module Revision Code\r | |
757 | SPD3_MANUFACTURER_ID_CODE DramIdCode; ///< 148-149 Dram Manufacturer ID Code\r | |
758 | SPD3_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 150-175 Manufacturer's Specific Data\r | |
759 | UINT8 Reserved[255 - 176 + 1]; ///< 176-255 Open for Customer Use\r | |
6a82ceb6 LG |
760 | } SPD_DDR3;\r |
761 | \r | |
762 | #pragma pack (pop)\r | |
763 | #endif\r |