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[mirror_edk2.git] / MdePkg / Include / IndustryStandard / SdramSpdLpDdr.h
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6a82ceb6
LG		 1/** @file\r
2 This file contains definitions for SPD LPDDR.\r
3\r
4 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
9344f092 5 SPDX-License-Identifier: BSD-2-Clause-Patent\r
6a82ceb6
LG		 6\r
7 @par Revision Reference:\r
8 - Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules Document Release 2\r
9 http://www.jedec.org/standards-documents/docs/spd412m-2\r
10**/\r
11\r
12#ifndef _SDRAM_SPD_LPDDR_H_\r
13#define _SDRAM_SPD_LPDDR_H_\r
14\r
15#pragma pack (push, 1)\r
16\r
17typedef union {\r
18 struct {\r
19 UINT8 BytesUsed : 4; ///< Bits 3:0\r
20 UINT8 BytesTotal : 3; ///< Bits 6:4\r
21 UINT8 CrcCoverage : 1; ///< Bits 7:7\r
22 } Bits;\r
23 UINT8 Data;\r
24} SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT;\r
25\r
26typedef union {\r
27 struct {\r
28 UINT8 Minor : 4; ///< Bits 3:0\r
29 UINT8 Major : 4; ///< Bits 7:4\r
30 } Bits;\r
31 UINT8 Data;\r
32} SPD_LPDDR_REVISION_STRUCT;\r
33\r
34typedef union {\r
35 struct {\r
36 UINT8 Type : 8; ///< Bits 7:0\r
37 } Bits;\r
38 UINT8 Data;\r
39} SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT;\r
40\r
41typedef union {\r
42 struct {\r
43 UINT8 ModuleType : 4; ///< Bits 3:0\r
44 UINT8 HybridMedia : 3; ///< Bits 6:4\r
45 UINT8 Hybrid : 1; ///< Bits 7:7\r
46 } Bits;\r
47 UINT8 Data;\r
48} SPD_LPDDR_MODULE_TYPE_STRUCT;\r
49\r
50typedef union {\r
51 struct {\r
52 UINT8 Density : 4; ///< Bits 3:0\r
53 UINT8 BankAddress : 2; ///< Bits 5:4\r
54 UINT8 BankGroup : 2; ///< Bits 7:6\r
55 } Bits;\r
56 UINT8 Data;\r
57} SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT;\r
58\r
59typedef union {\r
60 struct {\r
61 UINT8 ColumnAddress : 3; ///< Bits 2:0\r
62 UINT8 RowAddress : 3; ///< Bits 5:3\r
63 UINT8 Reserved : 2; ///< Bits 7:6\r
64 } Bits;\r
65 UINT8 Data;\r
66} SPD_LPDDR_SDRAM_ADDRESSING_STRUCT;\r
67\r
68typedef union {\r
69 struct {\r
70 UINT8 SignalLoading : 2; ///< Bits 1:0\r
71 UINT8 ChannelsPerDie : 2; ///< Bits 3:2\r
72 UINT8 DieCount : 3; ///< Bits 6:4\r
73 UINT8 SdramPackageType : 1; ///< Bits 7:7\r
74 } Bits;\r
75 UINT8 Data;\r
76} SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT;\r
77\r
78typedef union {\r
79 struct {\r
80 UINT8 MaximumActivateCount : 4; ///< Bits 3:0\r
81 UINT8 MaximumActivateWindow : 2; ///< Bits 5:4\r
82 UINT8 Reserved : 2; ///< Bits 7:6\r
83 } Bits;\r
84 UINT8 Data;\r
85} SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT;\r
86\r
87typedef union {\r
88 struct {\r
89 UINT8 Reserved : 8; ///< Bits 7:0\r
90 } Bits;\r
91 UINT8 Data;\r
92} SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT;\r
93\r
94typedef union {\r
95 struct {\r
96 UINT8 Reserved : 5; ///< Bits 4:0\r
97 UINT8 SoftPPR : 1; ///< Bits 5:5\r
98 UINT8 PostPackageRepair : 2; ///< Bits 7:6\r
99 } Bits;\r
100 UINT8 Data;\r
101} SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT;\r
102\r
103typedef union {\r
104 struct {\r
105 UINT8 OperationAt1_20 : 1; ///< Bits 0:0\r
106 UINT8 EndurantAt1_20 : 1; ///< Bits 1:1\r
107 UINT8 OperationAt1_10 : 1; ///< Bits 2:2\r
108 UINT8 EndurantAt1_10 : 1; ///< Bits 3:3\r
109 UINT8 OperationAtTBD2V : 1; ///< Bits 4:4\r
110 UINT8 EndurantAtTBD2V : 1; ///< Bits 5:5\r
111 UINT8 Reserved : 2; ///< Bits 7:6\r
112 } Bits;\r
113 UINT8 Data;\r
114} SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT;\r
115\r
116typedef union {\r
117 struct {\r
118 UINT8 SdramDeviceWidth : 3; ///< Bits 2:0\r
119 UINT8 RankCount : 3; ///< Bits 5:3\r
120 UINT8 Reserved : 2; ///< Bits 7:6\r
121 } Bits;\r
122 UINT8 Data;\r
123} SPD_LPDDR_MODULE_ORGANIZATION_STRUCT;\r
124\r
125typedef union {\r
126 struct {\r
127 UINT8 PrimaryBusWidth : 3; ///< Bits 2:0\r
128 UINT8 BusWidthExtension : 2; ///< Bits 4:3\r
129 UINT8 NumberofChannels : 3; ///< Bits 7:5\r
130 } Bits;\r
131 UINT8 Data;\r
132} SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT;\r
133\r
134typedef union {\r
135 struct {\r
136 UINT8 Reserved : 7; ///< Bits 6:0\r
137 UINT8 ThermalSensorPresence : 1; ///< Bits 7:7\r
138 } Bits;\r
139 UINT8 Data;\r
140} SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT;\r
141\r
142typedef union {\r
143 struct {\r
144 UINT8 ExtendedBaseModuleType : 4; ///< Bits 3:0\r
145 UINT8 Reserved : 4; ///< Bits 7:4\r
146 } Bits;\r
147 UINT8 Data;\r
148} SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT;\r
149\r
150typedef union {\r
151 struct {\r
152 UINT8 ChipSelectLoading : 3; ///< Bits 2:0\r
153 UINT8 CommandAddressControlClockLoading : 3; ///< Bits 5:3\r
154 UINT8 DataStrobeMaskLoading : 2; ///< Bits 7:6\r
155 } Bits;\r
156 UINT8 Data;\r
157} SPD_LPDDR_SIGNAL_LOADING_STRUCT;\r
158\r
159typedef union {\r
160 struct {\r
161 UINT8 Fine : 2; ///< Bits 1:0\r
162 UINT8 Medium : 2; ///< Bits 3:2\r
163 UINT8 Reserved : 4; ///< Bits 7:4\r
164 } Bits;\r
165 UINT8 Data;\r
166} SPD_LPDDR_TIMEBASE_STRUCT;\r
167\r
168typedef union {\r
169 struct {\r
170 UINT8 tCKmin : 8; ///< Bits 7:0\r
171 } Bits;\r
172 UINT8 Data;\r
173} SPD_LPDDR_TCK_MIN_MTB_STRUCT;\r
174\r
175typedef union {\r
176 struct {\r
177 UINT8 tCKmax : 8; ///< Bits 7:0\r
178 } Bits;\r
179 UINT8 Data;\r
180} SPD_LPDDR_TCK_MAX_MTB_STRUCT;\r
181\r
182typedef union {\r
183 struct {\r
184 UINT32 Cl3 : 1; ///< Bits 0:0\r
185 UINT32 Cl6 : 1; ///< Bits 1:1\r
186 UINT32 Cl8 : 1; ///< Bits 2:2\r
187 UINT32 Cl9 : 1; ///< Bits 3:3\r
188 UINT32 Cl10 : 1; ///< Bits 4:4\r
189 UINT32 Cl11 : 1; ///< Bits 5:5\r
190 UINT32 Cl12 : 1; ///< Bits 6:6\r
191 UINT32 Cl14 : 1; ///< Bits 7:7\r
192 UINT32 Cl16 : 1; ///< Bits 8:8\r
193 UINT32 Reserved0 : 1; ///< Bits 9:9\r
194 UINT32 Cl20 : 1; ///< Bits 10:10\r
195 UINT32 Cl22 : 1; ///< Bits 11:11\r
196 UINT32 Cl24 : 1; ///< Bits 12:12\r
197 UINT32 Reserved1 : 1; ///< Bits 13:13\r
198 UINT32 Cl28 : 1; ///< Bits 14:14\r
199 UINT32 Reserved2 : 1; ///< Bits 15:15\r
200 UINT32 Cl32 : 1; ///< Bits 16:16\r
201 UINT32 Reserved3 : 1; ///< Bits 17:17\r
202 UINT32 Cl36 : 1; ///< Bits 18:18\r
203 UINT32 Reserved4 : 1; ///< Bits 19:19\r
204 UINT32 Cl40 : 1; ///< Bits 20:20\r
205 UINT32 Reserved5 : 11; ///< Bits 31:21\r
206 } Bits;\r
207 UINT32 Data;\r
208 UINT16 Data16[2];\r
209 UINT8 Data8[4];\r
210} SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT;\r
211\r
212typedef union {\r
213 struct {\r
214 UINT8 tAAmin : 8; ///< Bits 7:0\r
215 } Bits;\r
216 UINT8 Data;\r
217} SPD_LPDDR_TAA_MIN_MTB_STRUCT;\r
218\r
219typedef union {\r
220 struct {\r
221 UINT8 ReadLatencyMode : 2; ///< Bits 1:0\r
222 UINT8 WriteLatencySet : 2; ///< Bits 3:2\r
223 UINT8 Reserved : 4; ///< Bits 7:4\r
224 } Bits;\r
225 UINT8 Data;\r
226} SPD_LPDDR_RW_LATENCY_OPTION_STRUCT;\r
227\r
228typedef union {\r
229 struct {\r
230 UINT8 tRCDmin : 8; ///< Bits 7:0\r
231 } Bits;\r
232 UINT8 Data;\r
233} SPD_LPDDR_TRCD_MIN_MTB_STRUCT;\r
234\r
235typedef union {\r
236 struct {\r
237 UINT8 tRPab : 8; ///< Bits 7:0\r
238 } Bits;\r
239 UINT8 Data;\r
240} SPD_LPDDR_TRP_AB_MTB_STRUCT;\r
241\r
242typedef union {\r
243 struct {\r
244 UINT8 tRPpb : 8; ///< Bits 7:0\r
245 } Bits;\r
246 UINT8 Data;\r
247} SPD_LPDDR_TRP_PB_MTB_STRUCT;\r
248\r
249typedef union {\r
250 struct {\r
251 UINT16 tRFCab : 16; ///< Bits 15:0\r
252 } Bits;\r
253 UINT16 Data;\r
254 UINT8 Data8[2];\r
255} SPD_LPDDR_TRFC_AB_MTB_STRUCT;\r
256\r
257typedef union {\r
258struct {\r
259 UINT16 tRFCpb : 16; ///< Bits 15:0\r
260 } Bits;\r
261 UINT16 Data;\r
262 UINT8 Data8[2];\r
263} SPD_LPDDR_TRFC_PB_MTB_STRUCT;\r
264\r
265typedef union {\r
266 struct {\r
267 UINT8 BitOrderatSDRAM : 5; ///< Bits 4:0\r
268 UINT8 WiredtoUpperLowerNibble : 1; ///< Bits 5:5\r
269 UINT8 PackageRankMap : 2; ///< Bits 7:6\r
270 } Bits;\r
271 UINT8 Data;\r
272} SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT;\r
273\r
274typedef union {\r
275 struct {\r
276 INT8 tRPpbFine : 8; ///< Bits 7:0\r
277 } Bits;\r
278 INT8 Data;\r
279} SPD_LPDDR_TRP_PB_FTB_STRUCT;\r
280\r
281typedef union {\r
282 struct {\r
283 INT8 tRPabFine : 8; ///< Bits 7:0\r
284 } Bits;\r
285 INT8 Data;\r
286} SPD_LPDDR_TRP_AB_FTB_STRUCT;\r
287\r
288typedef union {\r
289 struct {\r
290 INT8 tRCDminFine : 8; ///< Bits 7:0\r
291 } Bits;\r
292 INT8 Data;\r
293} SPD_LPDDR_TRCD_MIN_FTB_STRUCT;\r
294\r
295typedef union {\r
296 struct {\r
297 INT8 tAAminFine : 8; ///< Bits 7:0\r
298 } Bits;\r
299 INT8 Data;\r
300} SPD_LPDDR_TAA_MIN_FTB_STRUCT;\r
301\r
302typedef union {\r
303 struct {\r
304 INT8 tCKmaxFine : 8; ///< Bits 7:0\r
305 } Bits;\r
306 INT8 Data;\r
307} SPD_LPDDR_TCK_MAX_FTB_STRUCT;\r
308\r
309typedef union {\r
310 struct {\r
311 INT8 tCKminFine : 8; ///< Bits 7:0\r
312 } Bits;\r
313 INT8 Data;\r
314} SPD_LPDDR_TCK_MIN_FTB_STRUCT;\r
315\r
316typedef union {\r
317 struct {\r
318 UINT16 ContinuationCount : 7; ///< Bits 6:0\r
319 UINT16 ContinuationParity : 1; ///< Bits 7:7\r
320 UINT16 LastNonZeroByte : 8; ///< Bits 15:8\r
321 } Bits;\r
322 UINT16 Data;\r
323 UINT8 Data8[2];\r
324} SPD_LPDDR_MANUFACTURER_ID_CODE;\r
325\r
326typedef struct {\r
327 UINT8 Location; ///< Module Manufacturing Location\r
328} SPD_LPDDR_MANUFACTURING_LOCATION;\r
329\r
330typedef struct {\r
331 UINT8 Year; ///< Year represented in BCD (00h = 2000)\r
332 UINT8 Week; ///< Year represented in BCD (47h = week 47)\r
333} SPD_LPDDR_MANUFACTURING_DATE;\r
334\r
335typedef union {\r
336 UINT32 Data;\r
337 UINT16 SerialNumber16[2];\r
338 UINT8 SerialNumber8[4];\r
339} SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER;\r
340\r
341typedef struct {\r
342 SPD_LPDDR_MANUFACTURER_ID_CODE IdCode; ///< Module Manufacturer ID Code\r
343 SPD_LPDDR_MANUFACTURING_LOCATION Location; ///< Module Manufacturing Location\r
344 SPD_LPDDR_MANUFACTURING_DATE Date; ///< Module Manufacturing Year, in BCD (range: 2000-2255)\r
345 SPD_LPDDR_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Module Serial Number\r
346} SPD_LPDDR_UNIQUE_MODULE_ID;\r
347\r
348typedef union {\r
349 struct {\r
350 UINT8 FrontThickness : 4; ///< Bits 3:0\r
351 UINT8 BackThickness : 4; ///< Bits 7:4\r
352 } Bits;\r
353 UINT8 Data;\r
354} SPD_LPDDR_MODULE_MAXIMUM_THICKNESS;\r
355\r
356typedef union {\r
357 struct {\r
358 UINT8 Height : 5; ///< Bits 4:0\r
359 UINT8 RawCardExtension : 3; ///< Bits 7:5\r
360 } Bits;\r
361 UINT8 Data;\r
362} SPD_LPDDR_MODULE_NOMINAL_HEIGHT;\r
363\r
364typedef union {\r
365 struct {\r
366 UINT8 Card : 5; ///< Bits 4:0\r
367 UINT8 Revision : 2; ///< Bits 6:5\r
368 UINT8 Extension : 1; ///< Bits 7:7\r
369 } Bits;\r
370 UINT8 Data;\r
371} SPD_LPDDR_REFERENCE_RAW_CARD;\r
372\r
373typedef union {\r
374 UINT16 Crc[1];\r
375 UINT8 Data8[2];\r
376} SPD_LPDDR_CYCLIC_REDUNDANCY_CODE;\r
377\r
378typedef struct {\r
379 SPD_LPDDR_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2\r
380 SPD_LPDDR_REVISION_STRUCT Revision; ///< 1 SPD Revision\r
381 SPD_LPDDR_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 DRAM Device Type\r
382 SPD_LPDDR_MODULE_TYPE_STRUCT ModuleType; ///< 3 Module Type\r
383 SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 SDRAM Density and Banks\r
384 SPD_LPDDR_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 SDRAM Addressing\r
385 SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT SdramPackageType; ///< 6 SDRAM Package Type\r
386 SPD_LPDDR_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 7 SDRAM Optional Features\r
387 SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 8 SDRAM Thermal and Refresh Options\r
388 SPD_LPDDR_OTHER_SDRAM_OPTIONAL_FEATURES_STRUCT OtherOptionalFeatures; ///< 9 Other SDRAM Optional Features\r
389 UINT8 Reserved0; ///< 10 Reserved\r
390 SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 11 Module Nominal Voltage, VDD\r
391 SPD_LPDDR_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 12 Module Organization\r
392 SPD_LPDDR_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 13 Module Memory Bus Width\r
393 SPD_LPDDR_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 14 Module Thermal Sensor\r
394 SPD_LPDDR_EXTENDED_MODULE_TYPE_STRUCT ExtendedModuleType; ///< 15 Extended Module Type\r
395 SPD_LPDDR_SIGNAL_LOADING_STRUCT SignalLoading; ///< 16 Signal Loading\r
396 SPD_LPDDR_TIMEBASE_STRUCT Timebase; ///< 17 Timebases\r
397 SPD_LPDDR_TCK_MIN_MTB_STRUCT tCKmin; ///< 18 SDRAM Minimum Cycle Time (tCKmin)\r
398 SPD_LPDDR_TCK_MAX_MTB_STRUCT tCKmax; ///< 19 SDRAM Maximum Cycle Time (tCKmax)\r
399 SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 20-23 CAS Latencies Supported\r
400 SPD_LPDDR_TAA_MIN_MTB_STRUCT tAAmin; ///< 24 Minimum CAS Latency Time (tAAmin)\r
401 SPD_LPDDR_RW_LATENCY_OPTION_STRUCT LatencySetOptions; ///< 25 Read and Write Latency Set Options\r
402 SPD_LPDDR_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 26 Minimum RAS# to CAS# Delay Time (tRCDmin)\r
403 SPD_LPDDR_TRP_AB_MTB_STRUCT tRPab; ///< 27 Minimum Row Precharge Delay Time (tRPab), all banks\r
404 SPD_LPDDR_TRP_PB_MTB_STRUCT tRPpb; ///< 28 Minimum Row Precharge Delay Time (tRPpb), per bank\r
405 SPD_LPDDR_TRFC_AB_MTB_STRUCT tRFCab; ///< 29-30 Minimum Refresh Recovery Delay Time (tRFCab), all banks\r
406 SPD_LPDDR_TRFC_PB_MTB_STRUCT tRFCpb; ///< 31-32 Minimum Refresh Recovery Delay Time (tRFCpb), per bank\r
407 UINT8 Reserved1[59 - 33 + 1]; ///< 33-59 Reserved\r
408 SPD_LPDDR_CONNECTOR_BIT_MAPPING_BYTE_STRUCT BitMapping[77 - 60 + 1]; ///< 60-77 Connector to SDRAM Bit Mapping\r
409 UINT8 Reserved2[119 - 78 + 1]; ///< 78-119 Reserved\r
410 SPD_LPDDR_TRP_PB_FTB_STRUCT tRPpbFine; ///< 120 Fine Offset for Minimum Row Precharge Delay Time (tRPpbFine), per bank\r
411 SPD_LPDDR_TRP_AB_FTB_STRUCT tRPabFine; ///< 121 Fine Offset for Minimum Row Precharge Delay Time (tRPabFine), all ranks\r
412 SPD_LPDDR_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin)\r
413 SPD_LPDDR_TAA_MIN_FTB_STRUCT tAAminFine; ///< 123 Fine Offset for Minimum CAS Latency Time (tAAmin)\r
414 SPD_LPDDR_TCK_MAX_FTB_STRUCT tCKmaxFine; ///< 124 Fine Offset for SDRAM Maximum Cycle Time (tCKmax)\r
415 SPD_LPDDR_TCK_MIN_FTB_STRUCT tCKminFine; ///< 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin)\r
416 SPD_LPDDR_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-127 Cyclical Redundancy Code (CRC)\r
417} SPD_LPDDR_BASE_SECTION;\r
418\r
419typedef struct {\r
420 SPD_LPDDR_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 Module Nominal Height\r
421 SPD_LPDDR_MODULE_MAXIMUM_THICKNESS ModuleMaximumThickness; ///< 129 Module Maximum Thickness\r
422 SPD_LPDDR_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 Reference Raw Card Used\r
423 UINT8 Reserved[253 - 131 + 1]; ///< 131-253 Reserved\r
424 SPD_LPDDR_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-255 Cyclical Redundancy Code (CRC)\r
425} SPD_LPDDR_MODULE_LPDIMM;\r
426\r
427typedef struct {\r
428 SPD_LPDDR_MODULE_LPDIMM LpDimm; ///< 128-255 Unbuffered Memory Module Types\r
429} SPD_LPDDR_MODULE_SPECIFIC;\r
430\r
431typedef struct {\r
432 UINT8 ModulePartNumber[348 - 329 + 1]; ///< 329-348 Module Part Number\r
433} SPD_LPDDR_MODULE_PART_NUMBER;\r
434\r
435typedef struct {\r
436 UINT8 ManufacturerSpecificData[381 - 353 + 1]; ///< 353-381 Manufacturer's Specific Data\r
437} SPD_LPDDR_MANUFACTURER_SPECIFIC;\r
438\r
439typedef UINT8 SPD_LPDDR_MODULE_REVISION_CODE;///< 349 Module Revision Code\r
440typedef UINT8 SPD_LPDDR_DRAM_STEPPING; ///< 352 Dram Stepping\r
441\r
442typedef struct {\r
443 SPD_LPDDR_UNIQUE_MODULE_ID ModuleId; ///< 320-328 Unique Module ID\r
444 SPD_LPDDR_MODULE_PART_NUMBER ModulePartNumber; ///< 329-348 Module Part Number\r
445 SPD_LPDDR_MODULE_REVISION_CODE ModuleRevisionCode; ///< 349 Module Revision Code\r
446 SPD_LPDDR_MANUFACTURER_ID_CODE DramIdCode; ///< 350-351 Dram Manufacturer ID Code\r
447 SPD_LPDDR_DRAM_STEPPING DramStepping; ///< 352 Dram Stepping\r
448 SPD_LPDDR_MANUFACTURER_SPECIFIC ManufacturerSpecificData; ///< 353-381 Manufacturer's Specific Data\r
449 UINT8 Reserved[383 - 382 + 1]; ///< 382-383 Reserved\r
450} SPD_LPDDR_MANUFACTURING_DATA;\r
451\r
452typedef struct {\r
453 UINT8 Reserved[511 - 384 + 1]; ///< 384-511 End User Programmable\r
454} SPD_LPDDR_END_USER_SECTION;\r
455\r
456///\r
457/// LPDDR Serial Presence Detect structure\r
458///\r
459typedef struct {\r
460 SPD_LPDDR_BASE_SECTION Base; ///< 0-127 Base Configuration and DRAM Parameters\r
461 SPD_LPDDR_MODULE_SPECIFIC Module; ///< 128-255 Module-Specific Section\r
462 UINT8 Reserved[319 - 256 + 1]; ///< 256-319 Hybrid Memory Parameters\r
463 SPD_LPDDR_MANUFACTURING_DATA ManufactureInfo; ///< 320-383 Manufacturing Information\r
464 SPD_LPDDR_END_USER_SECTION EndUser; ///< 384-511 End User Programmable\r
465} SPD_LPDDR;\r
466\r
467#pragma pack (pop)\r
468#endif\r
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