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1 | /** @file\r |
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2 | Provides services to access PCI Configuration Space using the I/O ports 0xCF8 and 0xCFC.\r |
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3 | \r |
| 4 | This library is identical to the PCI Library, except the access method for performing PCI \r |
| 5 | configuration cycles must be though I/O ports 0xCF8 and 0xCFC. This library only allows \r |
| 6 | access to PCI Segment #0.\r |
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7 | \r |
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8 | Copyright (c) 2006 - 2008, Intel Corporation<BR>\r |
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9 | All rights reserved. This program and the accompanying materials\r |
| 10 | are licensed and made available under the terms and conditions of the BSD License\r |
| 11 | which accompanies this distribution. The full text of the license may be found at\r |
| 12 | http://opensource.org/licenses/bsd-license.php\r |
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13 | \r |
| 50a64e5b |
14 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 15 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| fb3df220 |
16 | \r |
| fb3df220 |
17 | **/\r |
| 18 | \r |
| 19 | #ifndef __PCI_CF8_LIB_H__\r |
| 20 | #define __PCI_CF8_LIB_H__\r |
| 21 | \r |
| 22 | \r |
| 23 | /**\r |
| 24 | Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an\r |
| 25 | address that can be passed to the PCI Library functions.\r |
| 26 | \r |
| 27 | Computes an address that is compatible with the PCI Library functions. The\r |
| 28 | unused upper bits of Bus, Device, Function and Register are stripped prior to\r |
| 29 | the generation of the address.\r |
| 30 | \r |
| 31 | @param Bus PCI Bus number. Range 0..255.\r |
| 32 | @param Device PCI Device number. Range 0..31.\r |
| 33 | @param Function PCI Function number. Range 0..7.\r |
| 34 | @param Register PCI Register number. Range 0..255.\r |
| 35 | \r |
| 36 | @return The encode PCI address.\r |
| 37 | \r |
| 38 | **/\r |
| 39 | #define PCI_CF8_LIB_ADDRESS(Bus,Device,Function,Offset) \\r |
| 40 | (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r |
| 41 | \r |
| f926e538 |
42 | /**\r |
| 43 | Register a PCI device so PCI configuration registers may be accessed after \r |
| 44 | SetVirtualAddressMap().\r |
| 45 | \r |
| 46 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 47 | \r |
| 48 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 49 | Register.\r |
| 50 | \r |
| 51 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r |
| 52 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r |
| 53 | after ExitBootServices().\r |
| 54 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r |
| 55 | at runtime could not be mapped.\r |
| 56 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r |
| 57 | complete the registration.\r |
| 58 | \r |
| 59 | **/\r |
| 60 | RETURN_STATUS\r |
| 61 | EFIAPI\r |
| 62 | PciCf8RegisterForRuntimeAccess (\r |
| 63 | IN UINTN Address\r |
| 64 | );\r |
| 65 | \r |
| fb3df220 |
66 | /**\r |
| 67 | Reads an 8-bit PCI configuration register.\r |
| 68 | \r |
| 69 | Reads and returns the 8-bit PCI configuration register specified by Address.\r |
| 70 | This function must guarantee that all PCI read and write operations are\r |
| 71 | serialized.\r |
| 72 | \r |
| 73 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 74 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 75 | \r |
| 76 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 77 | Register.\r |
| 78 | \r |
| 79 | @return The read value from the PCI configuration register.\r |
| 80 | \r |
| 81 | **/\r |
| 82 | UINT8\r |
| 83 | EFIAPI\r |
| 84 | PciCf8Read8 (\r |
| 85 | IN UINTN Address\r |
| 86 | );\r |
| 87 | \r |
| 88 | /**\r |
| 89 | Writes an 8-bit PCI configuration register.\r |
| 90 | \r |
| 91 | Writes the 8-bit PCI configuration register specified by Address with the\r |
| 92 | value specified by Value. Value is returned. This function must guarantee\r |
| 93 | that all PCI read and write operations are serialized.\r |
| 94 | \r |
| 95 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 96 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 97 | \r |
| 98 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 99 | Register.\r |
| 100 | @param Value The value to write.\r |
| 101 | \r |
| 102 | @return The value written to the PCI configuration register.\r |
| 103 | \r |
| 104 | **/\r |
| 105 | UINT8\r |
| 106 | EFIAPI\r |
| 107 | PciCf8Write8 (\r |
| 108 | IN UINTN Address,\r |
| 94646ec0 |
109 | IN UINT8 Value\r |
| fb3df220 |
110 | );\r |
| 111 | \r |
| 112 | /**\r |
| 113 | Performs a bitwise inclusive OR of an 8-bit PCI configuration register with\r |
| 114 | an 8-bit value.\r |
| 115 | \r |
| 116 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 117 | bitwise inclusive OR between the read result and the value specified by\r |
| 118 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| 119 | specified by Address. The value written to the PCI configuration register is\r |
| 120 | returned. This function must guarantee that all PCI read and write operations\r |
| 121 | are serialized.\r |
| 122 | \r |
| 123 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 124 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 125 | \r |
| 126 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 127 | Register.\r |
| 128 | @param OrData The value to OR with the PCI configuration register.\r |
| 129 | \r |
| 130 | @return The value written back to the PCI configuration register.\r |
| 131 | \r |
| 132 | **/\r |
| 133 | UINT8\r |
| 134 | EFIAPI\r |
| 135 | PciCf8Or8 (\r |
| 136 | IN UINTN Address,\r |
| 137 | IN UINT8 OrData\r |
| 138 | );\r |
| 139 | \r |
| 140 | /**\r |
| 141 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
| 142 | value.\r |
| 143 | \r |
| 144 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 145 | bitwise AND between the read result and the value specified by AndData, and\r |
| 146 | writes the result to the 8-bit PCI configuration register specified by\r |
| 147 | Address. The value written to the PCI configuration register is returned.\r |
| 148 | This function must guarantee that all PCI read and write operations are\r |
| 149 | serialized.\r |
| 150 | \r |
| 151 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 152 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 153 | \r |
| 154 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 155 | Register.\r |
| 156 | @param AndData The value to AND with the PCI configuration register.\r |
| 157 | \r |
| 158 | @return The value written back to the PCI configuration register.\r |
| 159 | \r |
| 160 | **/\r |
| 161 | UINT8\r |
| 162 | EFIAPI\r |
| 163 | PciCf8And8 (\r |
| 164 | IN UINTN Address,\r |
| 165 | IN UINT8 AndData\r |
| 166 | );\r |
| 167 | \r |
| 168 | /**\r |
| 169 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
| 170 | value, followed a bitwise inclusive OR with another 8-bit value.\r |
| 171 | \r |
| 172 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 173 | bitwise AND between the read result and the value specified by AndData,\r |
| 174 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 175 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
| 176 | configuration register specified by Address. The value written to the PCI\r |
| 177 | configuration register is returned. This function must guarantee that all PCI\r |
| 178 | read and write operations are serialized.\r |
| 179 | \r |
| 180 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 181 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 182 | \r |
| 183 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 184 | Register.\r |
| 185 | @param AndData The value to AND with the PCI configuration register.\r |
| 186 | @param OrData The value to OR with the result of the AND operation.\r |
| 187 | \r |
| 188 | @return The value written back to the PCI configuration register.\r |
| 189 | \r |
| 190 | **/\r |
| 191 | UINT8\r |
| 192 | EFIAPI\r |
| 193 | PciCf8AndThenOr8 (\r |
| 194 | IN UINTN Address,\r |
| 195 | IN UINT8 AndData,\r |
| 196 | IN UINT8 OrData\r |
| 197 | );\r |
| 198 | \r |
| 199 | /**\r |
| 200 | Reads a bit field of a PCI configuration register.\r |
| 201 | \r |
| 202 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r |
| 203 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 204 | returned.\r |
| 205 | \r |
| 206 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 207 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 208 | If StartBit is greater than 7, then ASSERT().\r |
| 209 | If EndBit is greater than 7, then ASSERT().\r |
| 210 | If EndBit is less than StartBit, then ASSERT().\r |
| 211 | \r |
| 212 | @param Address PCI configuration register to read.\r |
| 213 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 214 | Range 0..7.\r |
| 215 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 216 | Range 0..7.\r |
| 217 | \r |
| 218 | @return The value of the bit field read from the PCI configuration register.\r |
| 219 | \r |
| 220 | **/\r |
| 221 | UINT8\r |
| 222 | EFIAPI\r |
| 223 | PciCf8BitFieldRead8 (\r |
| 224 | IN UINTN Address,\r |
| 225 | IN UINTN StartBit,\r |
| 226 | IN UINTN EndBit\r |
| 227 | );\r |
| 228 | \r |
| 229 | /**\r |
| 230 | Writes a bit field to a PCI configuration register.\r |
| 231 | \r |
| 232 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 233 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 234 | destination PCI configuration register are preserved. The new value of the\r |
| 235 | 8-bit register is returned.\r |
| 236 | \r |
| 237 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 238 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 239 | If StartBit is greater than 7, then ASSERT().\r |
| 240 | If EndBit is greater than 7, then ASSERT().\r |
| 241 | If EndBit is less than StartBit, then ASSERT().\r |
| 242 | \r |
| 243 | @param Address PCI configuration register to write.\r |
| 244 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 245 | Range 0..7.\r |
| 246 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 247 | Range 0..7.\r |
| 248 | @param Value New value of the bit field.\r |
| 249 | \r |
| 250 | @return The value written back to the PCI configuration register.\r |
| 251 | \r |
| 252 | **/\r |
| 253 | UINT8\r |
| 254 | EFIAPI\r |
| 255 | PciCf8BitFieldWrite8 (\r |
| 256 | IN UINTN Address,\r |
| 257 | IN UINTN StartBit,\r |
| 258 | IN UINTN EndBit,\r |
| 259 | IN UINT8 Value\r |
| 260 | );\r |
| 261 | \r |
| 262 | /**\r |
| 263 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r |
| 264 | writes the result back to the bit field in the 8-bit port.\r |
| 265 | \r |
| 266 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 267 | bitwise inclusive OR between the read result and the value specified by\r |
| 268 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| 269 | specified by Address. The value written to the PCI configuration register is\r |
| 270 | returned. This function must guarantee that all PCI read and write operations\r |
| 271 | are serialized. Extra left bits in OrData are stripped.\r |
| 272 | \r |
| 273 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 274 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 275 | If StartBit is greater than 7, then ASSERT().\r |
| 276 | If EndBit is greater than 7, then ASSERT().\r |
| 277 | If EndBit is less than StartBit, then ASSERT().\r |
| 278 | \r |
| 279 | @param Address PCI configuration register to write.\r |
| 280 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 281 | Range 0..7.\r |
| 282 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 283 | Range 0..7.\r |
| 284 | @param OrData The value to OR with the PCI configuration register.\r |
| 285 | \r |
| 286 | @return The value written back to the PCI configuration register.\r |
| 287 | \r |
| 288 | **/\r |
| 289 | UINT8\r |
| 290 | EFIAPI\r |
| 291 | PciCf8BitFieldOr8 (\r |
| 292 | IN UINTN Address,\r |
| 293 | IN UINTN StartBit,\r |
| 294 | IN UINTN EndBit,\r |
| 295 | IN UINT8 OrData\r |
| 296 | );\r |
| 297 | \r |
| 298 | /**\r |
| 299 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r |
| 300 | AND, and writes the result back to the bit field in the 8-bit register.\r |
| 301 | \r |
| 302 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 303 | bitwise AND between the read result and the value specified by AndData, and\r |
| 304 | writes the result to the 8-bit PCI configuration register specified by\r |
| 305 | Address. The value written to the PCI configuration register is returned.\r |
| 306 | This function must guarantee that all PCI read and write operations are\r |
| 307 | serialized. Extra left bits in AndData are stripped.\r |
| 308 | \r |
| 309 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 310 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 311 | If StartBit is greater than 7, then ASSERT().\r |
| 312 | If EndBit is greater than 7, then ASSERT().\r |
| 313 | If EndBit is less than StartBit, then ASSERT().\r |
| 314 | \r |
| 315 | @param Address PCI configuration register to write.\r |
| 316 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 317 | Range 0..7.\r |
| 318 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 319 | Range 0..7.\r |
| 320 | @param AndData The value to AND with the PCI configuration register.\r |
| 321 | \r |
| 322 | @return The value written back to the PCI configuration register.\r |
| 323 | \r |
| 324 | **/\r |
| 325 | UINT8\r |
| 326 | EFIAPI\r |
| 327 | PciCf8BitFieldAnd8 (\r |
| 328 | IN UINTN Address,\r |
| 329 | IN UINTN StartBit,\r |
| 330 | IN UINTN EndBit,\r |
| 331 | IN UINT8 AndData\r |
| 332 | );\r |
| 333 | \r |
| 334 | /**\r |
| 335 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r |
| 336 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 337 | 8-bit port.\r |
| 338 | \r |
| 339 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 340 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 341 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
| 342 | configuration register specified by Address. The value written to the PCI\r |
| 343 | configuration register is returned. This function must guarantee that all PCI\r |
| 344 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 345 | OrData are stripped.\r |
| 346 | \r |
| 347 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 348 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 349 | If StartBit is greater than 7, then ASSERT().\r |
| 350 | If EndBit is greater than 7, then ASSERT().\r |
| 351 | If EndBit is less than StartBit, then ASSERT().\r |
| 352 | \r |
| 353 | @param Address PCI configuration register to write.\r |
| 354 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 355 | Range 0..7.\r |
| 356 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 357 | Range 0..7.\r |
| 358 | @param AndData The value to AND with the PCI configuration register.\r |
| 359 | @param OrData The value to OR with the result of the AND operation.\r |
| 360 | \r |
| 361 | @return The value written back to the PCI configuration register.\r |
| 362 | \r |
| 363 | **/\r |
| 364 | UINT8\r |
| 365 | EFIAPI\r |
| 366 | PciCf8BitFieldAndThenOr8 (\r |
| 367 | IN UINTN Address,\r |
| 368 | IN UINTN StartBit,\r |
| 369 | IN UINTN EndBit,\r |
| 370 | IN UINT8 AndData,\r |
| 371 | IN UINT8 OrData\r |
| 372 | );\r |
| 373 | \r |
| 374 | /**\r |
| 375 | Reads a 16-bit PCI configuration register.\r |
| 376 | \r |
| 377 | Reads and returns the 16-bit PCI configuration register specified by Address.\r |
| 378 | This function must guarantee that all PCI read and write operations are\r |
| 379 | serialized.\r |
| 380 | \r |
| 381 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 382 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 383 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 384 | \r |
| 385 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 386 | Register.\r |
| 387 | \r |
| 388 | @return The read value from the PCI configuration register.\r |
| 389 | \r |
| 390 | **/\r |
| 391 | UINT16\r |
| 392 | EFIAPI\r |
| 393 | PciCf8Read16 (\r |
| 394 | IN UINTN Address\r |
| 395 | );\r |
| 396 | \r |
| 397 | /**\r |
| 398 | Writes a 16-bit PCI configuration register.\r |
| 399 | \r |
| 400 | Writes the 16-bit PCI configuration register specified by Address with the\r |
| 401 | value specified by Value. Value is returned. This function must guarantee\r |
| 402 | that all PCI read and write operations are serialized.\r |
| 403 | \r |
| 404 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 405 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 406 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 407 | \r |
| 408 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 409 | Register.\r |
| 410 | @param Value The value to write.\r |
| 411 | \r |
| 412 | @return The value written to the PCI configuration register.\r |
| 413 | \r |
| 414 | **/\r |
| 415 | UINT16\r |
| 416 | EFIAPI\r |
| 417 | PciCf8Write16 (\r |
| 418 | IN UINTN Address,\r |
| 94646ec0 |
419 | IN UINT16 Value\r |
| fb3df220 |
420 | );\r |
| 421 | \r |
| 422 | /**\r |
| 423 | Performs a bitwise inclusive OR of a 16-bit PCI configuration register with\r |
| 424 | a 16-bit value.\r |
| 425 | \r |
| 426 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 427 | bitwise inclusive OR between the read result and the value specified by\r |
| 428 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| 429 | specified by Address. The value written to the PCI configuration register is\r |
| 430 | returned. This function must guarantee that all PCI read and write operations\r |
| 431 | are serialized.\r |
| 432 | \r |
| 433 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 434 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 435 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 436 | \r |
| 437 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 438 | Register.\r |
| 439 | @param OrData The value to OR with the PCI configuration register.\r |
| 440 | \r |
| 441 | @return The value written back to the PCI configuration register.\r |
| 442 | \r |
| 443 | **/\r |
| 444 | UINT16\r |
| 445 | EFIAPI\r |
| 446 | PciCf8Or16 (\r |
| 447 | IN UINTN Address,\r |
| 448 | IN UINT16 OrData\r |
| 449 | );\r |
| 450 | \r |
| 451 | /**\r |
| 452 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
| 453 | value.\r |
| 454 | \r |
| 455 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 456 | bitwise AND between the read result and the value specified by AndData, and\r |
| 457 | writes the result to the 16-bit PCI configuration register specified by\r |
| 458 | Address. The value written to the PCI configuration register is returned.\r |
| 459 | This function must guarantee that all PCI read and write operations are\r |
| 460 | serialized.\r |
| 461 | \r |
| 462 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 463 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 464 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 465 | \r |
| 466 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 467 | Register.\r |
| 468 | @param AndData The value to AND with the PCI configuration register.\r |
| 469 | \r |
| 470 | @return The value written back to the PCI configuration register.\r |
| 471 | \r |
| 472 | **/\r |
| 473 | UINT16\r |
| 474 | EFIAPI\r |
| 475 | PciCf8And16 (\r |
| 476 | IN UINTN Address,\r |
| 477 | IN UINT16 AndData\r |
| 478 | );\r |
| 479 | \r |
| 480 | /**\r |
| 481 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
| 482 | value, followed a bitwise inclusive OR with another 16-bit value.\r |
| 483 | \r |
| 484 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 485 | bitwise AND between the read result and the value specified by AndData,\r |
| 486 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 487 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
| 488 | configuration register specified by Address. The value written to the PCI\r |
| 489 | configuration register is returned. This function must guarantee that all PCI\r |
| 490 | read and write operations are serialized.\r |
| 491 | \r |
| 492 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 493 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 494 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 495 | \r |
| 496 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 497 | Register.\r |
| 498 | @param AndData The value to AND with the PCI configuration register.\r |
| 499 | @param OrData The value to OR with the result of the AND operation.\r |
| 500 | \r |
| 501 | @return The value written back to the PCI configuration register.\r |
| 502 | \r |
| 503 | **/\r |
| 504 | UINT16\r |
| 505 | EFIAPI\r |
| 506 | PciCf8AndThenOr16 (\r |
| 507 | IN UINTN Address,\r |
| 508 | IN UINT16 AndData,\r |
| 509 | IN UINT16 OrData\r |
| 510 | );\r |
| 511 | \r |
| 512 | /**\r |
| 513 | Reads a bit field of a PCI configuration register.\r |
| 514 | \r |
| 515 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r |
| 516 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 517 | returned.\r |
| 518 | \r |
| 519 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 520 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 521 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 522 | If StartBit is greater than 15, then ASSERT().\r |
| 523 | If EndBit is greater than 15, then ASSERT().\r |
| 524 | If EndBit is less than StartBit, then ASSERT().\r |
| 525 | \r |
| 526 | @param Address PCI configuration register to read.\r |
| 527 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 528 | Range 0..15.\r |
| 529 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 530 | Range 0..15.\r |
| 531 | \r |
| 532 | @return The value of the bit field read from the PCI configuration register.\r |
| 533 | \r |
| 534 | **/\r |
| 535 | UINT16\r |
| 536 | EFIAPI\r |
| 537 | PciCf8BitFieldRead16 (\r |
| 538 | IN UINTN Address,\r |
| 539 | IN UINTN StartBit,\r |
| 540 | IN UINTN EndBit\r |
| 541 | );\r |
| 542 | \r |
| 543 | /**\r |
| 544 | Writes a bit field to a PCI configuration register.\r |
| 545 | \r |
| 546 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 547 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 548 | destination PCI configuration register are preserved. The new value of the\r |
| 549 | 16-bit register is returned.\r |
| 550 | \r |
| 551 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 552 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 553 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 554 | If StartBit is greater than 15, then ASSERT().\r |
| 555 | If EndBit is greater than 15, then ASSERT().\r |
| 556 | If EndBit is less than StartBit, then ASSERT().\r |
| 557 | \r |
| 558 | @param Address PCI configuration register to write.\r |
| 559 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 560 | Range 0..15.\r |
| 561 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 562 | Range 0..15.\r |
| 563 | @param Value New value of the bit field.\r |
| 564 | \r |
| 565 | @return The value written back to the PCI configuration register.\r |
| 566 | \r |
| 567 | **/\r |
| 568 | UINT16\r |
| 569 | EFIAPI\r |
| 570 | PciCf8BitFieldWrite16 (\r |
| 571 | IN UINTN Address,\r |
| 572 | IN UINTN StartBit,\r |
| 573 | IN UINTN EndBit,\r |
| 574 | IN UINT16 Value\r |
| 575 | );\r |
| 576 | \r |
| 577 | /**\r |
| 578 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r |
| 579 | writes the result back to the bit field in the 16-bit port.\r |
| 580 | \r |
| 581 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 582 | bitwise inclusive OR between the read result and the value specified by\r |
| 583 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| 584 | specified by Address. The value written to the PCI configuration register is\r |
| 585 | returned. This function must guarantee that all PCI read and write operations\r |
| 586 | are serialized. Extra left bits in OrData are stripped.\r |
| 587 | \r |
| 588 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 589 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 590 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 591 | If StartBit is greater than 15, then ASSERT().\r |
| 592 | If EndBit is greater than 15, then ASSERT().\r |
| 593 | If EndBit is less than StartBit, then ASSERT().\r |
| 594 | \r |
| 595 | @param Address PCI configuration register to write.\r |
| 596 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 597 | Range 0..15.\r |
| 598 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 599 | Range 0..15.\r |
| 600 | @param OrData The value to OR with the PCI configuration register.\r |
| 601 | \r |
| 602 | @return The value written back to the PCI configuration register.\r |
| 603 | \r |
| 604 | **/\r |
| 605 | UINT16\r |
| 606 | EFIAPI\r |
| 607 | PciCf8BitFieldOr16 (\r |
| 608 | IN UINTN Address,\r |
| 609 | IN UINTN StartBit,\r |
| 610 | IN UINTN EndBit,\r |
| 611 | IN UINT16 OrData\r |
| 612 | );\r |
| 613 | \r |
| 614 | /**\r |
| 615 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r |
| 616 | AND, and writes the result back to the bit field in the 16-bit register.\r |
| 617 | \r |
| 618 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 619 | bitwise AND between the read result and the value specified by AndData, and\r |
| 620 | writes the result to the 16-bit PCI configuration register specified by\r |
| 621 | Address. The value written to the PCI configuration register is returned.\r |
| 622 | This function must guarantee that all PCI read and write operations are\r |
| 623 | serialized. Extra left bits in AndData are stripped.\r |
| 624 | \r |
| 625 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 626 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 627 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 628 | If StartBit is greater than 15, then ASSERT().\r |
| 629 | If EndBit is greater than 15, then ASSERT().\r |
| 630 | If EndBit is less than StartBit, then ASSERT().\r |
| 631 | \r |
| 632 | @param Address PCI configuration register to write.\r |
| 633 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 634 | Range 0..15.\r |
| 635 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 636 | Range 0..15.\r |
| 637 | @param AndData The value to AND with the PCI configuration register.\r |
| 638 | \r |
| 639 | @return The value written back to the PCI configuration register.\r |
| 640 | \r |
| 641 | **/\r |
| 642 | UINT16\r |
| 643 | EFIAPI\r |
| 644 | PciCf8BitFieldAnd16 (\r |
| 645 | IN UINTN Address,\r |
| 646 | IN UINTN StartBit,\r |
| 647 | IN UINTN EndBit,\r |
| 648 | IN UINT16 AndData\r |
| 649 | );\r |
| 650 | \r |
| 651 | /**\r |
| 652 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r |
| 653 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 654 | 16-bit port.\r |
| 655 | \r |
| 656 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 657 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 658 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
| 659 | configuration register specified by Address. The value written to the PCI\r |
| 660 | configuration register is returned. This function must guarantee that all PCI\r |
| 661 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 662 | OrData are stripped.\r |
| 663 | \r |
| 664 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 665 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 666 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 667 | If StartBit is greater than 15, then ASSERT().\r |
| 668 | If EndBit is greater than 15, then ASSERT().\r |
| 669 | If EndBit is less than StartBit, then ASSERT().\r |
| 670 | \r |
| 671 | @param Address PCI configuration register to write.\r |
| 672 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 673 | Range 0..15.\r |
| 674 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 675 | Range 0..15.\r |
| 676 | @param AndData The value to AND with the PCI configuration register.\r |
| 677 | @param OrData The value to OR with the result of the AND operation.\r |
| 678 | \r |
| 679 | @return The value written back to the PCI configuration register.\r |
| 680 | \r |
| 681 | **/\r |
| 682 | UINT16\r |
| 683 | EFIAPI\r |
| 684 | PciCf8BitFieldAndThenOr16 (\r |
| 685 | IN UINTN Address,\r |
| 686 | IN UINTN StartBit,\r |
| 687 | IN UINTN EndBit,\r |
| 688 | IN UINT16 AndData,\r |
| 689 | IN UINT16 OrData\r |
| 690 | );\r |
| 691 | \r |
| 692 | /**\r |
| 693 | Reads a 32-bit PCI configuration register.\r |
| 694 | \r |
| 695 | Reads and returns the 32-bit PCI configuration register specified by Address.\r |
| 696 | This function must guarantee that all PCI read and write operations are\r |
| 697 | serialized.\r |
| 698 | \r |
| 699 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 700 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 701 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 702 | \r |
| 703 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 704 | Register.\r |
| 705 | \r |
| 706 | @return The read value from the PCI configuration register.\r |
| 707 | \r |
| 708 | **/\r |
| 709 | UINT32\r |
| 710 | EFIAPI\r |
| 711 | PciCf8Read32 (\r |
| 712 | IN UINTN Address\r |
| 713 | );\r |
| 714 | \r |
| 715 | /**\r |
| 716 | Writes a 32-bit PCI configuration register.\r |
| 717 | \r |
| 718 | Writes the 32-bit PCI configuration register specified by Address with the\r |
| 719 | value specified by Value. Value is returned. This function must guarantee\r |
| 720 | that all PCI read and write operations are serialized.\r |
| 721 | \r |
| 722 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 723 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 724 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 725 | \r |
| 726 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 727 | Register.\r |
| 728 | @param Value The value to write.\r |
| 729 | \r |
| 730 | @return The value written to the PCI configuration register.\r |
| 731 | \r |
| 732 | **/\r |
| 733 | UINT32\r |
| 734 | EFIAPI\r |
| 735 | PciCf8Write32 (\r |
| 736 | IN UINTN Address,\r |
| 94646ec0 |
737 | IN UINT32 Value\r |
| fb3df220 |
738 | );\r |
| 739 | \r |
| 740 | /**\r |
| 741 | Performs a bitwise inclusive OR of a 32-bit PCI configuration register with\r |
| 742 | a 32-bit value.\r |
| 743 | \r |
| 744 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 745 | bitwise inclusive OR between the read result and the value specified by\r |
| 746 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| 747 | specified by Address. The value written to the PCI configuration register is\r |
| 748 | returned. This function must guarantee that all PCI read and write operations\r |
| 749 | are serialized.\r |
| 750 | \r |
| 751 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 752 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 753 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 754 | \r |
| 755 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 756 | Register.\r |
| 757 | @param OrData The value to OR with the PCI configuration register.\r |
| 758 | \r |
| 759 | @return The value written back to the PCI configuration register.\r |
| 760 | \r |
| 761 | **/\r |
| 762 | UINT32\r |
| 763 | EFIAPI\r |
| 764 | PciCf8Or32 (\r |
| 765 | IN UINTN Address,\r |
| 766 | IN UINT32 OrData\r |
| 767 | );\r |
| 768 | \r |
| 769 | /**\r |
| 770 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
| 771 | value.\r |
| 772 | \r |
| 773 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 774 | bitwise AND between the read result and the value specified by AndData, and\r |
| 775 | writes the result to the 32-bit PCI configuration register specified by\r |
| 776 | Address. The value written to the PCI configuration register is returned.\r |
| 777 | This function must guarantee that all PCI read and write operations are\r |
| 778 | serialized.\r |
| 779 | \r |
| 780 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 781 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 782 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 783 | \r |
| 784 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 785 | Register.\r |
| 786 | @param AndData The value to AND with the PCI configuration register.\r |
| 787 | \r |
| 788 | @return The value written back to the PCI configuration register.\r |
| 789 | \r |
| 790 | **/\r |
| 791 | UINT32\r |
| 792 | EFIAPI\r |
| 793 | PciCf8And32 (\r |
| 794 | IN UINTN Address,\r |
| 795 | IN UINT32 AndData\r |
| 796 | );\r |
| 797 | \r |
| 798 | /**\r |
| 799 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
| 800 | value, followed a bitwise inclusive OR with another 32-bit value.\r |
| 801 | \r |
| 802 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 803 | bitwise AND between the read result and the value specified by AndData,\r |
| 804 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 805 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
| 806 | configuration register specified by Address. The value written to the PCI\r |
| 807 | configuration register is returned. This function must guarantee that all PCI\r |
| 808 | read and write operations are serialized.\r |
| 809 | \r |
| 810 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 811 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 812 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 813 | \r |
| 814 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 815 | Register.\r |
| 816 | @param AndData The value to AND with the PCI configuration register.\r |
| 817 | @param OrData The value to OR with the result of the AND operation.\r |
| 818 | \r |
| 819 | @return The value written back to the PCI configuration register.\r |
| 820 | \r |
| 821 | **/\r |
| 822 | UINT32\r |
| 823 | EFIAPI\r |
| 824 | PciCf8AndThenOr32 (\r |
| 825 | IN UINTN Address,\r |
| 826 | IN UINT32 AndData,\r |
| 827 | IN UINT32 OrData\r |
| 828 | );\r |
| 829 | \r |
| 830 | /**\r |
| 831 | Reads a bit field of a PCI configuration register.\r |
| 832 | \r |
| 833 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r |
| 834 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 835 | returned.\r |
| 836 | \r |
| 837 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 838 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 839 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 840 | If StartBit is greater than 31, then ASSERT().\r |
| 841 | If EndBit is greater than 31, then ASSERT().\r |
| 842 | If EndBit is less than StartBit, then ASSERT().\r |
| 843 | \r |
| 844 | @param Address PCI configuration register to read.\r |
| 845 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 846 | Range 0..31.\r |
| 847 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 848 | Range 0..31.\r |
| 849 | \r |
| 850 | @return The value of the bit field read from the PCI configuration register.\r |
| 851 | \r |
| 852 | **/\r |
| 853 | UINT32\r |
| 854 | EFIAPI\r |
| 855 | PciCf8BitFieldRead32 (\r |
| 856 | IN UINTN Address,\r |
| 857 | IN UINTN StartBit,\r |
| 858 | IN UINTN EndBit\r |
| 859 | );\r |
| 860 | \r |
| 861 | /**\r |
| 862 | Writes a bit field to a PCI configuration register.\r |
| 863 | \r |
| 864 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 865 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 866 | destination PCI configuration register are preserved. The new value of the\r |
| 867 | 32-bit register is returned.\r |
| 868 | \r |
| 869 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 870 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 871 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 872 | If StartBit is greater than 31, then ASSERT().\r |
| 873 | If EndBit is greater than 31, then ASSERT().\r |
| 874 | If EndBit is less than StartBit, then ASSERT().\r |
| 875 | \r |
| 876 | @param Address PCI configuration register to write.\r |
| 877 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 878 | Range 0..31.\r |
| 879 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 880 | Range 0..31.\r |
| 881 | @param Value New value of the bit field.\r |
| 882 | \r |
| 883 | @return The value written back to the PCI configuration register.\r |
| 884 | \r |
| 885 | **/\r |
| 886 | UINT32\r |
| 887 | EFIAPI\r |
| 888 | PciCf8BitFieldWrite32 (\r |
| 889 | IN UINTN Address,\r |
| 890 | IN UINTN StartBit,\r |
| 891 | IN UINTN EndBit,\r |
| 892 | IN UINT32 Value\r |
| 893 | );\r |
| 894 | \r |
| 895 | /**\r |
| 896 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r |
| 897 | writes the result back to the bit field in the 32-bit port.\r |
| 898 | \r |
| 899 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 900 | bitwise inclusive OR between the read result and the value specified by\r |
| 901 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| 902 | specified by Address. The value written to the PCI configuration register is\r |
| 903 | returned. This function must guarantee that all PCI read and write operations\r |
| 904 | are serialized. Extra left bits in OrData are stripped.\r |
| 905 | \r |
| 906 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 907 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 908 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 909 | If StartBit is greater than 31, then ASSERT().\r |
| 910 | If EndBit is greater than 31, then ASSERT().\r |
| 911 | If EndBit is less than StartBit, then ASSERT().\r |
| 912 | \r |
| 913 | @param Address PCI configuration register to write.\r |
| 914 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 915 | Range 0..31.\r |
| 916 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 917 | Range 0..31.\r |
| 918 | @param OrData The value to OR with the PCI configuration register.\r |
| 919 | \r |
| 920 | @return The value written back to the PCI configuration register.\r |
| 921 | \r |
| 922 | **/\r |
| 923 | UINT32\r |
| 924 | EFIAPI\r |
| 925 | PciCf8BitFieldOr32 (\r |
| 926 | IN UINTN Address,\r |
| 927 | IN UINTN StartBit,\r |
| 928 | IN UINTN EndBit,\r |
| 929 | IN UINT32 OrData\r |
| 930 | );\r |
| 931 | \r |
| 932 | /**\r |
| 933 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r |
| 934 | AND, and writes the result back to the bit field in the 32-bit register.\r |
| 935 | \r |
| 936 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 937 | bitwise AND between the read result and the value specified by AndData, and\r |
| 938 | writes the result to the 32-bit PCI configuration register specified by\r |
| 939 | Address. The value written to the PCI configuration register is returned.\r |
| 940 | This function must guarantee that all PCI read and write operations are\r |
| 941 | serialized. Extra left bits in AndData are stripped.\r |
| 942 | \r |
| 943 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 944 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 945 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 946 | If StartBit is greater than 31, then ASSERT().\r |
| 947 | If EndBit is greater than 31, then ASSERT().\r |
| 948 | If EndBit is less than StartBit, then ASSERT().\r |
| 949 | \r |
| 950 | @param Address PCI configuration register to write.\r |
| 951 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 952 | Range 0..31.\r |
| 953 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 954 | Range 0..31.\r |
| 955 | @param AndData The value to AND with the PCI configuration register.\r |
| 956 | \r |
| 957 | @return The value written back to the PCI configuration register.\r |
| 958 | \r |
| 959 | **/\r |
| 960 | UINT32\r |
| 961 | EFIAPI\r |
| 962 | PciCf8BitFieldAnd32 (\r |
| 963 | IN UINTN Address,\r |
| 964 | IN UINTN StartBit,\r |
| 965 | IN UINTN EndBit,\r |
| 966 | IN UINT32 AndData\r |
| 967 | );\r |
| 968 | \r |
| 969 | /**\r |
| 970 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r |
| 971 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 972 | 32-bit port.\r |
| 973 | \r |
| 974 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 975 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 976 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
| 977 | configuration register specified by Address. The value written to the PCI\r |
| 978 | configuration register is returned. This function must guarantee that all PCI\r |
| 979 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 980 | OrData are stripped.\r |
| 981 | \r |
| 982 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 983 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 984 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 985 | If StartBit is greater than 31, then ASSERT().\r |
| 986 | If EndBit is greater than 31, then ASSERT().\r |
| 987 | If EndBit is less than StartBit, then ASSERT().\r |
| 988 | \r |
| 989 | @param Address PCI configuration register to write.\r |
| 990 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 991 | Range 0..31.\r |
| 992 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 993 | Range 0..31.\r |
| 994 | @param AndData The value to AND with the PCI configuration register.\r |
| 995 | @param OrData The value to OR with the result of the AND operation.\r |
| 996 | \r |
| 997 | @return The value written back to the PCI configuration register.\r |
| 998 | \r |
| 999 | **/\r |
| 1000 | UINT32\r |
| 1001 | EFIAPI\r |
| 1002 | PciCf8BitFieldAndThenOr32 (\r |
| 1003 | IN UINTN Address,\r |
| 1004 | IN UINTN StartBit,\r |
| 1005 | IN UINTN EndBit,\r |
| 1006 | IN UINT32 AndData,\r |
| 1007 | IN UINT32 OrData\r |
| 1008 | );\r |
| 1009 | \r |
| 1010 | /**\r |
| 1011 | Reads a range of PCI configuration registers into a caller supplied buffer.\r |
| 1012 | \r |
| 1013 | Reads the range of PCI configuration registers specified by StartAddress and\r |
| 1014 | Size into the buffer specified by Buffer. This function only allows the PCI\r |
| 1015 | configuration registers from a single PCI function to be read. Size is\r |
| 1016 | returned. When possible 32-bit PCI configuration read cycles are used to read\r |
| 1017 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r |
| 1018 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r |
| 1019 | end of the range.\r |
| 1020 | \r |
| 1021 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
| 1022 | If the register specified by StartAddress >= 0x100, then ASSERT().\r |
| 1023 | If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().\r |
| 1024 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| 1025 | \r |
| 1026 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r |
| 1027 | Function and Register.\r |
| 1028 | @param Size Size in bytes of the transfer.\r |
| 1029 | @param Buffer Pointer to a buffer receiving the data read.\r |
| 1030 | \r |
| 9199040c |
1031 | @return Size read from StartAddress.\r |
| fb3df220 |
1032 | \r |
| 1033 | **/\r |
| 1034 | UINTN\r |
| 1035 | EFIAPI\r |
| 1036 | PciCf8ReadBuffer (\r |
| 1037 | IN UINTN StartAddress,\r |
| 1038 | IN UINTN Size,\r |
| 1039 | OUT VOID *Buffer\r |
| 1040 | );\r |
| 1041 | \r |
| 1042 | /**\r |
| 1043 | Copies the data in a caller supplied buffer to a specified range of PCI\r |
| 1044 | configuration space.\r |
| 1045 | \r |
| 1046 | Writes the range of PCI configuration registers specified by StartAddress and\r |
| 1047 | Size from the buffer specified by Buffer. This function only allows the PCI\r |
| 1048 | configuration registers from a single PCI function to be written. Size is\r |
| 1049 | returned. When possible 32-bit PCI configuration write cycles are used to\r |
| 1050 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r |
| 1051 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r |
| 1052 | and the end of the range.\r |
| 1053 | \r |
| 1054 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
| 1055 | If the register specified by StartAddress >= 0x100, then ASSERT().\r |
| 1056 | If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().\r |
| 1057 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| 1058 | \r |
| 1059 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r |
| 1060 | Function and Register.\r |
| 1061 | @param Size Size in bytes of the transfer.\r |
| 1062 | @param Buffer Pointer to a buffer containing the data to write.\r |
| 1063 | \r |
| 9199040c |
1064 | @return Size written to StartAddress.\r |
| fb3df220 |
1065 | \r |
| 1066 | **/\r |
| 1067 | UINTN\r |
| 1068 | EFIAPI\r |
| 1069 | PciCf8WriteBuffer (\r |
| 1070 | IN UINTN StartAddress,\r |
| 1071 | IN UINTN Size,\r |
| 1072 | IN VOID *Buffer\r |
| 1073 | );\r |
| 1074 | \r |
| 1075 | #endif\r |
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