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1 | /** @file\r |
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2 | Provides services to access PCI Configuration Space using the MMIO PCI Express window.\r |
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3 | \r |
| 4 | This library is identical to the PCI Library, except the access method for performing PCI \r |
| 5 | configuration cycles must be though the 256 MB PCI Express MMIO window whose base address\r |
| 6 | is defined by PcdPciExpressBaseAddress.\r |
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7 | \r |
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8 | Copyright (c) 2006 - 2008, Intel Corporation<BR>\r |
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9 | All rights reserved. This program and the accompanying materials\r |
| 10 | are licensed and made available under the terms and conditions of the BSD License\r |
| 11 | which accompanies this distribution. The full text of the license may be found at\r |
| 12 | http://opensource.org/licenses/bsd-license.php\r |
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13 | \r |
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14 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 15 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
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16 | \r |
| fb3df220 |
17 | **/\r |
| 18 | \r |
| 19 | #ifndef __PCI_EXPRESS_LIB_H__\r |
| 20 | #define __PCI_EXPRESS_LIB_H__\r |
| 21 | \r |
| fb3df220 |
22 | /**\r |
| 23 | Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an\r |
| 24 | address that can be passed to the PCI Library functions.\r |
| 25 | \r |
| 26 | Computes an address that is compatible with the PCI Library functions. The\r |
| 27 | unused upper bits of Bus, Device, Function and Register are stripped prior to\r |
| 28 | the generation of the address.\r |
| 29 | \r |
| 30 | @param Bus PCI Bus number. Range 0..255.\r |
| 31 | @param Device PCI Device number. Range 0..31.\r |
| 32 | @param Function PCI Function number. Range 0..7.\r |
| 33 | @param Register PCI Register number. Range 0..4095.\r |
| 34 | \r |
| 35 | @return The encode PCI address.\r |
| 36 | \r |
| 37 | **/\r |
| 38 | #define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) \\r |
| 39 | (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r |
| 40 | \r |
| f926e538 |
41 | /**\r |
| 42 | Register a PCI device so PCI configuration registers may be accessed after \r |
| 43 | SetVirtualAddressMap().\r |
| 44 | \r |
| 45 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 46 | \r |
| 47 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 48 | Register.\r |
| 49 | \r |
| 50 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r |
| 51 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r |
| 52 | after ExitBootServices().\r |
| 53 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r |
| 54 | at runtime could not be mapped.\r |
| 55 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r |
| 56 | complete the registration.\r |
| 57 | \r |
| 58 | **/\r |
| 59 | RETURN_STATUS\r |
| 60 | EFIAPI\r |
| 61 | PciExpressRegisterForRuntimeAccess (\r |
| 62 | IN UINTN Address\r |
| 63 | );\r |
| 64 | \r |
| fb3df220 |
65 | /**\r |
| 66 | Reads an 8-bit PCI configuration register.\r |
| 67 | \r |
| 68 | Reads and returns the 8-bit PCI configuration register specified by Address.\r |
| 69 | This function must guarantee that all PCI read and write operations are\r |
| 70 | serialized.\r |
| 71 | \r |
| 72 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 73 | \r |
| 74 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 75 | Register.\r |
| 76 | \r |
| 77 | @return The read value from the PCI configuration register.\r |
| 78 | \r |
| 79 | **/\r |
| 80 | UINT8\r |
| 81 | EFIAPI\r |
| 82 | PciExpressRead8 (\r |
| 83 | IN UINTN Address\r |
| 84 | );\r |
| 85 | \r |
| 86 | /**\r |
| 87 | Writes an 8-bit PCI configuration register.\r |
| 88 | \r |
| 89 | Writes the 8-bit PCI configuration register specified by Address with the\r |
| 90 | value specified by Value. Value is returned. This function must guarantee\r |
| 91 | that all PCI read and write operations are serialized.\r |
| 92 | \r |
| 93 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 94 | \r |
| 95 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 96 | Register.\r |
| 97 | @param Value The value to write.\r |
| 98 | \r |
| 99 | @return The value written to the PCI configuration register.\r |
| 100 | \r |
| 101 | **/\r |
| 102 | UINT8\r |
| 103 | EFIAPI\r |
| 104 | PciExpressWrite8 (\r |
| 105 | IN UINTN Address,\r |
| 94646ec0 |
106 | IN UINT8 Value\r |
| fb3df220 |
107 | );\r |
| 108 | \r |
| 109 | /**\r |
| 110 | Performs a bitwise inclusive OR of an 8-bit PCI configuration register with\r |
| 111 | an 8-bit value.\r |
| 112 | \r |
| 113 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 114 | bitwise inclusive OR between the read result and the value specified by\r |
| 115 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| 116 | specified by Address. The value written to the PCI configuration register is\r |
| 117 | returned. This function must guarantee that all PCI read and write operations\r |
| 118 | are serialized.\r |
| 119 | \r |
| 120 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 121 | \r |
| 122 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 123 | Register.\r |
| 124 | @param OrData The value to OR with the PCI configuration register.\r |
| 125 | \r |
| 126 | @return The value written back to the PCI configuration register.\r |
| 127 | \r |
| 128 | **/\r |
| 129 | UINT8\r |
| 130 | EFIAPI\r |
| 131 | PciExpressOr8 (\r |
| 132 | IN UINTN Address,\r |
| 133 | IN UINT8 OrData\r |
| 134 | );\r |
| 135 | \r |
| 136 | /**\r |
| 137 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
| 138 | value.\r |
| 139 | \r |
| 140 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 141 | bitwise AND between the read result and the value specified by AndData, and\r |
| 142 | writes the result to the 8-bit PCI configuration register specified by\r |
| 143 | Address. The value written to the PCI configuration register is returned.\r |
| 144 | This function must guarantee that all PCI read and write operations are\r |
| 145 | serialized.\r |
| 146 | \r |
| 147 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 148 | \r |
| 149 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 150 | Register.\r |
| 151 | @param AndData The value to AND with the PCI configuration register.\r |
| 152 | \r |
| 153 | @return The value written back to the PCI configuration register.\r |
| 154 | \r |
| 155 | **/\r |
| 156 | UINT8\r |
| 157 | EFIAPI\r |
| 158 | PciExpressAnd8 (\r |
| 159 | IN UINTN Address,\r |
| 160 | IN UINT8 AndData\r |
| 161 | );\r |
| 162 | \r |
| 163 | /**\r |
| 164 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
| 165 | value, followed a bitwise inclusive OR with another 8-bit value.\r |
| 166 | \r |
| 167 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 168 | bitwise AND between the read result and the value specified by AndData,\r |
| 169 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 170 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
| 171 | configuration register specified by Address. The value written to the PCI\r |
| 172 | configuration register is returned. This function must guarantee that all PCI\r |
| 173 | read and write operations are serialized.\r |
| 174 | \r |
| 175 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 176 | \r |
| 177 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 178 | Register.\r |
| 179 | @param AndData The value to AND with the PCI configuration register.\r |
| 180 | @param OrData The value to OR with the result of the AND operation.\r |
| 181 | \r |
| 182 | @return The value written back to the PCI configuration register.\r |
| 183 | \r |
| 184 | **/\r |
| 185 | UINT8\r |
| 186 | EFIAPI\r |
| 187 | PciExpressAndThenOr8 (\r |
| 188 | IN UINTN Address,\r |
| 189 | IN UINT8 AndData,\r |
| 190 | IN UINT8 OrData\r |
| 191 | );\r |
| 192 | \r |
| 193 | /**\r |
| 194 | Reads a bit field of a PCI configuration register.\r |
| 195 | \r |
| 196 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r |
| 197 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 198 | returned.\r |
| 199 | \r |
| 200 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 201 | If StartBit is greater than 7, then ASSERT().\r |
| 202 | If EndBit is greater than 7, then ASSERT().\r |
| 203 | If EndBit is less than StartBit, then ASSERT().\r |
| 204 | \r |
| 205 | @param Address PCI configuration register to read.\r |
| 206 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 207 | Range 0..7.\r |
| 208 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 209 | Range 0..7.\r |
| 210 | \r |
| 211 | @return The value of the bit field read from the PCI configuration register.\r |
| 212 | \r |
| 213 | **/\r |
| 214 | UINT8\r |
| 215 | EFIAPI\r |
| 216 | PciExpressBitFieldRead8 (\r |
| 217 | IN UINTN Address,\r |
| 218 | IN UINTN StartBit,\r |
| 219 | IN UINTN EndBit\r |
| 220 | );\r |
| 221 | \r |
| 222 | /**\r |
| 223 | Writes a bit field to a PCI configuration register.\r |
| 224 | \r |
| 225 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 226 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 227 | destination PCI configuration register are preserved. The new value of the\r |
| 228 | 8-bit register is returned.\r |
| 229 | \r |
| 230 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 231 | If StartBit is greater than 7, then ASSERT().\r |
| 232 | If EndBit is greater than 7, then ASSERT().\r |
| 233 | If EndBit is less than StartBit, then ASSERT().\r |
| 234 | \r |
| 235 | @param Address PCI configuration register to write.\r |
| 236 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 237 | Range 0..7.\r |
| 238 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 239 | Range 0..7.\r |
| 240 | @param Value New value of the bit field.\r |
| 241 | \r |
| 242 | @return The value written back to the PCI configuration register.\r |
| 243 | \r |
| 244 | **/\r |
| 245 | UINT8\r |
| 246 | EFIAPI\r |
| 247 | PciExpressBitFieldWrite8 (\r |
| 248 | IN UINTN Address,\r |
| 249 | IN UINTN StartBit,\r |
| 250 | IN UINTN EndBit,\r |
| 251 | IN UINT8 Value\r |
| 252 | );\r |
| 253 | \r |
| 254 | /**\r |
| 255 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r |
| 256 | writes the result back to the bit field in the 8-bit port.\r |
| 257 | \r |
| 258 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 259 | bitwise inclusive OR between the read result and the value specified by\r |
| 260 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| 261 | specified by Address. The value written to the PCI configuration register is\r |
| 262 | returned. This function must guarantee that all PCI read and write operations\r |
| 263 | are serialized. Extra left bits in OrData are stripped.\r |
| 264 | \r |
| 265 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 266 | If StartBit is greater than 7, then ASSERT().\r |
| 267 | If EndBit is greater than 7, then ASSERT().\r |
| 268 | If EndBit is less than StartBit, then ASSERT().\r |
| 269 | \r |
| 270 | @param Address PCI configuration register to write.\r |
| 271 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 272 | Range 0..7.\r |
| 273 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 274 | Range 0..7.\r |
| 275 | @param OrData The value to OR with the PCI configuration register.\r |
| 276 | \r |
| 277 | @return The value written back to the PCI configuration register.\r |
| 278 | \r |
| 279 | **/\r |
| 280 | UINT8\r |
| 281 | EFIAPI\r |
| 282 | PciExpressBitFieldOr8 (\r |
| 283 | IN UINTN Address,\r |
| 284 | IN UINTN StartBit,\r |
| 285 | IN UINTN EndBit,\r |
| 286 | IN UINT8 OrData\r |
| 287 | );\r |
| 288 | \r |
| 289 | /**\r |
| 290 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r |
| 291 | AND, and writes the result back to the bit field in the 8-bit register.\r |
| 292 | \r |
| 293 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 294 | bitwise AND between the read result and the value specified by AndData, and\r |
| 295 | writes the result to the 8-bit PCI configuration register specified by\r |
| 296 | Address. The value written to the PCI configuration register is returned.\r |
| 297 | This function must guarantee that all PCI read and write operations are\r |
| 298 | serialized. Extra left bits in AndData are stripped.\r |
| 299 | \r |
| 300 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 301 | If StartBit is greater than 7, then ASSERT().\r |
| 302 | If EndBit is greater than 7, then ASSERT().\r |
| 303 | If EndBit is less than StartBit, then ASSERT().\r |
| 304 | \r |
| 305 | @param Address PCI configuration register to write.\r |
| 306 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 307 | Range 0..7.\r |
| 308 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 309 | Range 0..7.\r |
| 310 | @param AndData The value to AND with the PCI configuration register.\r |
| 311 | \r |
| 312 | @return The value written back to the PCI configuration register.\r |
| 313 | \r |
| 314 | **/\r |
| 315 | UINT8\r |
| 316 | EFIAPI\r |
| 317 | PciExpressBitFieldAnd8 (\r |
| 318 | IN UINTN Address,\r |
| 319 | IN UINTN StartBit,\r |
| 320 | IN UINTN EndBit,\r |
| 321 | IN UINT8 AndData\r |
| 322 | );\r |
| 323 | \r |
| 324 | /**\r |
| 325 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r |
| 326 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 327 | 8-bit port.\r |
| 328 | \r |
| 329 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 330 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 331 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
| 332 | configuration register specified by Address. The value written to the PCI\r |
| 333 | configuration register is returned. This function must guarantee that all PCI\r |
| 334 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 335 | OrData are stripped.\r |
| 336 | \r |
| 337 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 338 | If StartBit is greater than 7, then ASSERT().\r |
| 339 | If EndBit is greater than 7, then ASSERT().\r |
| 340 | If EndBit is less than StartBit, then ASSERT().\r |
| 341 | \r |
| 342 | @param Address PCI configuration register to write.\r |
| 343 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 344 | Range 0..7.\r |
| 345 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 346 | Range 0..7.\r |
| 347 | @param AndData The value to AND with the PCI configuration register.\r |
| 348 | @param OrData The value to OR with the result of the AND operation.\r |
| 349 | \r |
| 350 | @return The value written back to the PCI configuration register.\r |
| 351 | \r |
| 352 | **/\r |
| 353 | UINT8\r |
| 354 | EFIAPI\r |
| 355 | PciExpressBitFieldAndThenOr8 (\r |
| 356 | IN UINTN Address,\r |
| 357 | IN UINTN StartBit,\r |
| 358 | IN UINTN EndBit,\r |
| 359 | IN UINT8 AndData,\r |
| 360 | IN UINT8 OrData\r |
| 361 | );\r |
| 362 | \r |
| 363 | /**\r |
| 364 | Reads a 16-bit PCI configuration register.\r |
| 365 | \r |
| 366 | Reads and returns the 16-bit PCI configuration register specified by Address.\r |
| 367 | This function must guarantee that all PCI read and write operations are\r |
| 368 | serialized.\r |
| 369 | \r |
| 370 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 371 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 372 | \r |
| 373 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 374 | Register.\r |
| 375 | \r |
| 376 | @return The read value from the PCI configuration register.\r |
| 377 | \r |
| 378 | **/\r |
| 379 | UINT16\r |
| 380 | EFIAPI\r |
| 381 | PciExpressRead16 (\r |
| 382 | IN UINTN Address\r |
| 383 | );\r |
| 384 | \r |
| 385 | /**\r |
| 386 | Writes a 16-bit PCI configuration register.\r |
| 387 | \r |
| 388 | Writes the 16-bit PCI configuration register specified by Address with the\r |
| 389 | value specified by Value. Value is returned. This function must guarantee\r |
| 390 | that all PCI read and write operations are serialized.\r |
| 391 | \r |
| 392 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 393 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 394 | \r |
| 395 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 396 | Register.\r |
| 397 | @param Value The value to write.\r |
| 398 | \r |
| 399 | @return The value written to the PCI configuration register.\r |
| 400 | \r |
| 401 | **/\r |
| 402 | UINT16\r |
| 403 | EFIAPI\r |
| 404 | PciExpressWrite16 (\r |
| 405 | IN UINTN Address,\r |
| 94646ec0 |
406 | IN UINT16 Value\r |
| fb3df220 |
407 | );\r |
| 408 | \r |
| 409 | /**\r |
| 410 | Performs a bitwise inclusive OR of a 16-bit PCI configuration register with\r |
| 411 | a 16-bit value.\r |
| 412 | \r |
| 413 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 414 | bitwise inclusive OR between the read result and the value specified by\r |
| 415 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| 416 | specified by Address. The value written to the PCI configuration register is\r |
| 417 | returned. This function must guarantee that all PCI read and write operations\r |
| 418 | are serialized.\r |
| 419 | \r |
| 420 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 421 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 422 | \r |
| 423 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 424 | Register.\r |
| 425 | @param OrData The value to OR with the PCI configuration register.\r |
| 426 | \r |
| 427 | @return The value written back to the PCI configuration register.\r |
| 428 | \r |
| 429 | **/\r |
| 430 | UINT16\r |
| 431 | EFIAPI\r |
| 432 | PciExpressOr16 (\r |
| 433 | IN UINTN Address,\r |
| 434 | IN UINT16 OrData\r |
| 435 | );\r |
| 436 | \r |
| 437 | /**\r |
| 438 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
| 439 | value.\r |
| 440 | \r |
| 441 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 442 | bitwise AND between the read result and the value specified by AndData, and\r |
| 443 | writes the result to the 16-bit PCI configuration register specified by\r |
| 444 | Address. The value written to the PCI configuration register is returned.\r |
| 445 | This function must guarantee that all PCI read and write operations are\r |
| 446 | serialized.\r |
| 447 | \r |
| 448 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 449 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 450 | \r |
| 451 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 452 | Register.\r |
| 453 | @param AndData The value to AND with the PCI configuration register.\r |
| 454 | \r |
| 455 | @return The value written back to the PCI configuration register.\r |
| 456 | \r |
| 457 | **/\r |
| 458 | UINT16\r |
| 459 | EFIAPI\r |
| 460 | PciExpressAnd16 (\r |
| 461 | IN UINTN Address,\r |
| 462 | IN UINT16 AndData\r |
| 463 | );\r |
| 464 | \r |
| 465 | /**\r |
| 466 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
| 467 | value, followed a bitwise inclusive OR with another 16-bit value.\r |
| 468 | \r |
| 469 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 470 | bitwise AND between the read result and the value specified by AndData,\r |
| 471 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 472 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
| 473 | configuration register specified by Address. The value written to the PCI\r |
| 474 | configuration register is returned. This function must guarantee that all PCI\r |
| 475 | read and write operations are serialized.\r |
| 476 | \r |
| 477 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 478 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 479 | \r |
| 480 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 481 | Register.\r |
| 482 | @param AndData The value to AND with the PCI configuration register.\r |
| 483 | @param OrData The value to OR with the result of the AND operation.\r |
| 484 | \r |
| 485 | @return The value written back to the PCI configuration register.\r |
| 486 | \r |
| 487 | **/\r |
| 488 | UINT16\r |
| 489 | EFIAPI\r |
| 490 | PciExpressAndThenOr16 (\r |
| 491 | IN UINTN Address,\r |
| 492 | IN UINT16 AndData,\r |
| 493 | IN UINT16 OrData\r |
| 494 | );\r |
| 495 | \r |
| 496 | /**\r |
| 497 | Reads a bit field of a PCI configuration register.\r |
| 498 | \r |
| 499 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r |
| 500 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 501 | returned.\r |
| 502 | \r |
| 503 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 504 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 505 | If StartBit is greater than 15, then ASSERT().\r |
| 506 | If EndBit is greater than 15, then ASSERT().\r |
| 507 | If EndBit is less than StartBit, then ASSERT().\r |
| 508 | \r |
| 509 | @param Address PCI configuration register to read.\r |
| 510 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 511 | Range 0..15.\r |
| 512 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 513 | Range 0..15.\r |
| 514 | \r |
| 515 | @return The value of the bit field read from the PCI configuration register.\r |
| 516 | \r |
| 517 | **/\r |
| 518 | UINT16\r |
| 519 | EFIAPI\r |
| 520 | PciExpressBitFieldRead16 (\r |
| 521 | IN UINTN Address,\r |
| 522 | IN UINTN StartBit,\r |
| 523 | IN UINTN EndBit\r |
| 524 | );\r |
| 525 | \r |
| 526 | /**\r |
| 527 | Writes a bit field to a PCI configuration register.\r |
| 528 | \r |
| 529 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 530 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 531 | destination PCI configuration register are preserved. The new value of the\r |
| 532 | 16-bit register is returned.\r |
| 533 | \r |
| 534 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 535 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 536 | If StartBit is greater than 15, then ASSERT().\r |
| 537 | If EndBit is greater than 15, then ASSERT().\r |
| 538 | If EndBit is less than StartBit, then ASSERT().\r |
| 539 | \r |
| 540 | @param Address PCI configuration register to write.\r |
| 541 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 542 | Range 0..15.\r |
| 543 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 544 | Range 0..15.\r |
| 545 | @param Value New value of the bit field.\r |
| 546 | \r |
| 547 | @return The value written back to the PCI configuration register.\r |
| 548 | \r |
| 549 | **/\r |
| 550 | UINT16\r |
| 551 | EFIAPI\r |
| 552 | PciExpressBitFieldWrite16 (\r |
| 553 | IN UINTN Address,\r |
| 554 | IN UINTN StartBit,\r |
| 555 | IN UINTN EndBit,\r |
| 556 | IN UINT16 Value\r |
| 557 | );\r |
| 558 | \r |
| 559 | /**\r |
| 560 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r |
| 561 | writes the result back to the bit field in the 16-bit port.\r |
| 562 | \r |
| 563 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 564 | bitwise inclusive OR between the read result and the value specified by\r |
| 565 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| 566 | specified by Address. The value written to the PCI configuration register is\r |
| 567 | returned. This function must guarantee that all PCI read and write operations\r |
| 568 | are serialized. Extra left bits in OrData are stripped.\r |
| 569 | \r |
| 570 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 571 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 572 | If StartBit is greater than 15, then ASSERT().\r |
| 573 | If EndBit is greater than 15, then ASSERT().\r |
| 574 | If EndBit is less than StartBit, then ASSERT().\r |
| 575 | \r |
| 576 | @param Address PCI configuration register to write.\r |
| 577 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 578 | Range 0..15.\r |
| 579 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 580 | Range 0..15.\r |
| 581 | @param OrData The value to OR with the PCI configuration register.\r |
| 582 | \r |
| 583 | @return The value written back to the PCI configuration register.\r |
| 584 | \r |
| 585 | **/\r |
| 586 | UINT16\r |
| 587 | EFIAPI\r |
| 588 | PciExpressBitFieldOr16 (\r |
| 589 | IN UINTN Address,\r |
| 590 | IN UINTN StartBit,\r |
| 591 | IN UINTN EndBit,\r |
| 592 | IN UINT16 OrData\r |
| 593 | );\r |
| 594 | \r |
| 595 | /**\r |
| 596 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r |
| 597 | AND, and writes the result back to the bit field in the 16-bit register.\r |
| 598 | \r |
| 599 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 600 | bitwise AND between the read result and the value specified by AndData, and\r |
| 601 | writes the result to the 16-bit PCI configuration register specified by\r |
| 602 | Address. The value written to the PCI configuration register is returned.\r |
| 603 | This function must guarantee that all PCI read and write operations are\r |
| 604 | serialized. Extra left bits in AndData are stripped.\r |
| 605 | \r |
| 606 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 607 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 608 | If StartBit is greater than 15, then ASSERT().\r |
| 609 | If EndBit is greater than 15, then ASSERT().\r |
| 610 | If EndBit is less than StartBit, then ASSERT().\r |
| 611 | \r |
| 612 | @param Address PCI configuration register to write.\r |
| 613 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 614 | Range 0..15.\r |
| 615 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 616 | Range 0..15.\r |
| 617 | @param AndData The value to AND with the PCI configuration register.\r |
| 618 | \r |
| 619 | @return The value written back to the PCI configuration register.\r |
| 620 | \r |
| 621 | **/\r |
| 622 | UINT16\r |
| 623 | EFIAPI\r |
| 624 | PciExpressBitFieldAnd16 (\r |
| 625 | IN UINTN Address,\r |
| 626 | IN UINTN StartBit,\r |
| 627 | IN UINTN EndBit,\r |
| 628 | IN UINT16 AndData\r |
| 629 | );\r |
| 630 | \r |
| 631 | /**\r |
| 632 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r |
| 633 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 634 | 16-bit port.\r |
| 635 | \r |
| 636 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 637 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 638 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
| 639 | configuration register specified by Address. The value written to the PCI\r |
| 640 | configuration register is returned. This function must guarantee that all PCI\r |
| 641 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 642 | OrData are stripped.\r |
| 643 | \r |
| 644 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 645 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 646 | If StartBit is greater than 15, then ASSERT().\r |
| 647 | If EndBit is greater than 15, then ASSERT().\r |
| 648 | If EndBit is less than StartBit, then ASSERT().\r |
| 649 | \r |
| 650 | @param Address PCI configuration register to write.\r |
| 651 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 652 | Range 0..15.\r |
| 653 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 654 | Range 0..15.\r |
| 655 | @param AndData The value to AND with the PCI configuration register.\r |
| 656 | @param OrData The value to OR with the result of the AND operation.\r |
| 657 | \r |
| 658 | @return The value written back to the PCI configuration register.\r |
| 659 | \r |
| 660 | **/\r |
| 661 | UINT16\r |
| 662 | EFIAPI\r |
| 663 | PciExpressBitFieldAndThenOr16 (\r |
| 664 | IN UINTN Address,\r |
| 665 | IN UINTN StartBit,\r |
| 666 | IN UINTN EndBit,\r |
| 667 | IN UINT16 AndData,\r |
| 668 | IN UINT16 OrData\r |
| 669 | );\r |
| 670 | \r |
| 671 | /**\r |
| 672 | Reads a 32-bit PCI configuration register.\r |
| 673 | \r |
| 674 | Reads and returns the 32-bit PCI configuration register specified by Address.\r |
| 675 | This function must guarantee that all PCI read and write operations are\r |
| 676 | serialized.\r |
| 677 | \r |
| 678 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 679 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 680 | \r |
| 681 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 682 | Register.\r |
| 683 | \r |
| 684 | @return The read value from the PCI configuration register.\r |
| 685 | \r |
| 686 | **/\r |
| 687 | UINT32\r |
| 688 | EFIAPI\r |
| 689 | PciExpressRead32 (\r |
| 690 | IN UINTN Address\r |
| 691 | );\r |
| 692 | \r |
| 693 | /**\r |
| 694 | Writes a 32-bit PCI configuration register.\r |
| 695 | \r |
| 696 | Writes the 32-bit PCI configuration register specified by Address with the\r |
| 697 | value specified by Value. Value is returned. This function must guarantee\r |
| 698 | that all PCI read and write operations are serialized.\r |
| 699 | \r |
| 700 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 701 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 702 | \r |
| 703 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 704 | Register.\r |
| 705 | @param Value The value to write.\r |
| 706 | \r |
| 707 | @return The value written to the PCI configuration register.\r |
| 708 | \r |
| 709 | **/\r |
| 710 | UINT32\r |
| 711 | EFIAPI\r |
| 712 | PciExpressWrite32 (\r |
| 713 | IN UINTN Address,\r |
| 94646ec0 |
714 | IN UINT32 Value\r |
| fb3df220 |
715 | );\r |
| 716 | \r |
| 717 | /**\r |
| 718 | Performs a bitwise inclusive OR of a 32-bit PCI configuration register with\r |
| 719 | a 32-bit value.\r |
| 720 | \r |
| 721 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 722 | bitwise inclusive OR between the read result and the value specified by\r |
| 723 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| 724 | specified by Address. The value written to the PCI configuration register is\r |
| 725 | returned. This function must guarantee that all PCI read and write operations\r |
| 726 | are serialized.\r |
| 727 | \r |
| 728 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 729 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 730 | \r |
| 731 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 732 | Register.\r |
| 733 | @param OrData The value to OR with the PCI configuration register.\r |
| 734 | \r |
| 735 | @return The value written back to the PCI configuration register.\r |
| 736 | \r |
| 737 | **/\r |
| 738 | UINT32\r |
| 739 | EFIAPI\r |
| 740 | PciExpressOr32 (\r |
| 741 | IN UINTN Address,\r |
| 742 | IN UINT32 OrData\r |
| 743 | );\r |
| 744 | \r |
| 745 | /**\r |
| 746 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
| 747 | value.\r |
| 748 | \r |
| 749 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 750 | bitwise AND between the read result and the value specified by AndData, and\r |
| 751 | writes the result to the 32-bit PCI configuration register specified by\r |
| 752 | Address. The value written to the PCI configuration register is returned.\r |
| 753 | This function must guarantee that all PCI read and write operations are\r |
| 754 | serialized.\r |
| 755 | \r |
| 756 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 757 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 758 | \r |
| 759 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 760 | Register.\r |
| 761 | @param AndData The value to AND with the PCI configuration register.\r |
| 762 | \r |
| 763 | @return The value written back to the PCI configuration register.\r |
| 764 | \r |
| 765 | **/\r |
| 766 | UINT32\r |
| 767 | EFIAPI\r |
| 768 | PciExpressAnd32 (\r |
| 769 | IN UINTN Address,\r |
| 770 | IN UINT32 AndData\r |
| 771 | );\r |
| 772 | \r |
| 773 | /**\r |
| 774 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
| 775 | value, followed a bitwise inclusive OR with another 32-bit value.\r |
| 776 | \r |
| 777 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 778 | bitwise AND between the read result and the value specified by AndData,\r |
| 779 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 780 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
| 781 | configuration register specified by Address. The value written to the PCI\r |
| 782 | configuration register is returned. This function must guarantee that all PCI\r |
| 783 | read and write operations are serialized.\r |
| 784 | \r |
| 785 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 786 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 787 | \r |
| 788 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 789 | Register.\r |
| 790 | @param AndData The value to AND with the PCI configuration register.\r |
| 791 | @param OrData The value to OR with the result of the AND operation.\r |
| 792 | \r |
| 793 | @return The value written back to the PCI configuration register.\r |
| 794 | \r |
| 795 | **/\r |
| 796 | UINT32\r |
| 797 | EFIAPI\r |
| 798 | PciExpressAndThenOr32 (\r |
| 799 | IN UINTN Address,\r |
| 800 | IN UINT32 AndData,\r |
| 801 | IN UINT32 OrData\r |
| 802 | );\r |
| 803 | \r |
| 804 | /**\r |
| 805 | Reads a bit field of a PCI configuration register.\r |
| 806 | \r |
| 807 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r |
| 808 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 809 | returned.\r |
| 810 | \r |
| 811 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 812 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 813 | If StartBit is greater than 31, then ASSERT().\r |
| 814 | If EndBit is greater than 31, then ASSERT().\r |
| 815 | If EndBit is less than StartBit, then ASSERT().\r |
| 816 | \r |
| 817 | @param Address PCI configuration register to read.\r |
| 818 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 819 | Range 0..31.\r |
| 820 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 821 | Range 0..31.\r |
| 822 | \r |
| 823 | @return The value of the bit field read from the PCI configuration register.\r |
| 824 | \r |
| 825 | **/\r |
| 826 | UINT32\r |
| 827 | EFIAPI\r |
| 828 | PciExpressBitFieldRead32 (\r |
| 829 | IN UINTN Address,\r |
| 830 | IN UINTN StartBit,\r |
| 831 | IN UINTN EndBit\r |
| 832 | );\r |
| 833 | \r |
| 834 | /**\r |
| 835 | Writes a bit field to a PCI configuration register.\r |
| 836 | \r |
| 837 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 838 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 839 | destination PCI configuration register are preserved. The new value of the\r |
| 840 | 32-bit register is returned.\r |
| 841 | \r |
| 842 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 843 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 844 | If StartBit is greater than 31, then ASSERT().\r |
| 845 | If EndBit is greater than 31, then ASSERT().\r |
| 846 | If EndBit is less than StartBit, then ASSERT().\r |
| 847 | \r |
| 848 | @param Address PCI configuration register to write.\r |
| 849 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 850 | Range 0..31.\r |
| 851 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 852 | Range 0..31.\r |
| 853 | @param Value New value of the bit field.\r |
| 854 | \r |
| 855 | @return The value written back to the PCI configuration register.\r |
| 856 | \r |
| 857 | **/\r |
| 858 | UINT32\r |
| 859 | EFIAPI\r |
| 860 | PciExpressBitFieldWrite32 (\r |
| 861 | IN UINTN Address,\r |
| 862 | IN UINTN StartBit,\r |
| 863 | IN UINTN EndBit,\r |
| 864 | IN UINT32 Value\r |
| 865 | );\r |
| 866 | \r |
| 867 | /**\r |
| 868 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r |
| 869 | writes the result back to the bit field in the 32-bit port.\r |
| 870 | \r |
| 871 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 872 | bitwise inclusive OR between the read result and the value specified by\r |
| 873 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| 874 | specified by Address. The value written to the PCI configuration register is\r |
| 875 | returned. This function must guarantee that all PCI read and write operations\r |
| 876 | are serialized. Extra left bits in OrData are stripped.\r |
| 877 | \r |
| 878 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 879 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 880 | If StartBit is greater than 31, then ASSERT().\r |
| 881 | If EndBit is greater than 31, then ASSERT().\r |
| 882 | If EndBit is less than StartBit, then ASSERT().\r |
| 883 | \r |
| 884 | @param Address PCI configuration register to write.\r |
| 885 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 886 | Range 0..31.\r |
| 887 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 888 | Range 0..31.\r |
| 889 | @param OrData The value to OR with the PCI configuration register.\r |
| 890 | \r |
| 891 | @return The value written back to the PCI configuration register.\r |
| 892 | \r |
| 893 | **/\r |
| 894 | UINT32\r |
| 895 | EFIAPI\r |
| 896 | PciExpressBitFieldOr32 (\r |
| 897 | IN UINTN Address,\r |
| 898 | IN UINTN StartBit,\r |
| 899 | IN UINTN EndBit,\r |
| 900 | IN UINT32 OrData\r |
| 901 | );\r |
| 902 | \r |
| 903 | /**\r |
| 904 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r |
| 905 | AND, and writes the result back to the bit field in the 32-bit register.\r |
| 906 | \r |
| 907 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 908 | bitwise AND between the read result and the value specified by AndData, and\r |
| 909 | writes the result to the 32-bit PCI configuration register specified by\r |
| 910 | Address. The value written to the PCI configuration register is returned.\r |
| 911 | This function must guarantee that all PCI read and write operations are\r |
| 912 | serialized. Extra left bits in AndData are stripped.\r |
| 913 | \r |
| 914 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 915 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 916 | If StartBit is greater than 31, then ASSERT().\r |
| 917 | If EndBit is greater than 31, then ASSERT().\r |
| 918 | If EndBit is less than StartBit, then ASSERT().\r |
| 919 | \r |
| 920 | @param Address PCI configuration register to write.\r |
| 921 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 922 | Range 0..31.\r |
| 923 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 924 | Range 0..31.\r |
| 925 | @param AndData The value to AND with the PCI configuration register.\r |
| 926 | \r |
| 927 | @return The value written back to the PCI configuration register.\r |
| 928 | \r |
| 929 | **/\r |
| 930 | UINT32\r |
| 931 | EFIAPI\r |
| 932 | PciExpressBitFieldAnd32 (\r |
| 933 | IN UINTN Address,\r |
| 934 | IN UINTN StartBit,\r |
| 935 | IN UINTN EndBit,\r |
| 936 | IN UINT32 AndData\r |
| 937 | );\r |
| 938 | \r |
| 939 | /**\r |
| 940 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r |
| 941 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 942 | 32-bit port.\r |
| 943 | \r |
| 944 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 945 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 946 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
| 947 | configuration register specified by Address. The value written to the PCI\r |
| 948 | configuration register is returned. This function must guarantee that all PCI\r |
| 949 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 950 | OrData are stripped.\r |
| 951 | \r |
| 952 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 953 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 954 | If StartBit is greater than 31, then ASSERT().\r |
| 955 | If EndBit is greater than 31, then ASSERT().\r |
| 956 | If EndBit is less than StartBit, then ASSERT().\r |
| 957 | \r |
| 958 | @param Address PCI configuration register to write.\r |
| 959 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 960 | Range 0..31.\r |
| 961 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 962 | Range 0..31.\r |
| 963 | @param AndData The value to AND with the PCI configuration register.\r |
| 964 | @param OrData The value to OR with the result of the AND operation.\r |
| 965 | \r |
| 966 | @return The value written back to the PCI configuration register.\r |
| 967 | \r |
| 968 | **/\r |
| 969 | UINT32\r |
| 970 | EFIAPI\r |
| 971 | PciExpressBitFieldAndThenOr32 (\r |
| 972 | IN UINTN Address,\r |
| 973 | IN UINTN StartBit,\r |
| 974 | IN UINTN EndBit,\r |
| 975 | IN UINT32 AndData,\r |
| 976 | IN UINT32 OrData\r |
| 977 | );\r |
| 978 | \r |
| 979 | /**\r |
| 980 | Reads a range of PCI configuration registers into a caller supplied buffer.\r |
| 981 | \r |
| 982 | Reads the range of PCI configuration registers specified by StartAddress and\r |
| 983 | Size into the buffer specified by Buffer. This function only allows the PCI\r |
| 984 | configuration registers from a single PCI function to be read. Size is\r |
| 985 | returned. When possible 32-bit PCI configuration read cycles are used to read\r |
| 986 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r |
| 987 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r |
| 988 | end of the range.\r |
| 989 | \r |
| 990 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
| 991 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
| 992 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| 993 | \r |
| 994 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r |
| 995 | Function and Register.\r |
| 996 | @param Size Size in bytes of the transfer.\r |
| 997 | @param Buffer Pointer to a buffer receiving the data read.\r |
| 998 | \r |
| badcbfb2 |
999 | @return Size read data from StartAddress.\r |
| fb3df220 |
1000 | \r |
| 1001 | **/\r |
| 1002 | UINTN\r |
| 1003 | EFIAPI\r |
| 1004 | PciExpressReadBuffer (\r |
| 1005 | IN UINTN StartAddress,\r |
| 1006 | IN UINTN Size,\r |
| 1007 | OUT VOID *Buffer\r |
| 1008 | );\r |
| 1009 | \r |
| 1010 | /**\r |
| 1011 | Copies the data in a caller supplied buffer to a specified range of PCI\r |
| 1012 | configuration space.\r |
| 1013 | \r |
| 1014 | Writes the range of PCI configuration registers specified by StartAddress and\r |
| 1015 | Size from the buffer specified by Buffer. This function only allows the PCI\r |
| 1016 | configuration registers from a single PCI function to be written. Size is\r |
| 1017 | returned. When possible 32-bit PCI configuration write cycles are used to\r |
| 1018 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r |
| 1019 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r |
| 1020 | and the end of the range.\r |
| 1021 | \r |
| 1022 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
| 1023 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
| 1024 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| 1025 | \r |
| 1026 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r |
| 1027 | Function and Register.\r |
| 1028 | @param Size Size in bytes of the transfer.\r |
| 1029 | @param Buffer Pointer to a buffer containing the data to write.\r |
| 1030 | \r |
| 9199040c |
1031 | @return Size written to StartAddress.\r |
| fb3df220 |
1032 | \r |
| 1033 | **/\r |
| 1034 | UINTN\r |
| 1035 | EFIAPI\r |
| 1036 | PciExpressWriteBuffer (\r |
| 1037 | IN UINTN StartAddress,\r |
| 1038 | IN UINTN Size,\r |
| 1039 | IN VOID *Buffer\r |
| 1040 | );\r |
| 1041 | \r |
| 1042 | #endif\r |
projects / mirror_edk2.git / blame