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fb3df220 | 1 | /** @file\r |
50a64e5b | 2 | Provides services to access PCI Configuration Space.\r |
badcbfb2 | 3 | \r |
4 | These functions perform PCI configuration cycles using the default PCI configuration \r | |
5 | access method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, \r | |
6 | or it may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some \r | |
7 | alternate access method. Modules will typically use the PCI Library for its PCI configuration \r | |
8 | accesses. However, if a module requires a mix of PCI access methods, the PCI CF8 Library or \r | |
9 | PCI Express Library may be used in conjunction with the PCI Library. The functionality of \r | |
10 | these three libraries is identical. The PCI CF8 Library and PCI Express Library simply use \r | |
11 | explicit access methods.\r | |
fb3df220 | 12 | \r |
50a64e5b | 13 | Copyright (c) 2006 - 2008, Intel Corporation\r |
14 | All rights reserved. This program and the accompanying materials\r | |
15 | are licensed and made available under the terms and conditions of the BSD License\r | |
16 | which accompanies this distribution. The full text of the license may be found at\r | |
17 | http://opensource.org/licenses/bsd-license.php\r | |
fb3df220 | 18 | \r |
50a64e5b | 19 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
20 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
fb3df220 | 21 | \r |
fb3df220 | 22 | **/\r |
23 | \r | |
24 | #ifndef __PCI_LIB_H__\r | |
25 | #define __PCI_LIB_H__\r | |
26 | \r | |
27 | /**\r | |
28 | Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an\r | |
29 | address that can be passed to the PCI Library functions.\r | |
30 | \r | |
31 | @param Bus PCI Bus number. Range 0..255.\r | |
32 | @param Device PCI Device number. Range 0..31.\r | |
33 | @param Function PCI Function number. Range 0..7.\r | |
34 | @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095\r | |
35 | for PCI Express.\r | |
36 | \r | |
37 | @return The encoded PCI address.\r | |
38 | \r | |
39 | **/\r | |
40 | #define PCI_LIB_ADDRESS(Bus,Device,Function,Offset) \\r | |
41 | (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r | |
42 | \r | |
43 | /**\r | |
44 | Reads an 8-bit PCI configuration register.\r | |
45 | \r | |
46 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
47 | This function must guarantee that all PCI read and write operations are\r | |
48 | serialized.\r | |
49 | \r | |
50 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
51 | \r | |
52 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
53 | Register.\r | |
54 | \r | |
55 | @return The read value from the PCI configuration register.\r | |
56 | \r | |
57 | **/\r | |
58 | UINT8\r | |
59 | EFIAPI\r | |
60 | PciRead8 (\r | |
61 | IN UINTN Address\r | |
62 | );\r | |
63 | \r | |
64 | /**\r | |
65 | Writes an 8-bit PCI configuration register.\r | |
66 | \r | |
67 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
68 | value specified by Value. Value is returned. This function must guarantee\r | |
69 | that all PCI read and write operations are serialized.\r | |
70 | \r | |
71 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
72 | \r | |
73 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
74 | Register.\r | |
75 | @param Value The value to write.\r | |
76 | \r | |
77 | @return The value written to the PCI configuration register.\r | |
78 | \r | |
79 | **/\r | |
80 | UINT8\r | |
81 | EFIAPI\r | |
82 | PciWrite8 (\r | |
83 | IN UINTN Address,\r | |
94646ec0 | 84 | IN UINT8 Value\r |
fb3df220 | 85 | );\r |
86 | \r | |
87 | /**\r | |
88 | Performs a bitwise inclusive OR of an 8-bit PCI configuration register with\r | |
89 | an 8-bit value.\r | |
90 | \r | |
91 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
92 | bitwise inclusive OR between the read result and the value specified by\r | |
93 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
94 | specified by Address. The value written to the PCI configuration register is\r | |
95 | returned. This function must guarantee that all PCI read and write operations\r | |
96 | are serialized.\r | |
97 | \r | |
98 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
99 | \r | |
100 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
101 | Register.\r | |
102 | @param OrData The value to OR with the PCI configuration register.\r | |
103 | \r | |
104 | @return The value written back to the PCI configuration register.\r | |
105 | \r | |
106 | **/\r | |
107 | UINT8\r | |
108 | EFIAPI\r | |
109 | PciOr8 (\r | |
110 | IN UINTN Address,\r | |
111 | IN UINT8 OrData\r | |
112 | );\r | |
113 | \r | |
114 | /**\r | |
115 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
116 | value.\r | |
117 | \r | |
118 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
119 | bitwise AND between the read result and the value specified by AndData, and\r | |
120 | writes the result to the 8-bit PCI configuration register specified by\r | |
121 | Address. The value written to the PCI configuration register is returned.\r | |
122 | This function must guarantee that all PCI read and write operations are\r | |
123 | serialized.\r | |
124 | \r | |
125 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
126 | \r | |
127 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
128 | Register.\r | |
129 | @param AndData The value to AND with the PCI configuration register.\r | |
130 | \r | |
131 | @return The value written back to the PCI configuration register.\r | |
132 | \r | |
133 | **/\r | |
134 | UINT8\r | |
135 | EFIAPI\r | |
136 | PciAnd8 (\r | |
137 | IN UINTN Address,\r | |
138 | IN UINT8 AndData\r | |
139 | );\r | |
140 | \r | |
141 | /**\r | |
142 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
143 | value, followed a bitwise inclusive OR with another 8-bit value.\r | |
144 | \r | |
145 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
146 | bitwise AND between the read result and the value specified by AndData,\r | |
147 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
148 | the value specified by OrData, and writes the result to the 8-bit PCI\r | |
149 | configuration register specified by Address. The value written to the PCI\r | |
150 | configuration register is returned. This function must guarantee that all PCI\r | |
151 | read and write operations are serialized.\r | |
152 | \r | |
153 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
154 | \r | |
155 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
156 | Register.\r | |
157 | @param AndData The value to AND with the PCI configuration register.\r | |
158 | @param OrData The value to OR with the result of the AND operation.\r | |
159 | \r | |
160 | @return The value written back to the PCI configuration register.\r | |
161 | \r | |
162 | **/\r | |
163 | UINT8\r | |
164 | EFIAPI\r | |
165 | PciAndThenOr8 (\r | |
166 | IN UINTN Address,\r | |
167 | IN UINT8 AndData,\r | |
168 | IN UINT8 OrData\r | |
169 | );\r | |
170 | \r | |
171 | /**\r | |
172 | Reads a bit field of a PCI configuration register.\r | |
173 | \r | |
174 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
175 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
176 | returned.\r | |
177 | \r | |
178 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
179 | If StartBit is greater than 7, then ASSERT().\r | |
180 | If EndBit is greater than 7, then ASSERT().\r | |
181 | If EndBit is less than StartBit, then ASSERT().\r | |
182 | \r | |
183 | @param Address PCI configuration register to read.\r | |
184 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
185 | Range 0..7.\r | |
186 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
187 | Range 0..7.\r | |
188 | \r | |
189 | @return The value of the bit field read from the PCI configuration register.\r | |
190 | \r | |
191 | **/\r | |
192 | UINT8\r | |
193 | EFIAPI\r | |
194 | PciBitFieldRead8 (\r | |
195 | IN UINTN Address,\r | |
196 | IN UINTN StartBit,\r | |
197 | IN UINTN EndBit\r | |
198 | );\r | |
199 | \r | |
200 | /**\r | |
201 | Writes a bit field to a PCI configuration register.\r | |
202 | \r | |
203 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
204 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
205 | destination PCI configuration register are preserved. The new value of the\r | |
206 | 8-bit register is returned.\r | |
207 | \r | |
208 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
209 | If StartBit is greater than 7, then ASSERT().\r | |
210 | If EndBit is greater than 7, then ASSERT().\r | |
211 | If EndBit is less than StartBit, then ASSERT().\r | |
212 | \r | |
213 | @param Address PCI configuration register to write.\r | |
214 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
215 | Range 0..7.\r | |
216 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
217 | Range 0..7.\r | |
218 | @param Value New value of the bit field.\r | |
219 | \r | |
220 | @return The value written back to the PCI configuration register.\r | |
221 | \r | |
222 | **/\r | |
223 | UINT8\r | |
224 | EFIAPI\r | |
225 | PciBitFieldWrite8 (\r | |
226 | IN UINTN Address,\r | |
227 | IN UINTN StartBit,\r | |
228 | IN UINTN EndBit,\r | |
229 | IN UINT8 Value\r | |
230 | );\r | |
231 | \r | |
232 | /**\r | |
233 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
234 | writes the result back to the bit field in the 8-bit port.\r | |
235 | \r | |
236 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
237 | bitwise inclusive OR between the read result and the value specified by\r | |
238 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
239 | specified by Address. The value written to the PCI configuration register is\r | |
240 | returned. This function must guarantee that all PCI read and write operations\r | |
241 | are serialized. Extra left bits in OrData are stripped.\r | |
242 | \r | |
243 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
244 | If StartBit is greater than 7, then ASSERT().\r | |
245 | If EndBit is greater than 7, then ASSERT().\r | |
246 | If EndBit is less than StartBit, then ASSERT().\r | |
247 | \r | |
248 | @param Address PCI configuration register to write.\r | |
249 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
250 | Range 0..7.\r | |
251 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
252 | Range 0..7.\r | |
253 | @param OrData The value to OR with the PCI configuration register.\r | |
254 | \r | |
255 | @return The value written back to the PCI configuration register.\r | |
256 | \r | |
257 | **/\r | |
258 | UINT8\r | |
259 | EFIAPI\r | |
260 | PciBitFieldOr8 (\r | |
261 | IN UINTN Address,\r | |
262 | IN UINTN StartBit,\r | |
263 | IN UINTN EndBit,\r | |
264 | IN UINT8 OrData\r | |
265 | );\r | |
266 | \r | |
267 | /**\r | |
268 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
269 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
270 | \r | |
271 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
272 | bitwise AND between the read result and the value specified by AndData, and\r | |
273 | writes the result to the 8-bit PCI configuration register specified by\r | |
274 | Address. The value written to the PCI configuration register is returned.\r | |
275 | This function must guarantee that all PCI read and write operations are\r | |
276 | serialized. Extra left bits in AndData are stripped.\r | |
277 | \r | |
278 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
279 | If StartBit is greater than 7, then ASSERT().\r | |
280 | If EndBit is greater than 7, then ASSERT().\r | |
281 | If EndBit is less than StartBit, then ASSERT().\r | |
282 | \r | |
283 | @param Address PCI configuration register to write.\r | |
284 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
285 | Range 0..7.\r | |
286 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
287 | Range 0..7.\r | |
288 | @param AndData The value to AND with the PCI configuration register.\r | |
289 | \r | |
290 | @return The value written back to the PCI configuration register.\r | |
291 | \r | |
292 | **/\r | |
293 | UINT8\r | |
294 | EFIAPI\r | |
295 | PciBitFieldAnd8 (\r | |
296 | IN UINTN Address,\r | |
297 | IN UINTN StartBit,\r | |
298 | IN UINTN EndBit,\r | |
299 | IN UINT8 AndData\r | |
300 | );\r | |
301 | \r | |
302 | /**\r | |
303 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
304 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
305 | 8-bit port.\r | |
306 | \r | |
307 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
308 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
309 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
310 | configuration register specified by Address. The value written to the PCI\r | |
311 | configuration register is returned. This function must guarantee that all PCI\r | |
312 | read and write operations are serialized. Extra left bits in both AndData and\r | |
313 | OrData are stripped.\r | |
314 | \r | |
315 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
316 | If StartBit is greater than 7, then ASSERT().\r | |
317 | If EndBit is greater than 7, then ASSERT().\r | |
318 | If EndBit is less than StartBit, then ASSERT().\r | |
319 | \r | |
320 | @param Address PCI configuration register to write.\r | |
321 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
322 | Range 0..7.\r | |
323 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
324 | Range 0..7.\r | |
325 | @param AndData The value to AND with the PCI configuration register.\r | |
326 | @param OrData The value to OR with the result of the AND operation.\r | |
327 | \r | |
328 | @return The value written back to the PCI configuration register.\r | |
329 | \r | |
330 | **/\r | |
331 | UINT8\r | |
332 | EFIAPI\r | |
333 | PciBitFieldAndThenOr8 (\r | |
334 | IN UINTN Address,\r | |
335 | IN UINTN StartBit,\r | |
336 | IN UINTN EndBit,\r | |
337 | IN UINT8 AndData,\r | |
338 | IN UINT8 OrData\r | |
339 | );\r | |
340 | \r | |
341 | /**\r | |
342 | Reads a 16-bit PCI configuration register.\r | |
343 | \r | |
344 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
345 | This function must guarantee that all PCI read and write operations are\r | |
346 | serialized.\r | |
347 | \r | |
348 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
349 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
350 | \r | |
351 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
352 | Register.\r | |
353 | \r | |
354 | @return The read value from the PCI configuration register.\r | |
355 | \r | |
356 | **/\r | |
357 | UINT16\r | |
358 | EFIAPI\r | |
359 | PciRead16 (\r | |
360 | IN UINTN Address\r | |
361 | );\r | |
362 | \r | |
363 | /**\r | |
364 | Writes a 16-bit PCI configuration register.\r | |
365 | \r | |
366 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
367 | value specified by Value. Value is returned. This function must guarantee\r | |
368 | that all PCI read and write operations are serialized.\r | |
369 | \r | |
370 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
371 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
372 | \r | |
373 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
374 | Register.\r | |
375 | @param Value The value to write.\r | |
376 | \r | |
377 | @return The value written to the PCI configuration register.\r | |
378 | \r | |
379 | **/\r | |
380 | UINT16\r | |
381 | EFIAPI\r | |
382 | PciWrite16 (\r | |
383 | IN UINTN Address,\r | |
94646ec0 | 384 | IN UINT16 Value\r |
fb3df220 | 385 | );\r |
386 | \r | |
387 | /**\r | |
388 | Performs a bitwise inclusive OR of a 16-bit PCI configuration register with\r | |
389 | a 16-bit value.\r | |
390 | \r | |
391 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
392 | bitwise inclusive OR between the read result and the value specified by\r | |
393 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
394 | specified by Address. The value written to the PCI configuration register is\r | |
395 | returned. This function must guarantee that all PCI read and write operations\r | |
396 | are serialized.\r | |
397 | \r | |
398 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
399 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
400 | \r | |
401 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
402 | Register.\r | |
403 | @param OrData The value to OR with the PCI configuration register.\r | |
404 | \r | |
405 | @return The value written back to the PCI configuration register.\r | |
406 | \r | |
407 | **/\r | |
408 | UINT16\r | |
409 | EFIAPI\r | |
410 | PciOr16 (\r | |
411 | IN UINTN Address,\r | |
412 | IN UINT16 OrData\r | |
413 | );\r | |
414 | \r | |
415 | /**\r | |
416 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
417 | value.\r | |
418 | \r | |
419 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
420 | bitwise AND between the read result and the value specified by AndData, and\r | |
421 | writes the result to the 16-bit PCI configuration register specified by\r | |
422 | Address. The value written to the PCI configuration register is returned.\r | |
423 | This function must guarantee that all PCI read and write operations are\r | |
424 | serialized.\r | |
425 | \r | |
426 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
427 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
428 | \r | |
429 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
430 | Register.\r | |
431 | @param AndData The value to AND with the PCI configuration register.\r | |
432 | \r | |
433 | @return The value written back to the PCI configuration register.\r | |
434 | \r | |
435 | **/\r | |
436 | UINT16\r | |
437 | EFIAPI\r | |
438 | PciAnd16 (\r | |
439 | IN UINTN Address,\r | |
440 | IN UINT16 AndData\r | |
441 | );\r | |
442 | \r | |
443 | /**\r | |
444 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
445 | value, followed a bitwise inclusive OR with another 16-bit value.\r | |
446 | \r | |
447 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
448 | bitwise AND between the read result and the value specified by AndData,\r | |
449 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
450 | the value specified by OrData, and writes the result to the 16-bit PCI\r | |
451 | configuration register specified by Address. The value written to the PCI\r | |
452 | configuration register is returned. This function must guarantee that all PCI\r | |
453 | read and write operations are serialized.\r | |
454 | \r | |
455 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
456 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
457 | \r | |
458 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
459 | Register.\r | |
460 | @param AndData The value to AND with the PCI configuration register.\r | |
461 | @param OrData The value to OR with the result of the AND operation.\r | |
462 | \r | |
463 | @return The value written back to the PCI configuration register.\r | |
464 | \r | |
465 | **/\r | |
466 | UINT16\r | |
467 | EFIAPI\r | |
468 | PciAndThenOr16 (\r | |
469 | IN UINTN Address,\r | |
470 | IN UINT16 AndData,\r | |
471 | IN UINT16 OrData\r | |
472 | );\r | |
473 | \r | |
474 | /**\r | |
475 | Reads a bit field of a PCI configuration register.\r | |
476 | \r | |
477 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
478 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
479 | returned.\r | |
480 | \r | |
481 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
482 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
483 | If StartBit is greater than 15, then ASSERT().\r | |
484 | If EndBit is greater than 15, then ASSERT().\r | |
485 | If EndBit is less than StartBit, then ASSERT().\r | |
486 | \r | |
487 | @param Address PCI configuration register to read.\r | |
488 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
489 | Range 0..15.\r | |
490 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
491 | Range 0..15.\r | |
492 | \r | |
493 | @return The value of the bit field read from the PCI configuration register.\r | |
494 | \r | |
495 | **/\r | |
496 | UINT16\r | |
497 | EFIAPI\r | |
498 | PciBitFieldRead16 (\r | |
499 | IN UINTN Address,\r | |
500 | IN UINTN StartBit,\r | |
501 | IN UINTN EndBit\r | |
502 | );\r | |
503 | \r | |
504 | /**\r | |
505 | Writes a bit field to a PCI configuration register.\r | |
506 | \r | |
507 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
508 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
509 | destination PCI configuration register are preserved. The new value of the\r | |
510 | 16-bit register is returned.\r | |
511 | \r | |
512 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
513 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
514 | If StartBit is greater than 15, then ASSERT().\r | |
515 | If EndBit is greater than 15, then ASSERT().\r | |
516 | If EndBit is less than StartBit, then ASSERT().\r | |
517 | \r | |
518 | @param Address PCI configuration register to write.\r | |
519 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
520 | Range 0..15.\r | |
521 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
522 | Range 0..15.\r | |
523 | @param Value New value of the bit field.\r | |
524 | \r | |
525 | @return The value written back to the PCI configuration register.\r | |
526 | \r | |
527 | **/\r | |
528 | UINT16\r | |
529 | EFIAPI\r | |
530 | PciBitFieldWrite16 (\r | |
531 | IN UINTN Address,\r | |
532 | IN UINTN StartBit,\r | |
533 | IN UINTN EndBit,\r | |
534 | IN UINT16 Value\r | |
535 | );\r | |
536 | \r | |
537 | /**\r | |
538 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
539 | writes the result back to the bit field in the 16-bit port.\r | |
540 | \r | |
541 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
542 | bitwise inclusive OR between the read result and the value specified by\r | |
543 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
544 | specified by Address. The value written to the PCI configuration register is\r | |
545 | returned. This function must guarantee that all PCI read and write operations\r | |
546 | are serialized. Extra left bits in OrData are stripped.\r | |
547 | \r | |
548 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
549 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
550 | If StartBit is greater than 15, then ASSERT().\r | |
551 | If EndBit is greater than 15, then ASSERT().\r | |
552 | If EndBit is less than StartBit, then ASSERT().\r | |
553 | \r | |
554 | @param Address PCI configuration register to write.\r | |
555 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
556 | Range 0..15.\r | |
557 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
558 | Range 0..15.\r | |
559 | @param OrData The value to OR with the PCI configuration register.\r | |
560 | \r | |
561 | @return The value written back to the PCI configuration register.\r | |
562 | \r | |
563 | **/\r | |
564 | UINT16\r | |
565 | EFIAPI\r | |
566 | PciBitFieldOr16 (\r | |
567 | IN UINTN Address,\r | |
568 | IN UINTN StartBit,\r | |
569 | IN UINTN EndBit,\r | |
570 | IN UINT16 OrData\r | |
571 | );\r | |
572 | \r | |
573 | /**\r | |
574 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
575 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
576 | \r | |
577 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
578 | bitwise AND between the read result and the value specified by AndData, and\r | |
579 | writes the result to the 16-bit PCI configuration register specified by\r | |
580 | Address. The value written to the PCI configuration register is returned.\r | |
581 | This function must guarantee that all PCI read and write operations are\r | |
582 | serialized. Extra left bits in AndData are stripped.\r | |
583 | \r | |
584 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
585 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
586 | If StartBit is greater than 15, then ASSERT().\r | |
587 | If EndBit is greater than 15, then ASSERT().\r | |
588 | If EndBit is less than StartBit, then ASSERT().\r | |
589 | \r | |
590 | @param Address PCI configuration register to write.\r | |
591 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
592 | Range 0..15.\r | |
593 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
594 | Range 0..15.\r | |
595 | @param AndData The value to AND with the PCI configuration register.\r | |
596 | \r | |
597 | @return The value written back to the PCI configuration register.\r | |
598 | \r | |
599 | **/\r | |
600 | UINT16\r | |
601 | EFIAPI\r | |
602 | PciBitFieldAnd16 (\r | |
603 | IN UINTN Address,\r | |
604 | IN UINTN StartBit,\r | |
605 | IN UINTN EndBit,\r | |
606 | IN UINT16 AndData\r | |
607 | );\r | |
608 | \r | |
609 | /**\r | |
610 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
611 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
612 | 16-bit port.\r | |
613 | \r | |
614 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
615 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
616 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
617 | configuration register specified by Address. The value written to the PCI\r | |
618 | configuration register is returned. This function must guarantee that all PCI\r | |
619 | read and write operations are serialized. Extra left bits in both AndData and\r | |
620 | OrData are stripped.\r | |
621 | \r | |
622 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
623 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
624 | If StartBit is greater than 15, then ASSERT().\r | |
625 | If EndBit is greater than 15, then ASSERT().\r | |
626 | If EndBit is less than StartBit, then ASSERT().\r | |
627 | \r | |
628 | @param Address PCI configuration register to write.\r | |
629 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
630 | Range 0..15.\r | |
631 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
632 | Range 0..15.\r | |
633 | @param AndData The value to AND with the PCI configuration register.\r | |
634 | @param OrData The value to OR with the result of the AND operation.\r | |
635 | \r | |
636 | @return The value written back to the PCI configuration register.\r | |
637 | \r | |
638 | **/\r | |
639 | UINT16\r | |
640 | EFIAPI\r | |
641 | PciBitFieldAndThenOr16 (\r | |
642 | IN UINTN Address,\r | |
643 | IN UINTN StartBit,\r | |
644 | IN UINTN EndBit,\r | |
645 | IN UINT16 AndData,\r | |
646 | IN UINT16 OrData\r | |
647 | );\r | |
648 | \r | |
649 | /**\r | |
650 | Reads a 32-bit PCI configuration register.\r | |
651 | \r | |
652 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
653 | This function must guarantee that all PCI read and write operations are\r | |
654 | serialized.\r | |
655 | \r | |
656 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
657 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
658 | \r | |
659 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
660 | Register.\r | |
661 | \r | |
662 | @return The read value from the PCI configuration register.\r | |
663 | \r | |
664 | **/\r | |
665 | UINT32\r | |
666 | EFIAPI\r | |
667 | PciRead32 (\r | |
668 | IN UINTN Address\r | |
669 | );\r | |
670 | \r | |
671 | /**\r | |
672 | Writes a 32-bit PCI configuration register.\r | |
673 | \r | |
674 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
675 | value specified by Value. Value is returned. This function must guarantee\r | |
676 | that all PCI read and write operations are serialized.\r | |
677 | \r | |
678 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
679 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
680 | \r | |
681 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
682 | Register.\r | |
683 | @param Value The value to write.\r | |
684 | \r | |
685 | @return The value written to the PCI configuration register.\r | |
686 | \r | |
687 | **/\r | |
688 | UINT32\r | |
689 | EFIAPI\r | |
690 | PciWrite32 (\r | |
691 | IN UINTN Address,\r | |
94646ec0 | 692 | IN UINT32 Value\r |
fb3df220 | 693 | );\r |
694 | \r | |
695 | /**\r | |
696 | Performs a bitwise inclusive OR of a 32-bit PCI configuration register with\r | |
697 | a 32-bit value.\r | |
698 | \r | |
699 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
700 | bitwise inclusive OR between the read result and the value specified by\r | |
701 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
702 | specified by Address. The value written to the PCI configuration register is\r | |
703 | returned. This function must guarantee that all PCI read and write operations\r | |
704 | are serialized.\r | |
705 | \r | |
706 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
707 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
708 | \r | |
709 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
710 | Register.\r | |
711 | @param OrData The value to OR with the PCI configuration register.\r | |
712 | \r | |
713 | @return The value written back to the PCI configuration register.\r | |
714 | \r | |
715 | **/\r | |
716 | UINT32\r | |
717 | EFIAPI\r | |
718 | PciOr32 (\r | |
719 | IN UINTN Address,\r | |
720 | IN UINT32 OrData\r | |
721 | );\r | |
722 | \r | |
723 | /**\r | |
724 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
725 | value.\r | |
726 | \r | |
727 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
728 | bitwise AND between the read result and the value specified by AndData, and\r | |
729 | writes the result to the 32-bit PCI configuration register specified by\r | |
730 | Address. The value written to the PCI configuration register is returned.\r | |
731 | This function must guarantee that all PCI read and write operations are\r | |
732 | serialized.\r | |
733 | \r | |
734 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
735 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
736 | \r | |
737 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
738 | Register.\r | |
739 | @param AndData The value to AND with the PCI configuration register.\r | |
740 | \r | |
741 | @return The value written back to the PCI configuration register.\r | |
742 | \r | |
743 | **/\r | |
744 | UINT32\r | |
745 | EFIAPI\r | |
746 | PciAnd32 (\r | |
747 | IN UINTN Address,\r | |
748 | IN UINT32 AndData\r | |
749 | );\r | |
750 | \r | |
751 | /**\r | |
752 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
753 | value, followed a bitwise inclusive OR with another 32-bit value.\r | |
754 | \r | |
755 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
756 | bitwise AND between the read result and the value specified by AndData,\r | |
757 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
758 | the value specified by OrData, and writes the result to the 32-bit PCI\r | |
759 | configuration register specified by Address. The value written to the PCI\r | |
760 | configuration register is returned. This function must guarantee that all PCI\r | |
761 | read and write operations are serialized.\r | |
762 | \r | |
763 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
764 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
765 | \r | |
766 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
767 | Register.\r | |
768 | @param AndData The value to AND with the PCI configuration register.\r | |
769 | @param OrData The value to OR with the result of the AND operation.\r | |
770 | \r | |
771 | @return The value written back to the PCI configuration register.\r | |
772 | \r | |
773 | **/\r | |
774 | UINT32\r | |
775 | EFIAPI\r | |
776 | PciAndThenOr32 (\r | |
777 | IN UINTN Address,\r | |
778 | IN UINT32 AndData,\r | |
779 | IN UINT32 OrData\r | |
780 | );\r | |
781 | \r | |
782 | /**\r | |
783 | Reads a bit field of a PCI configuration register.\r | |
784 | \r | |
785 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
786 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
787 | returned.\r | |
788 | \r | |
789 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
790 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
791 | If StartBit is greater than 31, then ASSERT().\r | |
792 | If EndBit is greater than 31, then ASSERT().\r | |
793 | If EndBit is less than StartBit, then ASSERT().\r | |
794 | \r | |
795 | @param Address PCI configuration register to read.\r | |
796 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
797 | Range 0..31.\r | |
798 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
799 | Range 0..31.\r | |
800 | \r | |
801 | @return The value of the bit field read from the PCI configuration register.\r | |
802 | \r | |
803 | **/\r | |
804 | UINT32\r | |
805 | EFIAPI\r | |
806 | PciBitFieldRead32 (\r | |
807 | IN UINTN Address,\r | |
808 | IN UINTN StartBit,\r | |
809 | IN UINTN EndBit\r | |
810 | );\r | |
811 | \r | |
812 | /**\r | |
813 | Writes a bit field to a PCI configuration register.\r | |
814 | \r | |
815 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
816 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
817 | destination PCI configuration register are preserved. The new value of the\r | |
818 | 32-bit register is returned.\r | |
819 | \r | |
820 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
821 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
822 | If StartBit is greater than 31, then ASSERT().\r | |
823 | If EndBit is greater than 31, then ASSERT().\r | |
824 | If EndBit is less than StartBit, then ASSERT().\r | |
825 | \r | |
826 | @param Address PCI configuration register to write.\r | |
827 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
828 | Range 0..31.\r | |
829 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
830 | Range 0..31.\r | |
831 | @param Value New value of the bit field.\r | |
832 | \r | |
833 | @return The value written back to the PCI configuration register.\r | |
834 | \r | |
835 | **/\r | |
836 | UINT32\r | |
837 | EFIAPI\r | |
838 | PciBitFieldWrite32 (\r | |
839 | IN UINTN Address,\r | |
840 | IN UINTN StartBit,\r | |
841 | IN UINTN EndBit,\r | |
842 | IN UINT32 Value\r | |
843 | );\r | |
844 | \r | |
845 | /**\r | |
846 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
847 | writes the result back to the bit field in the 32-bit port.\r | |
848 | \r | |
849 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
850 | bitwise inclusive OR between the read result and the value specified by\r | |
851 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
852 | specified by Address. The value written to the PCI configuration register is\r | |
853 | returned. This function must guarantee that all PCI read and write operations\r | |
854 | are serialized. Extra left bits in OrData are stripped.\r | |
855 | \r | |
856 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
857 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
858 | If StartBit is greater than 31, then ASSERT().\r | |
859 | If EndBit is greater than 31, then ASSERT().\r | |
860 | If EndBit is less than StartBit, then ASSERT().\r | |
861 | \r | |
862 | @param Address PCI configuration register to write.\r | |
863 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
864 | Range 0..31.\r | |
865 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
866 | Range 0..31.\r | |
867 | @param OrData The value to OR with the PCI configuration register.\r | |
868 | \r | |
869 | @return The value written back to the PCI configuration register.\r | |
870 | \r | |
871 | **/\r | |
872 | UINT32\r | |
873 | EFIAPI\r | |
874 | PciBitFieldOr32 (\r | |
875 | IN UINTN Address,\r | |
876 | IN UINTN StartBit,\r | |
877 | IN UINTN EndBit,\r | |
878 | IN UINT32 OrData\r | |
879 | );\r | |
880 | \r | |
881 | /**\r | |
882 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
883 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
884 | \r | |
885 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
886 | bitwise AND between the read result and the value specified by AndData, and\r | |
887 | writes the result to the 32-bit PCI configuration register specified by\r | |
888 | Address. The value written to the PCI configuration register is returned.\r | |
889 | This function must guarantee that all PCI read and write operations are\r | |
890 | serialized. Extra left bits in AndData are stripped.\r | |
891 | \r | |
892 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
893 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
894 | If StartBit is greater than 31, then ASSERT().\r | |
895 | If EndBit is greater than 31, then ASSERT().\r | |
896 | If EndBit is less than StartBit, then ASSERT().\r | |
897 | \r | |
898 | @param Address PCI configuration register to write.\r | |
899 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
900 | Range 0..31.\r | |
901 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
902 | Range 0..31.\r | |
903 | @param AndData The value to AND with the PCI configuration register.\r | |
904 | \r | |
905 | @return The value written back to the PCI configuration register.\r | |
906 | \r | |
907 | **/\r | |
908 | UINT32\r | |
909 | EFIAPI\r | |
910 | PciBitFieldAnd32 (\r | |
911 | IN UINTN Address,\r | |
912 | IN UINTN StartBit,\r | |
913 | IN UINTN EndBit,\r | |
914 | IN UINT32 AndData\r | |
915 | );\r | |
916 | \r | |
917 | /**\r | |
918 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
919 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
920 | 32-bit port.\r | |
921 | \r | |
922 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
923 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
924 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
925 | configuration register specified by Address. The value written to the PCI\r | |
926 | configuration register is returned. This function must guarantee that all PCI\r | |
927 | read and write operations are serialized. Extra left bits in both AndData and\r | |
928 | OrData are stripped.\r | |
929 | \r | |
930 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
931 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
932 | If StartBit is greater than 31, then ASSERT().\r | |
933 | If EndBit is greater than 31, then ASSERT().\r | |
934 | If EndBit is less than StartBit, then ASSERT().\r | |
935 | \r | |
936 | @param Address PCI configuration register to write.\r | |
937 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
938 | Range 0..31.\r | |
939 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
940 | Range 0..31.\r | |
941 | @param AndData The value to AND with the PCI configuration register.\r | |
942 | @param OrData The value to OR with the result of the AND operation.\r | |
943 | \r | |
944 | @return The value written back to the PCI configuration register.\r | |
945 | \r | |
946 | **/\r | |
947 | UINT32\r | |
948 | EFIAPI\r | |
949 | PciBitFieldAndThenOr32 (\r | |
950 | IN UINTN Address,\r | |
951 | IN UINTN StartBit,\r | |
952 | IN UINTN EndBit,\r | |
953 | IN UINT32 AndData,\r | |
954 | IN UINT32 OrData\r | |
955 | );\r | |
956 | \r | |
957 | /**\r | |
958 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
959 | \r | |
960 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
961 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
962 | configuration registers from a single PCI function to be read. Size is\r | |
963 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
964 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
965 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
966 | end of the range.\r | |
967 | \r | |
968 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
969 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
970 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
971 | \r | |
972 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
973 | Function and Register.\r | |
974 | @param Size Size in bytes of the transfer.\r | |
975 | @param Buffer Pointer to a buffer receiving the data read.\r | |
976 | \r | |
977 | @return Size\r | |
978 | \r | |
979 | **/\r | |
980 | UINTN\r | |
981 | EFIAPI\r | |
982 | PciReadBuffer (\r | |
983 | IN UINTN StartAddress,\r | |
984 | IN UINTN Size,\r | |
985 | OUT VOID *Buffer\r | |
986 | );\r | |
987 | \r | |
988 | /**\r | |
989 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
990 | configuration space.\r | |
991 | \r | |
992 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
993 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
994 | configuration registers from a single PCI function to be written. Size is\r | |
995 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
996 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
997 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
998 | and the end of the range.\r | |
999 | \r | |
1000 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1001 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1002 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1003 | \r | |
1004 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1005 | Function and Register.\r | |
1006 | @param Size Size in bytes of the transfer.\r | |
1007 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1008 | \r | |
9199040c | 1009 | @return Size written to StartAddress.\r |
fb3df220 | 1010 | \r |
1011 | **/\r | |
1012 | UINTN\r | |
1013 | EFIAPI\r | |
1014 | PciWriteBuffer (\r | |
1015 | IN UINTN StartAddress,\r | |
1016 | IN UINTN Size,\r | |
1017 | IN VOID *Buffer\r | |
1018 | );\r | |
1019 | \r | |
1020 | #endif\r |