| fe69ac84 |
1 | /** @file\r |
| 2 | The PCI configuration Library Services that carry out PCI configuration and enable\r |
| 3 | the PCI operations to be replayed during an S3 resume. This library class\r |
| 4 | maps directly on top of the PciLib class. \r |
| 5 | \r |
| 6 | Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>\r |
| 7 | \r |
| 8 | This program and the accompanying materials\r |
| 9 | are licensed and made available under the terms and conditions\r |
| 10 | of the BSD License which accompanies this distribution. The\r |
| 11 | full text of the license may be found at\r |
| 12 | http://opensource.org/licenses/bsd-license.php\r |
| 13 | \r |
| 14 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 15 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 16 | \r |
| 17 | **/\r |
| 18 | \r |
| 19 | #ifndef __S3_PCI_LIB_H__\r |
| 20 | #define __S3_PCI_LIB_H__\r |
| 21 | \r |
| 22 | /**\r |
| 23 | Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an\r |
| 24 | address that can be passed to the S3 PCI Library functions.\r |
| 25 | \r |
| 26 | @param Bus The PCI Bus number. Range 0..255.\r |
| 27 | @param Device The PCI Device number. Range 0..31.\r |
| 28 | @param Function The PCI Function number. Range 0..7.\r |
| 29 | @param Register The PCI Register number. Range 0..255 for PCI. Range 0..4095\r |
| 30 | for PCI Express.\r |
| 31 | \r |
| 32 | @return The encoded PCI address.\r |
| 33 | \r |
| 34 | **/\r |
| 35 | #define S3_PCI_LIB_ADDRESS(Bus,Device,Function,Register) \\r |
| 36 | (((Register) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r |
| 37 | \r |
| 38 | /**\r |
| 39 | \r |
| 40 | Reads and returns the 8-bit PCI configuration register specified by Address, \r |
| 41 | and saves the value in the S3 script to be replayed on S3 resume.\r |
| 42 | This function must guarantee that all PCI read and write operations are\r |
| 43 | serialized.\r |
| 44 | \r |
| 45 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 46 | \r |
| 47 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r |
| 48 | Register.\r |
| 49 | \r |
| 50 | @return The value read from the PCI configuration register.\r |
| 51 | \r |
| 52 | **/\r |
| 53 | UINT8\r |
| 54 | EFIAPI\r |
| 55 | S3PciRead8 (\r |
| 56 | IN UINTN Address\r |
| 57 | );\r |
| 58 | \r |
| 59 | /**\r |
| 60 | Writes an 8-bit PCI configuration register, and saves the value in the S3\r |
| 61 | script to be replayed on S3 resume.\r |
| 62 | \r |
| 63 | Writes the 8-bit PCI configuration register specified by Address with the\r |
| 64 | value specified by Value. Value is returned. This function must guarantee\r |
| 65 | that all PCI read and write operations are serialized.\r |
| 66 | \r |
| 67 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 68 | \r |
| 69 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r |
| 70 | Register.\r |
| 71 | @param[in] Value The value to write.\r |
| 72 | \r |
| 73 | @return The value written to the PCI configuration register.\r |
| 74 | \r |
| 75 | **/\r |
| 76 | UINT8\r |
| 77 | EFIAPI\r |
| 78 | S3PciWrite8 (\r |
| 79 | IN UINTN Address,\r |
| 80 | IN UINT8 Value\r |
| 81 | );\r |
| 82 | \r |
| 83 | /**\r |
| 84 | Performs a bitwise OR of an 8-bit PCI configuration register with\r |
| 85 | an 8-bit value, and saves the value in the S3 script to be replayed on S3 resume.\r |
| 86 | \r |
| 87 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 88 | bitwise OR between the read result and the value specified by\r |
| 89 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| 90 | specified by Address. The value written to the PCI configuration register is\r |
| 91 | returned. This function must guarantee that all PCI read and write operations\r |
| 92 | are serialized.\r |
| 93 | \r |
| 94 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 95 | \r |
| 96 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r |
| 97 | Register.\r |
| 98 | @param[in] OrData The value to OR with the PCI configuration register.\r |
| 99 | \r |
| 100 | @return The value written back to the PCI configuration register.\r |
| 101 | \r |
| 102 | **/\r |
| 103 | UINT8\r |
| 104 | EFIAPI\r |
| 105 | S3PciOr8 (\r |
| 106 | IN UINTN Address,\r |
| 107 | IN UINT8 OrData\r |
| 108 | );\r |
| 109 | \r |
| 110 | /**\r |
| 111 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
| 112 | value, and saves the value in the S3 script to be replayed on S3 resume.\r |
| 113 | \r |
| 114 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 115 | bitwise AND between the read result and the value specified by AndData, and\r |
| 116 | writes the result to the 8-bit PCI configuration register specified by\r |
| 117 | Address. The value written to the PCI configuration register is returned.\r |
| 118 | This function must guarantee that all PCI read and write operations are\r |
| 119 | serialized.\r |
| 120 | \r |
| 121 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 122 | \r |
| 123 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r |
| 124 | Register.\r |
| 125 | @param[in] AndData The value to AND with the PCI configuration register.\r |
| 126 | \r |
| 127 | @return The value written back to the PCI configuration register.\r |
| 128 | \r |
| 129 | **/\r |
| 130 | UINT8\r |
| 131 | EFIAPI\r |
| 132 | S3PciAnd8 (\r |
| 133 | IN UINTN Address,\r |
| 134 | IN UINT8 AndData\r |
| 135 | );\r |
| 136 | \r |
| 137 | /**\r |
| 138 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
| 139 | value, followed a bitwise OR with another 8-bit value, and saves\r |
| 140 | the value in the S3 script to be replayed on S3 resume.\r |
| 141 | \r |
| 142 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 143 | bitwise AND between the read result and the value specified by AndData,\r |
| 144 | performs a bitwise OR between the result of the AND operation and\r |
| 145 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
| 146 | configuration register specified by Address. The value written to the PCI\r |
| 147 | configuration register is returned. This function must guarantee that all PCI\r |
| 148 | read and write operations are serialized.\r |
| 149 | \r |
| 150 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 151 | \r |
| 152 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r |
| 153 | Register.\r |
| 154 | @param[in] AndData The value to AND with the PCI configuration register.\r |
| 155 | @param[in] OrData The value to OR with the result of the AND operation.\r |
| 156 | \r |
| 157 | @return The value written back to the PCI configuration register.\r |
| 158 | \r |
| 159 | **/\r |
| 160 | UINT8\r |
| 161 | EFIAPI\r |
| 162 | S3PciAndThenOr8 (\r |
| 163 | IN UINTN Address,\r |
| 164 | IN UINT8 AndData,\r |
| 165 | IN UINT8 OrData\r |
| 166 | );\r |
| 167 | \r |
| 168 | /**\r |
| 169 | Reads a bit field of a PCI configuration register, and saves the value in\r |
| 170 | the S3 script to be replayed on S3 resume.\r |
| 171 | \r |
| 172 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r |
| 173 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 174 | returned.\r |
| 175 | \r |
| 176 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 177 | If StartBit is greater than 7, then ASSERT().\r |
| 178 | If EndBit is greater than 7, then ASSERT().\r |
| 179 | If EndBit is less than StartBit, then ASSERT().\r |
| 180 | \r |
| 181 | @param[in] Address The PCI configuration register to read.\r |
| 182 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r |
| 183 | Range 0..7.\r |
| 184 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r |
| 185 | Range 0..7.\r |
| 186 | \r |
| 187 | @return The value of the bit field read from the PCI configuration register.\r |
| 188 | \r |
| 189 | **/\r |
| 190 | UINT8\r |
| 191 | EFIAPI\r |
| 192 | S3PciBitFieldRead8 (\r |
| 193 | IN UINTN Address,\r |
| 194 | IN UINTN StartBit,\r |
| 195 | IN UINTN EndBit\r |
| 196 | );\r |
| 197 | \r |
| 198 | /**\r |
| 199 | Writes a bit field to a PCI configuration register, and saves the value in\r |
| 200 | the S3 script to be replayed on S3 resume.\r |
| 201 | \r |
| 202 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 203 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 204 | destination PCI configuration register are preserved. The new value of the\r |
| 205 | 8-bit register is returned.\r |
| 206 | \r |
| 207 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 208 | If StartBit is greater than 7, then ASSERT().\r |
| 209 | If EndBit is greater than 7, then ASSERT().\r |
| 210 | If EndBit is less than StartBit, then ASSERT().\r |
| 211 | \r |
| 212 | @param[in] Address The PCI configuration register to write.\r |
| 213 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r |
| 214 | Range 0..7.\r |
| 215 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r |
| 216 | Range 0..7.\r |
| 217 | @param[in] Value New value of the bit field.\r |
| 218 | \r |
| 219 | @return The value written back to the PCI configuration register.\r |
| 220 | \r |
| 221 | **/\r |
| 222 | UINT8\r |
| 223 | EFIAPI\r |
| 224 | S3PciBitFieldWrite8 (\r |
| 225 | IN UINTN Address,\r |
| 226 | IN UINTN StartBit,\r |
| 227 | IN UINTN EndBit,\r |
| 228 | IN UINT8 Value\r |
| 229 | );\r |
| 230 | \r |
| 231 | /**\r |
| 232 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r |
| 233 | writes the result back to the bit field in the 8-bit port, and saves the value\r |
| 234 | in the S3 script to be replayed on S3 resume.\r |
| 235 | \r |
| 236 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 237 | bitwise OR between the read result and the value specified by\r |
| 238 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| 239 | specified by Address. The value written to the PCI configuration register is\r |
| 240 | returned. This function must guarantee that all PCI read and write operations\r |
| 241 | are serialized. Extra left bits in OrData are stripped.\r |
| 242 | \r |
| 243 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 244 | If StartBit is greater than 7, then ASSERT().\r |
| 245 | If EndBit is greater than 7, then ASSERT().\r |
| 246 | If EndBit is less than StartBit, then ASSERT().\r |
| 247 | \r |
| 248 | @param[in] Address The PCI configuration register to write.\r |
| 249 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r |
| 250 | Range 0..7.\r |
| 251 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r |
| 252 | Range 0..7.\r |
| 253 | @param[in] OrData The value to OR with the PCI configuration register.\r |
| 254 | \r |
| 255 | @return The value written back to the PCI configuration register.\r |
| 256 | \r |
| 257 | **/\r |
| 258 | UINT8\r |
| 259 | EFIAPI\r |
| 260 | S3PciBitFieldOr8 (\r |
| 261 | IN UINTN Address,\r |
| 262 | IN UINTN StartBit,\r |
| 263 | IN UINTN EndBit,\r |
| 264 | IN UINT8 OrData\r |
| 265 | );\r |
| 266 | \r |
| 267 | /**\r |
| 268 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r |
| 269 | AND, and writes the result back to the bit field in the 8-bit register and\r |
| 270 | saves the value in the S3 script to be replayed on S3 resume.\r |
| 271 | \r |
| 272 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 273 | bitwise AND between the read result and the value specified by AndData, and\r |
| 274 | writes the result to the 8-bit PCI configuration register specified by\r |
| 275 | Address. The value written to the PCI configuration register is returned.\r |
| 276 | This function must guarantee that all PCI read and write operations are\r |
| 277 | serialized. Extra left bits in AndData are stripped.\r |
| 278 | \r |
| 279 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 280 | If StartBit is greater than 7, then ASSERT().\r |
| 281 | If EndBit is greater than 7, then ASSERT().\r |
| 282 | If EndBit is less than StartBit, then ASSERT().\r |
| 283 | \r |
| 284 | @param[in] Address The PCI configuration register to write.\r |
| 285 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r |
| 286 | Range 0..7.\r |
| 287 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r |
| 288 | Range 0..7.\r |
| 289 | @param[in] AndData The value to AND with the PCI configuration register.\r |
| 290 | \r |
| 291 | @return The value written back to the PCI configuration register.\r |
| 292 | \r |
| 293 | **/\r |
| 294 | UINT8\r |
| 295 | EFIAPI\r |
| 296 | S3PciBitFieldAnd8 (\r |
| 297 | IN UINTN Address,\r |
| 298 | IN UINTN StartBit,\r |
| 299 | IN UINTN EndBit,\r |
| 300 | IN UINT8 AndData\r |
| 301 | );\r |
| 302 | \r |
| 303 | /**\r |
| 304 | Reads a bit field in an 8-bit Address, performs a bitwise AND followed by a\r |
| 305 | bitwise OR, and writes the result back to the bit field in the\r |
| 306 | 8-bit port, and saves the value in the S3 script to be replayed on S3 resume.\r |
| 307 | \r |
| 308 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 309 | bitwise AND followed by a bitwise OR between the read result and\r |
| 310 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
| 311 | configuration register specified by Address. The value written to the PCI\r |
| 312 | configuration register is returned. This function must guarantee that all PCI\r |
| 313 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 314 | OrData are stripped.\r |
| 315 | \r |
| 316 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 317 | If StartBit is greater than 7, then ASSERT().\r |
| 318 | If EndBit is greater than 7, then ASSERT().\r |
| 319 | If EndBit is less than StartBit, then ASSERT().\r |
| 320 | \r |
| 321 | @param[in] Address The PCI configuration register to write.\r |
| 322 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r |
| 323 | Range 0..7.\r |
| 324 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r |
| 325 | Range 0..7.\r |
| 326 | @param[in] AndData The value to AND with the PCI configuration register.\r |
| 327 | @param[in] OrData The value to OR with the result of the AND operation.\r |
| 328 | \r |
| 329 | @return The value written back to the PCI configuration register.\r |
| 330 | \r |
| 331 | **/\r |
| 332 | UINT8\r |
| 333 | EFIAPI\r |
| 334 | S3PciBitFieldAndThenOr8 (\r |
| 335 | IN UINTN Address,\r |
| 336 | IN UINTN StartBit,\r |
| 337 | IN UINTN EndBit,\r |
| 338 | IN UINT8 AndData,\r |
| 339 | IN UINT8 OrData\r |
| 340 | );\r |
| 341 | \r |
| 342 | /**\r |
| 343 | Reads a 16-bit PCI configuration register, and saves the value in the S3\r |
| 344 | script to be replayed on S3 resume.\r |
| 345 | \r |
| 346 | Reads and returns the 16-bit PCI configuration register specified by Address.\r |
| 347 | This function must guarantee that all PCI read and write operations are\r |
| 348 | serialized.\r |
| 349 | \r |
| 350 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 351 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 352 | \r |
| 353 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r |
| 354 | Register.\r |
| 355 | \r |
| 356 | @return The read value from the PCI configuration register.\r |
| 357 | \r |
| 358 | **/\r |
| 359 | UINT16\r |
| 360 | EFIAPI\r |
| 361 | S3PciRead16 (\r |
| 362 | IN UINTN Address\r |
| 363 | );\r |
| 364 | \r |
| 365 | /**\r |
| 366 | Writes a 16-bit PCI configuration register, and saves the value in the S3\r |
| 367 | script to be replayed on S3 resume.\r |
| 368 | \r |
| 369 | Writes the 16-bit PCI configuration register specified by Address with the\r |
| 370 | value specified by Value. Value is returned. This function must guarantee\r |
| 371 | that all PCI read and write operations are serialized.\r |
| 372 | \r |
| 373 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 374 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 375 | \r |
| 376 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r |
| 377 | Register.\r |
| 378 | @param[in] Value The value to write.\r |
| 379 | \r |
| 380 | @return The value written to the PCI configuration register.\r |
| 381 | \r |
| 382 | **/\r |
| 383 | UINT16\r |
| 384 | EFIAPI\r |
| 385 | S3PciWrite16 (\r |
| 386 | IN UINTN Address,\r |
| 387 | IN UINT16 Value\r |
| 388 | );\r |
| 389 | \r |
| 390 | /**\r |
| 391 | Performs a bitwise OR of a 16-bit PCI configuration register with\r |
| 392 | a 16-bit value, and saves the value in the S3 script to be replayed on S3 resume.\r |
| 393 | \r |
| 394 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 395 | bitwise OR between the read result and the value specified by\r |
| 396 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| 397 | specified by Address. The value written to the PCI configuration register is\r |
| 398 | returned. This function must guarantee that all PCI read and write operations\r |
| 399 | are serialized.\r |
| 400 | \r |
| 401 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 402 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 403 | \r |
| 404 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r |
| 405 | Register.\r |
| 406 | @param[in] OrData The value to OR with the PCI configuration register.\r |
| 407 | \r |
| 408 | @return The value written back to the PCI configuration register.\r |
| 409 | \r |
| 410 | **/\r |
| 411 | UINT16\r |
| 412 | EFIAPI\r |
| 413 | S3PciOr16 (\r |
| 414 | IN UINTN Address,\r |
| 415 | IN UINT16 OrData\r |
| 416 | );\r |
| 417 | \r |
| 418 | /**\r |
| 419 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
| 420 | value, and saves the value in the S3 script to be replayed on S3 resume.\r |
| 421 | \r |
| 422 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 423 | bitwise AND between the read result and the value specified by AndData, and\r |
| 424 | writes the result to the 16-bit PCI configuration register specified by\r |
| 425 | Address. The value written to the PCI configuration register is returned.\r |
| 426 | This function must guarantee that all PCI read and write operations are\r |
| 427 | serialized.\r |
| 428 | \r |
| 429 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 430 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 431 | \r |
| 432 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r |
| 433 | Register.\r |
| 434 | @param[in] AndData The value to AND with the PCI configuration register.\r |
| 435 | \r |
| 436 | @return The value written back to the PCI configuration register.\r |
| 437 | \r |
| 438 | **/\r |
| 439 | UINT16\r |
| 440 | EFIAPI\r |
| 441 | S3PciAnd16 (\r |
| 442 | IN UINTN Address,\r |
| 443 | IN UINT16 AndData\r |
| 444 | );\r |
| 445 | \r |
| 446 | /**\r |
| 447 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
| 448 | value, followed a bitwise OR with another 16-bit value, and saves\r |
| 449 | the value in the S3 script to be replayed on S3 resume.\r |
| 450 | \r |
| 451 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 452 | bitwise AND between the read result and the value specified by AndData,\r |
| 453 | performs a bitwise OR between the result of the AND operation and\r |
| 454 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
| 455 | configuration register specified by Address. The value written to the PCI\r |
| 456 | configuration register is returned. This function must guarantee that all PCI\r |
| 457 | read and write operations are serialized.\r |
| 458 | \r |
| 459 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 460 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 461 | \r |
| 462 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r |
| 463 | Register.\r |
| 464 | @param[in] AndData The value to AND with the PCI configuration register.\r |
| 465 | @param[in] OrData The value to OR with the result of the AND operation.\r |
| 466 | \r |
| 467 | @return The value written back to the PCI configuration register.\r |
| 468 | \r |
| 469 | **/\r |
| 470 | UINT16\r |
| 471 | EFIAPI\r |
| 472 | S3PciAndThenOr16 (\r |
| 473 | IN UINTN Address,\r |
| 474 | IN UINT16 AndData,\r |
| 475 | IN UINT16 OrData\r |
| 476 | );\r |
| 477 | \r |
| 478 | /**\r |
| 479 | Reads a bit field of a PCI configuration register, and saves the value in\r |
| 480 | the S3 script to be replayed on S3 resume.\r |
| 481 | \r |
| 482 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r |
| 483 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 484 | returned.\r |
| 485 | \r |
| 486 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 487 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 488 | If StartBit is greater than 15, then ASSERT().\r |
| 489 | If EndBit is greater than 15, then ASSERT().\r |
| 490 | If EndBit is less than StartBit, then ASSERT().\r |
| 491 | \r |
| 492 | @param[in] Address The PCI configuration register to read.\r |
| 493 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r |
| 494 | Range 0..15.\r |
| 495 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r |
| 496 | Range 0..15.\r |
| 497 | \r |
| 498 | @return The value of the bit field read from the PCI configuration register.\r |
| 499 | \r |
| 500 | **/\r |
| 501 | UINT16\r |
| 502 | EFIAPI\r |
| 503 | S3PciBitFieldRead16 (\r |
| 504 | IN UINTN Address,\r |
| 505 | IN UINTN StartBit,\r |
| 506 | IN UINTN EndBit\r |
| 507 | );\r |
| 508 | \r |
| 509 | /**\r |
| 510 | Writes a bit field to a PCI configuration register, and saves the value in\r |
| 511 | the S3 script to be replayed on S3 resume.\r |
| 512 | \r |
| 513 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 514 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 515 | destination PCI configuration register are preserved. The new value of the\r |
| 516 | 16-bit register is returned.\r |
| 517 | \r |
| 518 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 519 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 520 | If StartBit is greater than 15, then ASSERT().\r |
| 521 | If EndBit is greater than 15, then ASSERT().\r |
| 522 | If EndBit is less than StartBit, then ASSERT().\r |
| 523 | \r |
| 524 | @param[in] Address The PCI configuration register to write.\r |
| 525 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r |
| 526 | Range 0..15.\r |
| 527 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r |
| 528 | Range 0..15.\r |
| 529 | @param[in] Value New value of the bit field.\r |
| 530 | \r |
| 531 | @return The value written back to the PCI configuration register.\r |
| 532 | \r |
| 533 | **/\r |
| 534 | UINT16\r |
| 535 | EFIAPI\r |
| 536 | S3PciBitFieldWrite16 (\r |
| 537 | IN UINTN Address,\r |
| 538 | IN UINTN StartBit,\r |
| 539 | IN UINTN EndBit,\r |
| 540 | IN UINT16 Value\r |
| 541 | );\r |
| 542 | \r |
| 543 | /**\r |
| 544 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r |
| 545 | writes the result back to the bit field in the 16-bit port, and saves the value\r |
| 546 | in the S3 script to be replayed on S3 resume.\r |
| 547 | \r |
| 548 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 549 | bitwise OR between the read result and the value specified by\r |
| 550 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| 551 | specified by Address. The value written to the PCI configuration register is\r |
| 552 | returned. This function must guarantee that all PCI read and write operations\r |
| 553 | are serialized. Extra left bits in OrData are stripped.\r |
| 554 | \r |
| 555 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 556 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 557 | If StartBit is greater than 15, then ASSERT().\r |
| 558 | If EndBit is greater than 15, then ASSERT().\r |
| 559 | If EndBit is less than StartBit, then ASSERT().\r |
| 560 | \r |
| 561 | @param[in] Address The PCI configuration register to write.\r |
| 562 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r |
| 563 | Range 0..15.\r |
| 564 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r |
| 565 | Range 0..15.\r |
| 566 | @param[in] OrData The value to OR with the PCI configuration register.\r |
| 567 | \r |
| 568 | @return The value written back to the PCI configuration register.\r |
| 569 | \r |
| 570 | **/\r |
| 571 | UINT16\r |
| 572 | EFIAPI\r |
| 573 | S3PciBitFieldOr16 (\r |
| 574 | IN UINTN Address,\r |
| 575 | IN UINTN StartBit,\r |
| 576 | IN UINTN EndBit,\r |
| 577 | IN UINT16 OrData\r |
| 578 | );\r |
| 579 | \r |
| 580 | /**\r |
| 581 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r |
| 582 | AND, and writes the result back to the bit field in the 16-bit register and\r |
| 583 | saves the value in the S3 script to be replayed on S3 resume.\r |
| 584 | \r |
| 585 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 586 | bitwise AND between the read result and the value specified by AndData, and\r |
| 587 | writes the result to the 16-bit PCI configuration register specified by\r |
| 588 | Address. The value written to the PCI configuration register is returned.\r |
| 589 | This function must guarantee that all PCI read and write operations are\r |
| 590 | serialized. Extra left bits in AndData are stripped.\r |
| 591 | \r |
| 592 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 593 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 594 | If StartBit is greater than 15, then ASSERT().\r |
| 595 | If EndBit is greater than 15, then ASSERT().\r |
| 596 | If EndBit is less than StartBit, then ASSERT().\r |
| 597 | \r |
| 598 | @param[in] Address The PCI configuration register to write.\r |
| 599 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r |
| 600 | Range 0..15.\r |
| 601 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r |
| 602 | Range 0..15.\r |
| 603 | @param[in] AndData The value to AND with the PCI configuration register.\r |
| 604 | \r |
| 605 | @return The value written back to the PCI configuration register.\r |
| 606 | \r |
| 607 | **/\r |
| 608 | UINT16\r |
| 609 | EFIAPI\r |
| 610 | S3PciBitFieldAnd16 (\r |
| 611 | IN UINTN Address,\r |
| 612 | IN UINTN StartBit,\r |
| 613 | IN UINTN EndBit,\r |
| 614 | IN UINT16 AndData\r |
| 615 | );\r |
| 616 | \r |
| 617 | /**\r |
| 618 | Reads a bit field in a 16-bit Address, performs a bitwise AND followed by a\r |
| 619 | bitwise OR, and writes the result back to the bit field in the\r |
| 620 | 16-bit port, and saves the value in the S3 script to be replayed on S3 resume.\r |
| 621 | \r |
| 622 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 623 | bitwise AND followed by a bitwise OR between the read result and\r |
| 624 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
| 625 | configuration register specified by Address. The value written to the PCI\r |
| 626 | configuration register is returned. This function must guarantee that all PCI\r |
| 627 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 628 | OrData are stripped.\r |
| 629 | \r |
| 630 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 631 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 632 | If StartBit is greater than 15, then ASSERT().\r |
| 633 | If EndBit is greater than 15, then ASSERT().\r |
| 634 | If EndBit is less than StartBit, then ASSERT().\r |
| 635 | \r |
| 636 | @param[in] Address The PCI configuration register to write.\r |
| 637 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r |
| 638 | Range 0..15.\r |
| 639 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r |
| 640 | Range 0..15.\r |
| 641 | @param[in] AndData The value to AND with the PCI configuration register.\r |
| 642 | @param[in] OrData The value to OR with the result of the AND operation.\r |
| 643 | \r |
| 644 | @return The value written back to the PCI configuration register.\r |
| 645 | \r |
| 646 | **/\r |
| 647 | UINT16\r |
| 648 | EFIAPI\r |
| 649 | S3PciBitFieldAndThenOr16 (\r |
| 650 | IN UINTN Address,\r |
| 651 | IN UINTN StartBit,\r |
| 652 | IN UINTN EndBit,\r |
| 653 | IN UINT16 AndData,\r |
| 654 | IN UINT16 OrData\r |
| 655 | );\r |
| 656 | \r |
| 657 | /**\r |
| 658 | Reads a 32-bit PCI configuration register, and saves the value in the S3\r |
| 659 | script to be replayed on S3 resume.\r |
| 660 | \r |
| 661 | Reads and returns the 32-bit PCI configuration register specified by Address.\r |
| 662 | This function must guarantee that all PCI read and write operations are\r |
| 663 | serialized.\r |
| 664 | \r |
| 665 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 666 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 667 | \r |
| 668 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r |
| 669 | Register.\r |
| 670 | \r |
| 671 | @return The read value from the PCI configuration register.\r |
| 672 | \r |
| 673 | **/\r |
| 674 | UINT32\r |
| 675 | EFIAPI\r |
| 676 | S3PciRead32 (\r |
| 677 | IN UINTN Address\r |
| 678 | );\r |
| 679 | \r |
| 680 | /**\r |
| 681 | Writes a 32-bit PCI configuration register, and saves the value in the S3\r |
| 682 | script to be replayed on S3 resume.\r |
| 683 | \r |
| 684 | Writes the 32-bit PCI configuration register specified by Address with the\r |
| 685 | value specified by Value. Value is returned. This function must guarantee\r |
| 686 | that all PCI read and write operations are serialized.\r |
| 687 | \r |
| 688 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 689 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 690 | \r |
| 691 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r |
| 692 | Register.\r |
| 693 | @param[in] Value The value to write.\r |
| 694 | \r |
| 695 | @return The value written to the PCI configuration register.\r |
| 696 | \r |
| 697 | **/\r |
| 698 | UINT32\r |
| 699 | EFIAPI\r |
| 700 | S3PciWrite32 (\r |
| 701 | IN UINTN Address,\r |
| 702 | IN UINT32 Value\r |
| 703 | );\r |
| 704 | \r |
| 705 | /**\r |
| 706 | Performs a bitwise OR of a 32-bit PCI configuration register with\r |
| 707 | a 32-bit value, and saves the value in the S3 script to be replayed on S3 resume.\r |
| 708 | \r |
| 709 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 710 | bitwise OR between the read result and the value specified by\r |
| 711 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| 712 | specified by Address. The value written to the PCI configuration register is\r |
| 713 | returned. This function must guarantee that all PCI read and write operations\r |
| 714 | are serialized.\r |
| 715 | \r |
| 716 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 717 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 718 | \r |
| 719 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r |
| 720 | Register.\r |
| 721 | @param[in] OrData The value to OR with the PCI configuration register.\r |
| 722 | \r |
| 723 | @return The value written back to the PCI configuration register.\r |
| 724 | \r |
| 725 | **/\r |
| 726 | UINT32\r |
| 727 | EFIAPI\r |
| 728 | S3PciOr32 (\r |
| 729 | IN UINTN Address,\r |
| 730 | IN UINT32 OrData\r |
| 731 | );\r |
| 732 | \r |
| 733 | /**\r |
| 734 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
| 735 | value, and saves the value in the S3 script to be replayed on S3 resume.\r |
| 736 | \r |
| 737 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 738 | bitwise AND between the read result and the value specified by AndData, and\r |
| 739 | writes the result to the 32-bit PCI configuration register specified by\r |
| 740 | Address. The value written to the PCI configuration register is returned.\r |
| 741 | This function must guarantee that all PCI read and write operations are\r |
| 742 | serialized.\r |
| 743 | \r |
| 744 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 745 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 746 | \r |
| 747 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r |
| 748 | Register.\r |
| 749 | @param[in] AndData The value to AND with the PCI configuration register.\r |
| 750 | \r |
| 751 | @return The value written back to the PCI configuration register.\r |
| 752 | \r |
| 753 | **/\r |
| 754 | UINT32\r |
| 755 | EFIAPI\r |
| 756 | S3PciAnd32 (\r |
| 757 | IN UINTN Address,\r |
| 758 | IN UINT32 AndData\r |
| 759 | );\r |
| 760 | \r |
| 761 | /**\r |
| 762 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
| 763 | value, followed a bitwise OR with another 32-bit value, and saves\r |
| 764 | the value in the S3 script to be replayed on S3 resume.\r |
| 765 | \r |
| 766 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 767 | bitwise AND between the read result and the value specified by AndData,\r |
| 768 | performs a bitwise OR between the result of the AND operation and\r |
| 769 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
| 770 | configuration register specified by Address. The value written to the PCI\r |
| 771 | configuration register is returned. This function must guarantee that all PCI\r |
| 772 | read and write operations are serialized.\r |
| 773 | \r |
| 774 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 775 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 776 | \r |
| 777 | @param[in] Address The address that encodes the PCI Bus, Device, Function and\r |
| 778 | Register.\r |
| 779 | @param[in] AndData The value to AND with the PCI configuration register.\r |
| 780 | @param[in] OrData The value to OR with the result of the AND operation.\r |
| 781 | \r |
| 782 | @return The value written back to the PCI configuration register.\r |
| 783 | \r |
| 784 | **/\r |
| 785 | UINT32\r |
| 786 | EFIAPI\r |
| 787 | S3PciAndThenOr32 (\r |
| 788 | IN UINTN Address,\r |
| 789 | IN UINT32 AndData,\r |
| 790 | IN UINT32 OrData\r |
| 791 | );\r |
| 792 | \r |
| 793 | /**\r |
| 794 | Reads a bit field of a PCI configuration register, and saves the value in\r |
| 795 | the S3 script to be replayed on S3 resume.\r |
| 796 | \r |
| 797 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r |
| 798 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 799 | returned.\r |
| 800 | \r |
| 801 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 802 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 803 | If StartBit is greater than 31, then ASSERT().\r |
| 804 | If EndBit is greater than 31, then ASSERT().\r |
| 805 | If EndBit is less than StartBit, then ASSERT().\r |
| 806 | \r |
| 807 | @param[in] Address The PCI configuration register to read.\r |
| 808 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r |
| 809 | Range 0..31.\r |
| 810 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r |
| 811 | Range 0..31.\r |
| 812 | \r |
| 813 | @return The value of the bit field read from the PCI configuration register.\r |
| 814 | \r |
| 815 | **/\r |
| 816 | UINT32\r |
| 817 | EFIAPI\r |
| 818 | S3PciBitFieldRead32 (\r |
| 819 | IN UINTN Address,\r |
| 820 | IN UINTN StartBit,\r |
| 821 | IN UINTN EndBit\r |
| 822 | );\r |
| 823 | \r |
| 824 | /**\r |
| 825 | Writes a bit field to a PCI configuration register, and saves the value in\r |
| 826 | the S3 script to be replayed on S3 resume.\r |
| 827 | \r |
| 828 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 829 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 830 | destination PCI configuration register are preserved. The new value of the\r |
| 831 | 32-bit register is returned.\r |
| 832 | \r |
| 833 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 834 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 835 | If StartBit is greater than 31, then ASSERT().\r |
| 836 | If EndBit is greater than 31, then ASSERT().\r |
| 837 | If EndBit is less than StartBit, then ASSERT().\r |
| 838 | \r |
| 839 | @param[in] Address The PCI configuration register to write.\r |
| 840 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r |
| 841 | Range 0..31.\r |
| 842 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r |
| 843 | Range 0..31.\r |
| 844 | @param[in] Value New value of the bit field.\r |
| 845 | \r |
| 846 | @return The value written back to the PCI configuration register.\r |
| 847 | \r |
| 848 | **/\r |
| 849 | UINT32\r |
| 850 | EFIAPI\r |
| 851 | S3PciBitFieldWrite32 (\r |
| 852 | IN UINTN Address,\r |
| 853 | IN UINTN StartBit,\r |
| 854 | IN UINTN EndBit,\r |
| 855 | IN UINT32 Value\r |
| 856 | );\r |
| 857 | \r |
| 858 | /**\r |
| 859 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r |
| 860 | writes the result back to the bit field in the 32-bit port, and saves the value\r |
| 861 | in the S3 script to be replayed on S3 resume.\r |
| 862 | \r |
| 863 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 864 | bitwise OR between the read result and the value specified by\r |
| 865 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| 866 | specified by Address. The value written to the PCI configuration register is\r |
| 867 | returned. This function must guarantee that all PCI read and write operations\r |
| 868 | are serialized. Extra left bits in OrData are stripped.\r |
| 869 | \r |
| 870 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 871 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 872 | If StartBit is greater than 31, then ASSERT().\r |
| 873 | If EndBit is greater than 31, then ASSERT().\r |
| 874 | If EndBit is less than StartBit, then ASSERT().\r |
| 875 | \r |
| 876 | @param[in] Address The PCI configuration register to write.\r |
| 877 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r |
| 878 | Range 0..31.\r |
| 879 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r |
| 880 | Range 0..31.\r |
| 881 | @param[in] OrData The value to OR with the PCI configuration register.\r |
| 882 | \r |
| 883 | @return The value written back to the PCI configuration register.\r |
| 884 | \r |
| 885 | **/\r |
| 886 | UINT32\r |
| 887 | EFIAPI\r |
| 888 | S3PciBitFieldOr32 (\r |
| 889 | IN UINTN Address,\r |
| 890 | IN UINTN StartBit,\r |
| 891 | IN UINTN EndBit,\r |
| 892 | IN UINT32 OrData\r |
| 893 | );\r |
| 894 | \r |
| 895 | /**\r |
| 896 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r |
| 897 | AND, and writes the result back to the bit field in the 32-bit register and\r |
| 898 | saves the value in the S3 script to be replayed on S3 resume.\r |
| 899 | \r |
| 900 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 901 | bitwise AND between the read result and the value specified by AndData, and\r |
| 902 | writes the result to the 32-bit PCI configuration register specified by\r |
| 903 | Address. The value written to the PCI configuration register is returned.\r |
| 904 | This function must guarantee that all PCI read and write operations are\r |
| 905 | serialized. Extra left bits in AndData are stripped.\r |
| 906 | \r |
| 907 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 908 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 909 | If StartBit is greater than 31, then ASSERT().\r |
| 910 | If EndBit is greater than 31, then ASSERT().\r |
| 911 | If EndBit is less than StartBit, then ASSERT().\r |
| 912 | \r |
| 913 | @param[in] Address The PCI configuration register to write.\r |
| 914 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r |
| 915 | Range 0..31.\r |
| 916 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r |
| 917 | Range 0..31.\r |
| 918 | @param[in] AndData The value to AND with the PCI configuration register.\r |
| 919 | \r |
| 920 | @return The value written back to the PCI configuration register.\r |
| 921 | \r |
| 922 | **/\r |
| 923 | UINT32\r |
| 924 | EFIAPI\r |
| 925 | S3PciBitFieldAnd32 (\r |
| 926 | IN UINTN Address,\r |
| 927 | IN UINTN StartBit,\r |
| 928 | IN UINTN EndBit,\r |
| 929 | IN UINT32 AndData\r |
| 930 | );\r |
| 931 | \r |
| 932 | /**\r |
| 933 | Reads a bit field in a 32-bit Address, performs a bitwise AND followed by a\r |
| 934 | bitwise OR, and writes the result back to the bit field in the\r |
| 935 | 32-bit port, and saves the value in the S3 script to be replayed on S3 resume.\r |
| 936 | \r |
| 937 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 938 | bitwise AND followed by a bitwise OR between the read result and\r |
| 939 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
| 940 | configuration register specified by Address. The value written to the PCI\r |
| 941 | configuration register is returned. This function must guarantee that all PCI\r |
| 942 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 943 | OrData are stripped.\r |
| 944 | \r |
| 945 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 946 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 947 | If StartBit is greater than 31, then ASSERT().\r |
| 948 | If EndBit is greater than 31, then ASSERT().\r |
| 949 | If EndBit is less than StartBit, then ASSERT().\r |
| 950 | \r |
| 951 | @param[in] Address The PCI configuration register to write.\r |
| 952 | @param[in] StartBit The ordinal of the least significant bit in the bit field.\r |
| 953 | Range 0..31.\r |
| 954 | @param[in] EndBit The ordinal of the most significant bit in the bit field.\r |
| 955 | Range 0..31.\r |
| 956 | @param[in] AndData The value to AND with the PCI configuration register.\r |
| 957 | @param[in] OrData The value to OR with the result of the AND operation.\r |
| 958 | \r |
| 959 | @return The value written back to the PCI configuration register.\r |
| 960 | \r |
| 961 | **/\r |
| 962 | UINT32\r |
| 963 | EFIAPI\r |
| 964 | S3PciBitFieldAndThenOr32 (\r |
| 965 | IN UINTN Address,\r |
| 966 | IN UINTN StartBit,\r |
| 967 | IN UINTN EndBit,\r |
| 968 | IN UINT32 AndData,\r |
| 969 | IN UINT32 OrData\r |
| 970 | );\r |
| 971 | \r |
| 972 | /**\r |
| 973 | Reads a range of PCI configuration registers into a caller supplied buffer,\r |
| 974 | and saves the value in the S3 script to be replayed on S3 resume.\r |
| 975 | \r |
| 976 | Reads the range of PCI configuration registers specified by StartAddress and\r |
| 977 | Size into the buffer specified by Buffer. This function only allows the PCI\r |
| 978 | configuration registers from a single PCI function to be read. Size is\r |
| 979 | returned. When possible 32-bit PCI configuration read cycles are used to read\r |
| 980 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r |
| 981 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r |
| 982 | end of the range.\r |
| 983 | \r |
| 984 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
| 985 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
| 986 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| 987 | \r |
| 988 | @param[in] StartAddress Starting address that encodes the PCI Bus, Device,\r |
| 989 | Function and Register.\r |
| 990 | @param[in] Size Size in bytes of the transfer.\r |
| 991 | @param[out] Buffer The pointer to a buffer receiving the data read.\r |
| 992 | \r |
| 993 | @return Size.\r |
| 994 | \r |
| 995 | **/\r |
| 996 | UINTN\r |
| 997 | EFIAPI\r |
| 998 | S3PciReadBuffer (\r |
| 999 | IN UINTN StartAddress,\r |
| 1000 | IN UINTN Size,\r |
| 1001 | OUT VOID *Buffer\r |
| 1002 | );\r |
| 1003 | \r |
| 1004 | /**\r |
| 1005 | Copies the data in a caller supplied buffer to a specified range of PCI\r |
| 1006 | configuration space, and saves the value in the S3 script to be replayed on S3\r |
| 1007 | resume.\r |
| 1008 | \r |
| 1009 | Writes the range of PCI configuration registers specified by StartAddress and\r |
| 1010 | Size from the buffer specified by Buffer. This function only allows the PCI\r |
| 1011 | configuration registers from a single PCI function to be written. Size is\r |
| 1012 | returned. When possible 32-bit PCI configuration write cycles are used to\r |
| 1013 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r |
| 1014 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r |
| 1015 | and the end of the range.\r |
| 1016 | \r |
| 1017 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
| 1018 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
| 1019 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| 1020 | \r |
| 1021 | @param[in] StartAddress Starting address that encodes the PCI Bus, Device,\r |
| 1022 | Function and Register.\r |
| 1023 | @param[in] Size Size in bytes of the transfer.\r |
| 1024 | @param[in] Buffer The pointer to a buffer containing the data to write.\r |
| 1025 | \r |
| 1026 | @return Size.\r |
| 1027 | \r |
| 1028 | **/\r |
| 1029 | UINTN\r |
| 1030 | EFIAPI\r |
| 1031 | S3PciWriteBuffer (\r |
| 1032 | IN UINTN StartAddress,\r |
| 1033 | IN UINTN Size,\r |
| 1034 | IN VOID *Buffer\r |
| 1035 | );\r |
| 1036 | \r |
| 1037 | #endif\r |
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