[mirror_edk2.git] / MdePkg / Include / Protocol / Cpu.h

/** @file\r
  CPU Architectural Protocol as defined in PI spec Volume 2 DXE\r
\r
  This code abstracts the DXE core from processor implementation details.\r
\r
  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef __ARCH_PROTOCOL_CPU_H__\r
#define __ARCH_PROTOCOL_CPU_H__\r
\r
#include <Protocol/DebugSupport.h>\r
\r
#define EFI_CPU_ARCH_PROTOCOL_GUID \\r
  { 0x26baccb1, 0x6f42, 0x11d4, {0xbc, 0xe7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } }\r
\r
typedef struct _EFI_CPU_ARCH_PROTOCOL EFI_CPU_ARCH_PROTOCOL;\r
\r
///\r
/// The type of flush operation\r
///\r
typedef enum {\r
  EfiCpuFlushTypeWriteBackInvalidate,\r
  EfiCpuFlushTypeWriteBack,\r
  EfiCpuFlushTypeInvalidate,\r
  EfiCpuMaxFlushType\r
} EFI_CPU_FLUSH_TYPE;\r
\r
///\r
/// The type of processor INIT.\r
///\r
typedef enum {\r
  EfiCpuInit,\r
  EfiCpuMaxInitType\r
} EFI_CPU_INIT_TYPE;\r
\r
/**\r
  EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.\r
\r
  @param  InterruptType    Defines the type of interrupt or exception that\r
                           occurred on the processor.This parameter is processor architecture specific.\r
  @param  SystemContext    A pointer to the processor context when\r
                           the interrupt occurred on the processor.\r
\r
  @return None\r
\r
**/\r
typedef\r
VOID\r
(EFIAPI *EFI_CPU_INTERRUPT_HANDLER)(\r
  IN CONST  EFI_EXCEPTION_TYPE  InterruptType,\r
  IN CONST  EFI_SYSTEM_CONTEXT  SystemContext\r
  );\r
\r
/**\r
  This function flushes the range of addresses from Start to Start+Length\r
  from the processor's data cache. If Start is not aligned to a cache line\r
  boundary, then the bytes before Start to the preceding cache line boundary\r
  are also flushed. If Start+Length is not aligned to a cache line boundary,\r
  then the bytes past Start+Length to the end of the next cache line boundary\r
  are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be\r
  supported. If the data cache is fully coherent with all DMA operations, then\r
  this function can just return EFI_SUCCESS. If the processor does not support\r
  flushing a range of the data cache, then the entire data cache can be flushed.\r
\r
  @param  This             The EFI_CPU_ARCH_PROTOCOL instance.\r
  @param  Start            The beginning physical address to flush from the processor's data\r
                           cache.\r
  @param  Length           The number of bytes to flush from the processor's data cache. This\r
                           function may flush more bytes than Length specifies depending upon\r
                           the granularity of the flush operation that the processor supports.\r
  @param  FlushType        Specifies the type of flush operation to perform.\r
\r
  @retval EFI_SUCCESS           The address range from Start to Start+Length was flushed from\r
                                the processor's data cache.\r
  @retval EFI_UNSUPPORTED       The processor does not support the cache flush type specified\r
                                by FlushType.\r
  @retval EFI_DEVICE_ERROR      The address range from Start to Start+Length could not be flushed\r
                                from the processor's data cache.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_CPU_FLUSH_DATA_CACHE)(\r
  IN EFI_CPU_ARCH_PROTOCOL              *This,\r
  IN EFI_PHYSICAL_ADDRESS               Start,\r
  IN UINT64                             Length,\r
  IN EFI_CPU_FLUSH_TYPE                 FlushType\r
  );\r
\r
/**\r
  This function enables interrupt processing by the processor.\r
\r
  @param  This             The EFI_CPU_ARCH_PROTOCOL instance.\r
\r
  @retval EFI_SUCCESS           Interrupts are enabled on the processor.\r
  @retval EFI_DEVICE_ERROR      Interrupts could not be enabled on the processor.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_CPU_ENABLE_INTERRUPT)(\r
  IN EFI_CPU_ARCH_PROTOCOL              *This\r
  );\r
\r
/**\r
  This function disables interrupt processing by the processor.\r
\r
  @param  This             The EFI_CPU_ARCH_PROTOCOL instance.\r
\r
  @retval EFI_SUCCESS           Interrupts are disabled on the processor.\r
  @retval EFI_DEVICE_ERROR      Interrupts could not be disabled on the processor.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_CPU_DISABLE_INTERRUPT)(\r
  IN EFI_CPU_ARCH_PROTOCOL              *This\r
  );\r
\r
/**\r
  This function retrieves the processor's current interrupt state a returns it in\r
  State. If interrupts are currently enabled, then TRUE is returned. If interrupts\r
  are currently disabled, then FALSE is returned.\r
\r
  @param  This             The EFI_CPU_ARCH_PROTOCOL instance.\r
  @param  State            A pointer to the processor's current interrupt state. Set to TRUE if\r
                           interrupts are enabled and FALSE if interrupts are disabled.\r
\r
  @retval EFI_SUCCESS           The processor's current interrupt state was returned in State.\r
  @retval EFI_INVALID_PARAMETER State is NULL.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_CPU_GET_INTERRUPT_STATE)(\r
  IN EFI_CPU_ARCH_PROTOCOL              *This,\r
  OUT BOOLEAN                           *State\r
  );\r
\r
/**\r
  This function generates an INIT on the processor. If this function succeeds, then the\r
  processor will be reset, and control will not be returned to the caller. If InitType is\r
  not supported by this processor, or the processor cannot programmatically generate an\r
  INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error\r
  occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.\r
\r
  @param  This             The EFI_CPU_ARCH_PROTOCOL instance.\r
  @param  InitType         The type of processor INIT to perform.\r
\r
  @retval EFI_SUCCESS           The processor INIT was performed. This return code should never be seen.\r
  @retval EFI_UNSUPPORTED       The processor INIT operation specified by InitType is not supported\r
                                by this processor.\r
  @retval EFI_DEVICE_ERROR      The processor INIT failed.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_CPU_INIT)(\r
  IN EFI_CPU_ARCH_PROTOCOL              *This,\r
  IN EFI_CPU_INIT_TYPE                  InitType\r
  );\r
\r
/**\r
  This function registers and enables the handler specified by InterruptHandler for a processor\r
  interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the\r
  handler for the processor interrupt or exception type specified by InterruptType is uninstalled.\r
  The installed handler is called once for each processor interrupt or exception.\r
\r
  @param  This             The EFI_CPU_ARCH_PROTOCOL instance.\r
  @param  InterruptType    A pointer to the processor's current interrupt state. Set to TRUE if interrupts\r
                           are enabled and FALSE if interrupts are disabled.\r
  @param  InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called\r
                           when a processor interrupt occurs. If this parameter is NULL, then the handler\r
                           will be uninstalled.\r
\r
  @retval EFI_SUCCESS           The handler for the processor interrupt was successfully installed or uninstalled.\r
  @retval EFI_ALREADY_STARTED   InterruptHandler is not NULL, and a handler for InterruptType was\r
                                previously installed.\r
  @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not\r
                                previously installed.\r
  @retval EFI_UNSUPPORTED       The interrupt specified by InterruptType is not supported.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_CPU_REGISTER_INTERRUPT_HANDLER)(\r
  IN EFI_CPU_ARCH_PROTOCOL              *This,\r
  IN EFI_EXCEPTION_TYPE                 InterruptType,\r
  IN EFI_CPU_INTERRUPT_HANDLER          InterruptHandler\r
  );\r
\r
/**\r
  This function reads the processor timer specified by TimerIndex and returns it in TimerValue.\r
\r
  @param  This             The EFI_CPU_ARCH_PROTOCOL instance.\r
  @param  TimerIndex       Specifies which processor timer is to be returned in TimerValue. This parameter\r
                           must be between 0 and NumberOfTimers-1.\r
  @param  TimerValue       Pointer to the returned timer value.\r
  @param  TimerPeriod      A pointer to the amount of time that passes in femtoseconds for each increment\r
                           of TimerValue. If TimerValue does not increment at a predictable rate, then 0 is\r
                           returned. This parameter is optional and may be NULL.\r
\r
  @retval EFI_SUCCESS           The processor timer value specified by TimerIndex was returned in TimerValue.\r
  @retval EFI_DEVICE_ERROR      An error occurred attempting to read one of the processor's timers.\r
  @retval EFI_INVALID_PARAMETER TimerValue is NULL or TimerIndex is not valid.\r
  @retval EFI_UNSUPPORTED       The processor does not have any readable timers.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_CPU_GET_TIMER_VALUE)(\r
  IN EFI_CPU_ARCH_PROTOCOL              *This,\r
  IN UINT32                             TimerIndex,\r
  OUT UINT64                            *TimerValue,\r
  OUT UINT64                            *TimerPeriod OPTIONAL\r
  );\r
\r
/**\r
  This function modifies the attributes for the memory region specified by BaseAddress and\r
  Length from their current attributes to the attributes specified by Attributes.\r
\r
  @param  This             The EFI_CPU_ARCH_PROTOCOL instance.\r
  @param  BaseAddress      The physical address that is the start address of a memory region.\r
  @param  Length           The size in bytes of the memory region.\r
  @param  Attributes       The bit mask of attributes to set for the memory region.\r
\r
  @retval EFI_SUCCESS           The attributes were set for the memory region.\r
  @retval EFI_ACCESS_DENIED     The attributes for the memory resource range specified by\r
                                BaseAddress and Length cannot be modified.\r
  @retval EFI_INVALID_PARAMETER Length is zero.\r
                                Attributes specified an illegal combination of attributes that\r
                                cannot be set together.\r
  @retval EFI_OUT_OF_RESOURCES  There are not enough system resources to modify the attributes of\r
                                the memory resource range.\r
  @retval EFI_UNSUPPORTED       The processor does not support one or more bytes of the memory\r
                                resource range specified by BaseAddress and Length.\r
                                The bit mask of attributes is not support for the memory resource\r
                                range specified by BaseAddress and Length.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_CPU_SET_MEMORY_ATTRIBUTES)(\r
  IN EFI_CPU_ARCH_PROTOCOL              *This,\r
  IN  EFI_PHYSICAL_ADDRESS              BaseAddress,\r
  IN  UINT64                            Length,\r
  IN  UINT64                            Attributes\r
  );\r
\r
///\r
/// The EFI_CPU_ARCH_PROTOCOL is used to abstract processor-specific functions from the DXE\r
/// Foundation. This includes flushing caches, enabling and disabling interrupts, hooking interrupt\r
/// vectors and exception vectors, reading internal processor timers, resetting the processor, and\r
/// determining the processor frequency.\r
///\r
struct _EFI_CPU_ARCH_PROTOCOL {\r
  EFI_CPU_FLUSH_DATA_CACHE              FlushDataCache;\r
  EFI_CPU_ENABLE_INTERRUPT              EnableInterrupt;\r
  EFI_CPU_DISABLE_INTERRUPT             DisableInterrupt;\r
  EFI_CPU_GET_INTERRUPT_STATE           GetInterruptState;\r
  EFI_CPU_INIT                          Init;\r
  EFI_CPU_REGISTER_INTERRUPT_HANDLER    RegisterInterruptHandler;\r
  EFI_CPU_GET_TIMER_VALUE               GetTimerValue;\r
  EFI_CPU_SET_MEMORY_ATTRIBUTES         SetMemoryAttributes;\r
  ///\r
  /// The number of timers that are available in a processor. The value in this\r
  /// field is a constant that must not be modified after the CPU Architectural\r
  /// Protocol is installed. All consumers must treat this as a read-only field.\r
  ///\r
  UINT32                                NumberOfTimers;\r
  ///\r
  /// The size, in bytes, of the alignment required for DMA buffer allocations.\r
  /// This is typically the size of the largest data cache line in the platform.\r
  /// The value in this field is a constant that must not be modified after the\r
  /// CPU Architectural Protocol is installed. All consumers must treat this as\r
  /// a read-only field.\r
  ///\r
  UINT32                                DmaBufferAlignment;\r
};\r
\r
extern EFI_GUID  gEfiCpuArchProtocolGuid;\r
\r
#endif\r
Commit	Line	Data
d1f95000	1	/** @file\r
4ca9b6c4	2	CPU Architectural Protocol as defined in PI spec Volume 2 DXE\r
d1f95000	3	\r
	4	This code abstracts the DXE core from processor implementation details.\r
	5	\r
9095d37b	6	Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
9344f092	7	SPDX-License-Identifier: BSD-2-Clause-Patent\r
d1f95000	8	\r
d1f95000	9	**/\r
	10	\r
	11	#ifndef __ARCH_PROTOCOL_CPU_H__\r
	12	#define __ARCH_PROTOCOL_CPU_H__\r
	13	\r
	14	#include <Protocol/DebugSupport.h>\r
	15	\r
	16	#define EFI_CPU_ARCH_PROTOCOL_GUID \\r
	17	{ 0x26baccb1, 0x6f42, 0x11d4, {0xbc, 0xe7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } }\r
	18	\r
2f88bd3a	19	typedef struct _EFI_CPU_ARCH_PROTOCOL EFI_CPU_ARCH_PROTOCOL;\r
d1f95000	20	\r
9319d2c2 LG	21	///\r
	22	/// The type of flush operation\r
	23	///\r
d1f95000	24	typedef enum {\r
	25	EfiCpuFlushTypeWriteBackInvalidate,\r
	26	EfiCpuFlushTypeWriteBack,\r
	27	EfiCpuFlushTypeInvalidate,\r
	28	EfiCpuMaxFlushType\r
	29	} EFI_CPU_FLUSH_TYPE;\r
	30	\r
9319d2c2 LG	31	///\r
	32	/// The type of processor INIT.\r
	33	///\r
d1f95000	34	typedef enum {\r
	35	EfiCpuInit,\r
	36	EfiCpuMaxInitType\r
	37	} EFI_CPU_INIT_TYPE;\r
	38	\r
	39	/**\r
	40	EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs.\r
	41	\r
	42	@param InterruptType Defines the type of interrupt or exception that\r
	43	occurred on the processor.This parameter is processor architecture specific.\r
	44	@param SystemContext A pointer to the processor context when\r
	45	the interrupt occurred on the processor.\r
	46	\r
	47	@return None\r
	48	\r
	49	**/\r
	50	typedef\r
	51	VOID\r
8b13229b	52	(EFIAPI *EFI_CPU_INTERRUPT_HANDLER)(\r
d1f95000	53	IN CONST EFI_EXCEPTION_TYPE InterruptType,\r
	54	IN CONST EFI_SYSTEM_CONTEXT SystemContext\r
	55	);\r
	56	\r
	57	/**\r
9095d37b LG	58	This function flushes the range of addresses from Start to Start+Length\r
	59	from the processor's data cache. If Start is not aligned to a cache line\r
	60	boundary, then the bytes before Start to the preceding cache line boundary\r
	61	are also flushed. If Start+Length is not aligned to a cache line boundary,\r
	62	then the bytes past Start+Length to the end of the next cache line boundary\r
	63	are also flushed. The FlushType of EfiCpuFlushTypeWriteBackInvalidate must be\r
	64	supported. If the data cache is fully coherent with all DMA operations, then\r
	65	this function can just return EFI_SUCCESS. If the processor does not support\r
d1f95000	66	flushing a range of the data cache, then the entire data cache can be flushed.\r
	67	\r
	68	@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
	69	@param Start The beginning physical address to flush from the processor's data\r
	70	cache.\r
	71	@param Length The number of bytes to flush from the processor's data cache. This\r
	72	function may flush more bytes than Length specifies depending upon\r
	73	the granularity of the flush operation that the processor supports.\r
	74	@param FlushType Specifies the type of flush operation to perform.\r
	75	\r
	76	@retval EFI_SUCCESS The address range from Start to Start+Length was flushed from\r
	77	the processor's data cache.\r
b88df761	78	@retval EFI_UNSUPPORTED The processor does not support the cache flush type specified\r
d1f95000	79	by FlushType.\r
	80	@retval EFI_DEVICE_ERROR The address range from Start to Start+Length could not be flushed\r
	81	from the processor's data cache.\r
	82	\r
	83	**/\r
	84	typedef\r
	85	EFI_STATUS\r
8b13229b	86	(EFIAPI *EFI_CPU_FLUSH_DATA_CACHE)(\r
d1f95000	87	IN EFI_CPU_ARCH_PROTOCOL *This,\r
	88	IN EFI_PHYSICAL_ADDRESS Start,\r
	89	IN UINT64 Length,\r
	90	IN EFI_CPU_FLUSH_TYPE FlushType\r
	91	);\r
	92	\r
d1f95000	93	/**\r
9095d37b	94	This function enables interrupt processing by the processor.\r
d1f95000	95	\r
	96	@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
	97	\r
	98	@retval EFI_SUCCESS Interrupts are enabled on the processor.\r
	99	@retval EFI_DEVICE_ERROR Interrupts could not be enabled on the processor.\r
	100	\r
	101	**/\r
	102	typedef\r
	103	EFI_STATUS\r
8b13229b	104	(EFIAPI *EFI_CPU_ENABLE_INTERRUPT)(\r
d1f95000	105	IN EFI_CPU_ARCH_PROTOCOL *This\r
	106	);\r
	107	\r
d1f95000	108	/**\r
	109	This function disables interrupt processing by the processor.\r
	110	\r
	111	@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
	112	\r
	113	@retval EFI_SUCCESS Interrupts are disabled on the processor.\r
	114	@retval EFI_DEVICE_ERROR Interrupts could not be disabled on the processor.\r
	115	\r
	116	**/\r
	117	typedef\r
	118	EFI_STATUS\r
8b13229b	119	(EFIAPI *EFI_CPU_DISABLE_INTERRUPT)(\r
d1f95000	120	IN EFI_CPU_ARCH_PROTOCOL *This\r
	121	);\r
	122	\r
d1f95000	123	/**\r
9095d37b LG	124	This function retrieves the processor's current interrupt state a returns it in\r
9095d37b LG	125	State. If interrupts are currently enabled, then TRUE is returned. If interrupts\r
d1f95000	126	are currently disabled, then FALSE is returned.\r
	127	\r
	128	@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
	129	@param State A pointer to the processor's current interrupt state. Set to TRUE if\r
	130	interrupts are enabled and FALSE if interrupts are disabled.\r
	131	\r
	132	@retval EFI_SUCCESS The processor's current interrupt state was returned in State.\r
	133	@retval EFI_INVALID_PARAMETER State is NULL.\r
	134	\r
	135	**/\r
	136	typedef\r
	137	EFI_STATUS\r
8b13229b	138	(EFIAPI *EFI_CPU_GET_INTERRUPT_STATE)(\r
d1f95000	139	IN EFI_CPU_ARCH_PROTOCOL *This,\r
	140	OUT BOOLEAN *State\r
	141	);\r
	142	\r
d1f95000	143	/**\r
d1f95000	144	This function generates an INIT on the processor. If this function succeeds, then the\r
9095d37b LG	145	processor will be reset, and control will not be returned to the caller. If InitType is\r
	146	not supported by this processor, or the processor cannot programmatically generate an\r
	147	INIT without help from external hardware, then EFI_UNSUPPORTED is returned. If an error\r
d1f95000	148	occurs attempting to generate an INIT, then EFI_DEVICE_ERROR is returned.\r
	149	\r
	150	@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
	151	@param InitType The type of processor INIT to perform.\r
	152	\r
	153	@retval EFI_SUCCESS The processor INIT was performed. This return code should never be seen.\r
	154	@retval EFI_UNSUPPORTED The processor INIT operation specified by InitType is not supported\r
	155	by this processor.\r
	156	@retval EFI_DEVICE_ERROR The processor INIT failed.\r
	157	\r
	158	**/\r
	159	typedef\r
	160	EFI_STATUS\r
8b13229b	161	(EFIAPI *EFI_CPU_INIT)(\r
d1f95000	162	IN EFI_CPU_ARCH_PROTOCOL *This,\r
	163	IN EFI_CPU_INIT_TYPE InitType\r
	164	);\r
	165	\r
d1f95000	166	/**\r
9095d37b LG	167	This function registers and enables the handler specified by InterruptHandler for a processor\r
	168	interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the\r
	169	handler for the processor interrupt or exception type specified by InterruptType is uninstalled.\r
d1f95000	170	The installed handler is called once for each processor interrupt or exception.\r
	171	\r
	172	@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
	173	@param InterruptType A pointer to the processor's current interrupt state. Set to TRUE if interrupts\r
	174	are enabled and FALSE if interrupts are disabled.\r
	175	@param InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called\r
	176	when a processor interrupt occurs. If this parameter is NULL, then the handler\r
	177	will be uninstalled.\r
	178	\r
	179	@retval EFI_SUCCESS The handler for the processor interrupt was successfully installed or uninstalled.\r
	180	@retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handler for InterruptType was\r
	181	previously installed.\r
	182	@retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not\r
	183	previously installed.\r
	184	@retval EFI_UNSUPPORTED The interrupt specified by InterruptType is not supported.\r
	185	\r
	186	**/\r
	187	typedef\r
	188	EFI_STATUS\r
8b13229b	189	(EFIAPI *EFI_CPU_REGISTER_INTERRUPT_HANDLER)(\r
d1f95000	190	IN EFI_CPU_ARCH_PROTOCOL *This,\r
	191	IN EFI_EXCEPTION_TYPE InterruptType,\r
	192	IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler\r
	193	);\r
	194	\r
d1f95000	195	/**\r
	196	This function reads the processor timer specified by TimerIndex and returns it in TimerValue.\r
	197	\r
	198	@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
	199	@param TimerIndex Specifies which processor timer is to be returned in TimerValue. This parameter\r
	200	must be between 0 and NumberOfTimers-1.\r
	201	@param TimerValue Pointer to the returned timer value.\r
	202	@param TimerPeriod A pointer to the amount of time that passes in femtoseconds for each increment\r
f1004231 LG	203	of TimerValue. If TimerValue does not increment at a predictable rate, then 0 is\r
f1004231 LG	204	returned. This parameter is optional and may be NULL.\r
d1f95000	205	\r
	206	@retval EFI_SUCCESS The processor timer value specified by TimerIndex was returned in TimerValue.\r
	207	@retval EFI_DEVICE_ERROR An error occurred attempting to read one of the processor's timers.\r
	208	@retval EFI_INVALID_PARAMETER TimerValue is NULL or TimerIndex is not valid.\r
	209	@retval EFI_UNSUPPORTED The processor does not have any readable timers.\r
	210	\r
	211	**/\r
	212	typedef\r
	213	EFI_STATUS\r
8b13229b	214	(EFIAPI *EFI_CPU_GET_TIMER_VALUE)(\r
d1f95000	215	IN EFI_CPU_ARCH_PROTOCOL *This,\r
	216	IN UINT32 TimerIndex,\r
	217	OUT UINT64 *TimerValue,\r
	218	OUT UINT64 *TimerPeriod OPTIONAL\r
	219	);\r
	220	\r
d1f95000	221	/**\r
	222	This function modifies the attributes for the memory region specified by BaseAddress and\r
	223	Length from their current attributes to the attributes specified by Attributes.\r
	224	\r
	225	@param This The EFI_CPU_ARCH_PROTOCOL instance.\r
	226	@param BaseAddress The physical address that is the start address of a memory region.\r
	227	@param Length The size in bytes of the memory region.\r
	228	@param Attributes The bit mask of attributes to set for the memory region.\r
	229	\r
	230	@retval EFI_SUCCESS The attributes were set for the memory region.\r
	231	@retval EFI_ACCESS_DENIED The attributes for the memory resource range specified by\r
	232	BaseAddress and Length cannot be modified.\r
	233	@retval EFI_INVALID_PARAMETER Length is zero.\r
4ec21e8b	234	Attributes specified an illegal combination of attributes that\r
4ec21e8b	235	cannot be set together.\r
d1f95000	236	@retval EFI_OUT_OF_RESOURCES There are not enough system resources to modify the attributes of\r
	237	the memory resource range.\r
	238	@retval EFI_UNSUPPORTED The processor does not support one or more bytes of the memory\r
	239	resource range specified by BaseAddress and Length.\r
	240	The bit mask of attributes is not support for the memory resource\r
	241	range specified by BaseAddress and Length.\r
	242	\r
	243	**/\r
	244	typedef\r
	245	EFI_STATUS\r
8b13229b	246	(EFIAPI *EFI_CPU_SET_MEMORY_ATTRIBUTES)(\r
d1f95000	247	IN EFI_CPU_ARCH_PROTOCOL *This,\r
	248	IN EFI_PHYSICAL_ADDRESS BaseAddress,\r
	249	IN UINT64 Length,\r
	250	IN UINT64 Attributes\r
	251	);\r
	252	\r
44717a39	253	///\r
	254	/// The EFI_CPU_ARCH_PROTOCOL is used to abstract processor-specific functions from the DXE\r
	255	/// Foundation. This includes flushing caches, enabling and disabling interrupts, hooking interrupt\r
	256	/// vectors and exception vectors, reading internal processor timers, resetting the processor, and\r
	257	/// determining the processor frequency.\r
	258	///\r
d1f95000	259	struct _EFI_CPU_ARCH_PROTOCOL {\r
2f88bd3a MK	260	EFI_CPU_FLUSH_DATA_CACHE FlushDataCache;\r
	261	EFI_CPU_ENABLE_INTERRUPT EnableInterrupt;\r
	262	EFI_CPU_DISABLE_INTERRUPT DisableInterrupt;\r
	263	EFI_CPU_GET_INTERRUPT_STATE GetInterruptState;\r
	264	EFI_CPU_INIT Init;\r
	265	EFI_CPU_REGISTER_INTERRUPT_HANDLER RegisterInterruptHandler;\r
	266	EFI_CPU_GET_TIMER_VALUE GetTimerValue;\r
	267	EFI_CPU_SET_MEMORY_ATTRIBUTES SetMemoryAttributes;\r
8b6c989b	268	///\r
9095d37b LG	269	/// The number of timers that are available in a processor. The value in this\r
9095d37b LG	270	/// field is a constant that must not be modified after the CPU Architectural\r
8b6c989b	271	/// Protocol is installed. All consumers must treat this as a read-only field.\r
8b6c989b	272	///\r
2f88bd3a	273	UINT32 NumberOfTimers;\r
8b6c989b	274	///\r
9095d37b LG	275	/// The size, in bytes, of the alignment required for DMA buffer allocations.\r
	276	/// This is typically the size of the largest data cache line in the platform.\r
	277	/// The value in this field is a constant that must not be modified after the\r
	278	/// CPU Architectural Protocol is installed. All consumers must treat this as\r
	279	/// a read-only field.\r
8b6c989b	280	///\r
2f88bd3a	281	UINT32 DmaBufferAlignment;\r
d1f95000	282	};\r
d1f95000	283	\r
2f88bd3a	284	extern EFI_GUID gEfiCpuArchProtocolGuid;\r
d1f95000	285	\r
d1f95000	286	#endif\r