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25a1f91d | 1 | /** @file\r |
2 | This files describes the CPU I/O 2 Protocol.\r | |
9095d37b | 3 | \r |
25a1f91d | 4 | This protocol provides an I/O abstraction for a system processor. This protocol\r |
5 | is used by a PCI root bridge I/O driver to perform memory-mapped I/O and I/O transactions.\r | |
6 | The I/O or memory primitives can be used by the consumer of the protocol to materialize\r | |
7 | bus-specific configuration cycles, such as the transitional configuration address and data\r | |
9095d37b LG |
8 | ports for PCI. Only drivers that require direct access to the entire system should use this\r |
9 | protocol.\r | |
10 | \r | |
25a1f91d | 11 | Note: This is a boot-services only protocol and it may not be used by runtime drivers after\r |
12 | ExitBootServices(). It is different from the Framework CPU I/O Protocol, which is a runtime\r | |
13 | protocol and can be used by runtime drivers after ExitBootServices().\r | |
14 | \r | |
9095d37b | 15 | Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r |
9344f092 | 16 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
25a1f91d | 17 | \r |
18 | @par Revision Reference:\r | |
9095d37b | 19 | This Protocol is defined in UEFI Platform Initialization Specification 1.2\r |
25a1f91d | 20 | Volume 5: Standards\r |
21 | \r | |
22 | **/\r | |
23 | \r | |
24 | #ifndef __CPU_IO2_H__\r | |
25 | #define __CPU_IO2_H__\r | |
26 | \r | |
25a1f91d | 27 | #define EFI_CPU_IO2_PROTOCOL_GUID \\r |
28 | { \\r | |
29 | 0xad61f191, 0xae5f, 0x4c0e, {0xb9, 0xfa, 0xe8, 0x69, 0xd2, 0x88, 0xc6, 0x4f} \\r | |
30 | }\r | |
31 | \r | |
32 | typedef struct _EFI_CPU_IO2_PROTOCOL EFI_CPU_IO2_PROTOCOL;\r | |
33 | \r | |
25a1f91d | 34 | ///\r |
35 | /// Enumeration that defines the width of the I/O operation.\r | |
36 | ///\r | |
37 | typedef enum {\r | |
38 | EfiCpuIoWidthUint8,\r | |
39 | EfiCpuIoWidthUint16,\r | |
40 | EfiCpuIoWidthUint32,\r | |
41 | EfiCpuIoWidthUint64,\r | |
42 | EfiCpuIoWidthFifoUint8,\r | |
43 | EfiCpuIoWidthFifoUint16,\r | |
44 | EfiCpuIoWidthFifoUint32,\r | |
45 | EfiCpuIoWidthFifoUint64,\r | |
46 | EfiCpuIoWidthFillUint8,\r | |
47 | EfiCpuIoWidthFillUint16,\r | |
48 | EfiCpuIoWidthFillUint32,\r | |
49 | EfiCpuIoWidthFillUint64,\r | |
50 | EfiCpuIoWidthMaximum\r | |
51 | } EFI_CPU_IO_PROTOCOL_WIDTH;\r | |
52 | \r | |
25a1f91d | 53 | /**\r |
9095d37b | 54 | Enables a driver to access registers in the PI CPU I/O space.\r |
25a1f91d | 55 | \r |
9095d37b LG |
56 | The Io.Read() and Io.Write() functions enable a driver to access PCI controller\r |
57 | registers in the PI CPU I/O space.\r | |
25a1f91d | 58 | \r |
9095d37b LG |
59 | The I/O operations are carried out exactly as requested. The caller is responsible\r |
60 | for satisfying any alignment and I/O width restrictions that a PI System on a\r | |
61 | platform might require. For example on some platforms, width requests of\r | |
62 | EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will\r | |
0b70a697 | 63 | be handled by the driver.\r |
9095d37b LG |
64 | \r |
65 | If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32,\r | |
66 | or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for\r | |
0b70a697 | 67 | each of the Count operations that is performed.\r |
9095d37b LG |
68 | \r |
69 | If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16,\r | |
70 | EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is\r | |
71 | incremented for each of the Count operations that is performed. The read or\r | |
0b70a697 | 72 | write operation is performed Count times on the same Address.\r |
9095d37b LG |
73 | \r |
74 | If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16,\r | |
75 | EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is\r | |
76 | incremented for each of the Count operations that is performed. The read or\r | |
0b70a697 | 77 | write operation is performed Count times from the first element of Buffer.\r |
25a1f91d | 78 | \r |
0b70a697 | 79 | @param[in] This A pointer to the EFI_CPU_IO2_PROTOCOL instance.\r |
80 | @param[in] Width Signifies the width of the I/O or Memory operation.\r | |
9095d37b LG |
81 | @param[in] Address The base address of the I/O operation.\r |
82 | @param[in] Count The number of I/O operations to perform. The number\r | |
0b70a697 | 83 | of bytes moved is Width size * Count, starting at Address.\r |
84 | @param[in, out] Buffer For read operations, the destination buffer to store the results.\r | |
85 | For write operations, the source buffer from which to write data.\r | |
25a1f91d | 86 | \r |
0b70a697 | 87 | @retval EFI_SUCCESS The data was read from or written to the PI system.\r |
88 | @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.\r | |
89 | @retval EFI_INVALID_PARAMETER Buffer is NULL.\r | |
90 | @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.\r | |
9095d37b | 91 | @retval EFI_UNSUPPORTED The address range specified by Address, Width,\r |
0b70a697 | 92 | and Count is not valid for this PI system.\r |
25a1f91d | 93 | \r |
94 | **/\r | |
95 | typedef\r | |
96 | EFI_STATUS\r | |
97 | (EFIAPI *EFI_CPU_IO_PROTOCOL_IO_MEM)(\r | |
98 | IN EFI_CPU_IO2_PROTOCOL *This,\r | |
99 | IN EFI_CPU_IO_PROTOCOL_WIDTH Width,\r | |
100 | IN UINT64 Address,\r | |
101 | IN UINTN Count,\r | |
102 | IN OUT VOID *Buffer\r | |
103 | );\r | |
104 | \r | |
25a1f91d | 105 | ///\r |
106 | /// Service for read and write accesses.\r | |
107 | ///\r | |
108 | typedef struct {\r | |
109 | ///\r | |
110 | /// This service provides the various modalities of memory and I/O read.\r | |
111 | ///\r | |
2f88bd3a | 112 | EFI_CPU_IO_PROTOCOL_IO_MEM Read;\r |
25a1f91d | 113 | ///\r |
114 | /// This service provides the various modalities of memory and I/O write.\r | |
115 | ///\r | |
2f88bd3a | 116 | EFI_CPU_IO_PROTOCOL_IO_MEM Write;\r |
25a1f91d | 117 | } EFI_CPU_IO_PROTOCOL_ACCESS;\r |
118 | \r | |
25a1f91d | 119 | ///\r |
120 | /// Provides the basic memory and I/O interfaces that are used to abstract\r | |
121 | /// accesses to devices in a system.\r | |
122 | ///\r | |
123 | struct _EFI_CPU_IO2_PROTOCOL {\r | |
124 | ///\r | |
125 | /// Enables a driver to access memory-mapped registers in the EFI system memory space.\r | |
126 | ///\r | |
2f88bd3a | 127 | EFI_CPU_IO_PROTOCOL_ACCESS Mem;\r |
25a1f91d | 128 | ///\r |
129 | /// Enables a driver to access registers in the EFI CPU I/O space.\r | |
130 | ///\r | |
2f88bd3a | 131 | EFI_CPU_IO_PROTOCOL_ACCESS Io;\r |
25a1f91d | 132 | };\r |
133 | \r | |
2f88bd3a | 134 | extern EFI_GUID gEfiCpuIo2ProtocolGuid;\r |
25a1f91d | 135 | \r |
136 | #endif\r |