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1 | /** @file\r |
2 | I2C Host Protocol as defined in the PI 1.3 specification.\r | |
3 | \r | |
9095d37b | 4 | This protocol provides callers with the ability to do I/O transactions\r |
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5 | to all of the devices on the I2C bus.\r |
6 | \r | |
9095d37b | 7 | Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.<BR>\r |
9344f092 | 8 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
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9 | \r |
10 | @par Revision Reference:\r | |
11 | This protocol is from PI Version 1.3.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | #ifndef __I2C_HOST_H__\r | |
16 | #define __I2C_HOST_H__\r | |
17 | \r | |
18 | #include <Pi/PiI2c.h>\r | |
19 | \r | |
20 | #define EFI_I2C_HOST_PROTOCOL_GUID { 0xa5aab9e3, 0xc727, 0x48cd, { 0x8b, 0xbf, 0x42, 0x72, 0x33, 0x85, 0x49, 0x48 }}\r | |
21 | \r | |
22 | ///\r | |
23 | /// I2C Host Protocol\r | |
24 | ///\r | |
25 | /// The I2C bus driver uses the services of the EFI_I2C_HOST_PROTOCOL\r | |
26 | /// to produce an instance of the EFI_I2C_IO_PROTOCOL for each I2C\r | |
27 | /// device on an I2C bus.\r | |
28 | ///\r | |
29 | /// The EFI_I2C_HOST_PROTOCOL exposes an asynchronous interface to\r | |
30 | /// callers to perform transactions to any device on the I2C bus.\r | |
31 | /// Internally, the I2C host protocol manages the flow of the I2C\r | |
32 | /// transactions to the host controller, keeping them in FIFO order.\r | |
33 | /// Prior to each transaction, the I2C host protocol ensures that the\r | |
34 | /// switches and multiplexers are properly configured. The I2C host\r | |
35 | /// protocol then starts the transaction on the host controller using\r | |
36 | /// the EFI_I2C_MASTER_PROTOCOL.\r | |
37 | ///\r | |
38 | typedef struct _EFI_I2C_HOST_PROTOCOL EFI_I2C_HOST_PROTOCOL;\r | |
39 | \r | |
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40 | /**\r |
41 | Queue an I2C transaction for execution on the I2C controller.\r | |
42 | \r | |
43 | This routine must be called at or below TPL_NOTIFY. For\r | |
44 | synchronous requests this routine must be called at or below\r | |
45 | TPL_CALLBACK.\r | |
9095d37b | 46 | \r |
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47 | The I2C host protocol uses the concept of I2C bus configurations\r |
48 | to describe the I2C bus. An I2C bus configuration is defined as\r | |
49 | a unique setting of the multiplexers and switches in the I2C bus\r | |
50 | which enable access to one or more I2C devices. When using a\r | |
51 | switch to divide a bus, due to bus frequency differences, the\r | |
52 | I2C bus configuration management protocol defines an I2C bus\r | |
53 | configuration for the I2C devices on each side of the switch.\r | |
54 | When using a multiplexer, the I2C bus configuration management\r | |
55 | defines an I2C bus configuration for each of the selector values\r | |
56 | required to control the multiplexer. See Figure 1 in the I2C -bus\r | |
57 | specification and user manual for a complex I2C bus configuration.\r | |
58 | \r | |
59 | The I2C host protocol processes all transactions in FIFO order.\r | |
60 | Prior to performing the transaction, the I2C host protocol calls\r | |
61 | EnableI2cBusConfiguration to reconfigure the switches and\r | |
62 | multiplexers in the I2C bus enabling access to the specified I2C\r | |
63 | device. The EnableI2cBusConfiguration also selects the I2C bus\r | |
64 | frequency for the I2C device. After the I2C bus is configured,\r | |
65 | the I2C host protocol calls the I2C master protocol to start the\r | |
66 | I2C transaction.\r | |
67 | \r | |
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68 | When Event is NULL, QueueRequest() operates synchronously and\r |
69 | returns the I2C completion status as its return value.\r | |
70 | \r | |
71 | When Event is not NULL, QueueRequest() synchronously returns\r | |
72 | EFI_SUCCESS indicating that the asynchronously I2C transaction was\r | |
73 | queued. The values above are returned in the buffer pointed to by\r | |
74 | I2cStatus upon the completion of the I2C transaction when I2cStatus\r | |
75 | is not NULL.\r | |
76 | \r | |
77 | @param[in] This Pointer to an EFI_I2C_HOST_PROTOCOL structure.\r | |
78 | @param[in] I2cBusConfiguration I2C bus configuration to access the I2C\r | |
79 | device\r | |
80 | @param[in] SlaveAddress Address of the device on the I2C bus. Set\r | |
81 | the I2C_ADDRESSING_10_BIT when using 10-bit\r | |
82 | addresses, clear this bit for 7-bit addressing.\r | |
83 | Bits 0-6 are used for 7-bit I2C slave addresses\r | |
84 | and bits 0-9 are used for 10-bit I2C slave\r | |
85 | addresses.\r | |
86 | @param[in] Event Event to signal for asynchronous transactions,\r | |
87 | NULL for synchronous transactions\r | |
88 | @param[in] RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET structure\r | |
89 | describing the I2C transaction\r | |
90 | @param[out] I2cStatus Optional buffer to receive the I2C transaction\r | |
91 | completion status\r | |
92 | \r | |
93 | @retval EFI_SUCCESS The asynchronous transaction was successfully\r | |
94 | queued when Event is not NULL.\r | |
95 | @retval EFI_SUCCESS The transaction completed successfully when\r | |
96 | Event is NULL.\r | |
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97 | @retval EFI_BAD_BUFFER_SIZE The RequestPacket->LengthInBytes value is\r |
98 | too large.\r | |
99 | @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the\r | |
100 | transaction.\r | |
101 | @retval EFI_INVALID_PARAMETER RequestPacket is NULL\r | |
102 | @retval EFI_NOT_FOUND Reserved bit set in the SlaveAddress parameter\r | |
103 | @retval EFI_NO_MAPPING Invalid I2cBusConfiguration value\r | |
104 | @retval EFI_NO_RESPONSE The I2C device is not responding to the slave\r | |
105 | address. EFI_DEVICE_ERROR will be returned\r | |
106 | if the controller cannot distinguish when the\r | |
107 | NACK occurred.\r | |
108 | @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C transaction\r | |
109 | @retval EFI_UNSUPPORTED The controller does not support the requested\r | |
110 | transaction.\r | |
111 | \r | |
112 | **/\r | |
113 | typedef\r | |
114 | EFI_STATUS\r | |
2f88bd3a | 115 | (EFIAPI *EFI_I2C_HOST_PROTOCOL_QUEUE_REQUEST)(\r |
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116 | IN CONST EFI_I2C_HOST_PROTOCOL *This,\r |
117 | IN UINTN I2cBusConfiguration,\r | |
118 | IN UINTN SlaveAddress,\r | |
119 | IN EFI_EVENT Event OPTIONAL,\r | |
120 | IN EFI_I2C_REQUEST_PACKET *RequestPacket,\r | |
121 | OUT EFI_STATUS *I2cStatus OPTIONAL\r | |
122 | );\r | |
123 | \r | |
124 | ///\r | |
125 | /// I2C Host Protocol\r | |
126 | ///\r | |
127 | struct _EFI_I2C_HOST_PROTOCOL {\r | |
128 | ///\r | |
129 | /// Queue an I2C transaction for execution on the I2C bus\r | |
130 | ///\r | |
2f88bd3a | 131 | EFI_I2C_HOST_PROTOCOL_QUEUE_REQUEST QueueRequest;\r |
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132 | \r |
133 | ///\r | |
134 | /// Pointer to an EFI_I2C_CONTROLLER_CAPABILITIES data structure\r | |
135 | /// containing the capabilities of the I2C host controller.\r | |
136 | ///\r | |
2f88bd3a | 137 | CONST EFI_I2C_CONTROLLER_CAPABILITIES *I2cControllerCapabilities;\r |
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138 | };\r |
139 | \r | |
140 | ///\r | |
141 | /// Reference to variable defined in the .DEC file\r | |
142 | ///\r | |
2f88bd3a | 143 | extern EFI_GUID gEfiI2cHostProtocolGuid;\r |
4006b0b5 | 144 | \r |
2f88bd3a | 145 | #endif // __I2C_HOST_H__\r |