[mirror_edk2.git] / MdePkg / Include / Protocol / PciIo.h

/** @file\r
  EFI PCI I/O Protocol provides the basic Memory, I/O, PCI configuration,\r
  and DMA interfaces that a driver uses to access its PCI controller.\r
\r
  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef __PCI_IO_H__\r
#define __PCI_IO_H__\r
\r
///\r
/// Global ID for the PCI I/O Protocol\r
///\r
#define EFI_PCI_IO_PROTOCOL_GUID \\r
  { \\r
    0x4cf5b200, 0x68b8, 0x4ca5, {0x9e, 0xec, 0xb2, 0x3e, 0x3f, 0x50, 0x2, 0x9a } \\r
  }\r
\r
typedef struct _EFI_PCI_IO_PROTOCOL  EFI_PCI_IO_PROTOCOL;\r
\r
///\r
/// *******************************************************\r
/// EFI_PCI_IO_PROTOCOL_WIDTH\r
/// *******************************************************\r
///\r
typedef enum {\r
  EfiPciIoWidthUint8      = 0,\r
  EfiPciIoWidthUint16,\r
  EfiPciIoWidthUint32,\r
  EfiPciIoWidthUint64,\r
  EfiPciIoWidthFifoUint8,\r
  EfiPciIoWidthFifoUint16,\r
  EfiPciIoWidthFifoUint32,\r
  EfiPciIoWidthFifoUint64,\r
  EfiPciIoWidthFillUint8,\r
  EfiPciIoWidthFillUint16,\r
  EfiPciIoWidthFillUint32,\r
  EfiPciIoWidthFillUint64,\r
  EfiPciIoWidthMaximum\r
} EFI_PCI_IO_PROTOCOL_WIDTH;\r
\r
//\r
// Complete PCI address generater\r
//\r
#define EFI_PCI_IO_PASS_THROUGH_BAR               0xff    ///< Special BAR that passes a memory or I/O cycle through unchanged\r
#define EFI_PCI_IO_ATTRIBUTE_MASK                 0x077f  ///< All the following I/O and Memory cycles\r
#define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO   0x0001  ///< I/O cycles 0x0000-0x00FF (10 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_ISA_IO               0x0002  ///< I/O cycles 0x0100-0x03FF or greater (10 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO       0x0004  ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (10 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY           0x0008  ///< MEM cycles 0xA0000-0xBFFFF (24 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_VGA_IO               0x0010  ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO       0x0020  ///< I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO     0x0040  ///< I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080  ///< Map a memory range so writes are combined\r
#define EFI_PCI_IO_ATTRIBUTE_IO                   0x0100  ///< Enable the I/O decode bit in the PCI Config Header\r
#define EFI_PCI_IO_ATTRIBUTE_MEMORY               0x0200  ///< Enable the Memory decode bit in the PCI Config Header\r
#define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER           0x0400  ///< Enable the DMA bit in the PCI Config Header\r
#define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED        0x0800  ///< Map a memory range so all r/w accesses are cached\r
#define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE       0x1000  ///< Disable a memory range\r
#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE      0x2000  ///< Clear for an add-in PCI Device\r
#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM         0x4000  ///< Clear for a physical PCI Option ROM accessed through ROM BAR\r
#define EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE   0x8000  ///< Clear for PCI controllers that can not genrate a DAC\r
#define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16            0x10000 ///< I/O cycles 0x0100-0x03FF or greater (16 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16    0x20000 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (16 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16            0x40000 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode)\r
\r
#define EFI_PCI_DEVICE_ENABLE                     (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER)\r
#define EFI_VGA_DEVICE_ENABLE                     (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY | EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_IO)\r
\r
///\r
/// *******************************************************\r
/// EFI_PCI_IO_PROTOCOL_OPERATION\r
/// *******************************************************\r
///\r
typedef enum {\r
  ///\r
  /// A read operation from system memory by a bus master.\r
  ///\r
  EfiPciIoOperationBusMasterRead,\r
  ///\r
  /// A write operation from system memory by a bus master.\r
  ///\r
  EfiPciIoOperationBusMasterWrite,\r
  ///\r
  /// Provides both read and write access to system memory by both the processor and a\r
  /// bus master. The buffer is coherent from both the processor's and the bus master's point of view.\r
  ///\r
  EfiPciIoOperationBusMasterCommonBuffer,\r
  EfiPciIoOperationMaximum\r
} EFI_PCI_IO_PROTOCOL_OPERATION;\r
\r
///\r
/// *******************************************************\r
/// EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION\r
/// *******************************************************\r
///\r
typedef enum {\r
  ///\r
  /// Retrieve the PCI controller's current attributes, and return them in Result.\r
  ///\r
  EfiPciIoAttributeOperationGet,\r
  ///\r
  /// Set the PCI controller's current attributes to Attributes.\r
  ///\r
  EfiPciIoAttributeOperationSet,\r
  ///\r
  /// Enable the attributes specified by the bits that are set in Attributes for this PCI controller.\r
  ///\r
  EfiPciIoAttributeOperationEnable,\r
  ///\r
  /// Disable the attributes specified by the bits that are set in Attributes for this PCI controller.\r
  ///\r
  EfiPciIoAttributeOperationDisable,\r
  ///\r
  /// Retrieve the PCI controller's supported attributes, and return them in Result.\r
  ///\r
  EfiPciIoAttributeOperationSupported,\r
  EfiPciIoAttributeOperationMaximum\r
} EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION;\r
\r
/**\r
  Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is\r
  satisfied or after a defined duration.\r
\r
  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
  @param  Width                 Signifies the width of the memory or I/O operations.\r
  @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the\r
                                base address for the memory operation to perform.\r
  @param  Offset                The offset within the selected BAR to start the memory operation.\r
  @param  Mask                  Mask used for the polling criteria.\r
  @param  Value                 The comparison value used for the polling exit criteria.\r
  @param  Delay                 The number of 100 ns units to poll.\r
  @param  Result                Pointer to the last value read from the memory location.\r
\r
  @retval EFI_SUCCESS           The last data returned from the access matched the poll exit criteria.\r
  @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.\r
  @retval EFI_UNSUPPORTED       Offset is not valid for the BarIndex of this PCI controller.\r
  @retval EFI_TIMEOUT           Delay expired before a match occurred.\r
  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_POLL_IO_MEM)(\r
  IN EFI_PCI_IO_PROTOCOL           *This,\r
  IN  EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
  IN  UINT8                        BarIndex,\r
  IN  UINT64                       Offset,\r
  IN  UINT64                       Mask,\r
  IN  UINT64                       Value,\r
  IN  UINT64                       Delay,\r
  OUT UINT64                       *Result\r
  );\r
\r
/**\r
  Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
\r
  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
  @param  Width                 Signifies the width of the memory or I/O operations.\r
  @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the\r
                                base address for the memory or I/O operation to perform.\r
  @param  Offset                The offset within the selected BAR to start the memory or I/O operation.\r
  @param  Count                 The number of memory or I/O operations to perform.\r
  @param  Buffer                For read operations, the destination buffer to store the results. For write\r
                                operations, the source buffer to write data from.\r
\r
  @retval EFI_SUCCESS           The data was read from or written to the PCI controller.\r
  @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.\r
  @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not\r
                                valid for the PCI BAR specified by BarIndex.\r
  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_IO_MEM)(\r
  IN EFI_PCI_IO_PROTOCOL              *This,\r
  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
  IN     UINT8                        BarIndex,\r
  IN     UINT64                       Offset,\r
  IN     UINTN                        Count,\r
  IN OUT VOID                         *Buffer\r
  );\r
\r
typedef struct {\r
  ///\r
  /// Read PCI controller registers in the PCI memory or I/O space.\r
  ///\r
  EFI_PCI_IO_PROTOCOL_IO_MEM  Read;\r
  ///\r
  /// Write PCI controller registers in the PCI memory or I/O space.\r
  ///\r
  EFI_PCI_IO_PROTOCOL_IO_MEM  Write;\r
} EFI_PCI_IO_PROTOCOL_ACCESS;\r
\r
/**\r
  Enable a PCI driver to access PCI controller registers in PCI configuration space.\r
\r
  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
  @param  Width                 Signifies the width of the memory operations.\r
  @param  Offset                The offset within the PCI configuration space for the PCI controller.\r
  @param  Count                 The number of PCI configuration operations to perform.\r
  @param  Buffer                For read operations, the destination buffer to store the results. For write\r
                                operations, the source buffer to write data from.\r
\r
\r
  @retval EFI_SUCCESS           The data was read from or written to the PCI controller.\r
  @retval EFI_UNSUPPORTED       The address range specified by Offset, Width, and Count is not\r
                                valid for the PCI configuration header of the PCI controller.\r
  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
  @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_CONFIG)(\r
  IN EFI_PCI_IO_PROTOCOL              *This,\r
  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
  IN     UINT32                       Offset,\r
  IN     UINTN                        Count,\r
  IN OUT VOID                         *Buffer\r
  );\r
\r
typedef struct {\r
  ///\r
  /// Read PCI controller registers in PCI configuration space.\r
  ///\r
  EFI_PCI_IO_PROTOCOL_CONFIG  Read;\r
  ///\r
  /// Write PCI controller registers in PCI configuration space.\r
  ///\r
  EFI_PCI_IO_PROTOCOL_CONFIG  Write;\r
} EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS;\r
\r
/**\r
  Enables a PCI driver to copy one region of PCI memory space to another region of PCI\r
  memory space.\r
\r
  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
  @param  Width                 Signifies the width of the memory operations.\r
  @param  DestBarIndex          The BAR index in the standard PCI Configuration header to use as the\r
                                base address for the memory operation to perform.\r
  @param  DestOffset            The destination offset within the BAR specified by DestBarIndex to\r
                                start the memory writes for the copy operation.\r
  @param  SrcBarIndex           The BAR index in the standard PCI Configuration header to use as the\r
                                base address for the memory operation to perform.\r
  @param  SrcOffset             The source offset within the BAR specified by SrcBarIndex to start\r
                                the memory reads for the copy operation.\r
  @param  Count                 The number of memory operations to perform. Bytes moved is Width\r
                                size * Count, starting at DestOffset and SrcOffset.\r
\r
  @retval EFI_SUCCESS           The data was copied from one memory region to another memory region.\r
  @retval EFI_UNSUPPORTED       DestBarIndex not valid for this PCI controller.\r
  @retval EFI_UNSUPPORTED       SrcBarIndex not valid for this PCI controller.\r
  @retval EFI_UNSUPPORTED       The address range specified by DestOffset, Width, and Count\r
                                is not valid for the PCI BAR specified by DestBarIndex.\r
  @retval EFI_UNSUPPORTED       The address range specified by SrcOffset, Width, and Count is\r
                                not valid for the PCI BAR specified by SrcBarIndex.\r
  @retval EFI_INVALID_PARAMETER Width is invalid.\r
  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_COPY_MEM)(\r
  IN EFI_PCI_IO_PROTOCOL              *This,\r
  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
  IN     UINT8                        DestBarIndex,\r
  IN     UINT64                       DestOffset,\r
  IN     UINT8                        SrcBarIndex,\r
  IN     UINT64                       SrcOffset,\r
  IN     UINTN                        Count\r
  );\r
\r
/**\r
  Provides the PCI controller-specific addresses needed to access system memory.\r
\r
  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
  @param  Operation             Indicates if the bus master is going to read or write to system memory.\r
  @param  HostAddress           The system memory address to map to the PCI controller.\r
  @param  NumberOfBytes         On input the number of bytes to map. On output the number of bytes\r
                                that were mapped.\r
  @param  DeviceAddress         The resulting map address for the bus master PCI controller to use to\r
                                access the hosts HostAddress.\r
  @param  Mapping               A resulting value to pass to Unmap().\r
\r
  @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.\r
  @retval EFI_UNSUPPORTED       The HostAddress cannot be mapped as a common buffer.\r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
  @retval EFI_DEVICE_ERROR      The system hardware could not map the requested address.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_MAP)(\r
  IN EFI_PCI_IO_PROTOCOL                *This,\r
  IN     EFI_PCI_IO_PROTOCOL_OPERATION  Operation,\r
  IN     VOID                           *HostAddress,\r
  IN OUT UINTN                          *NumberOfBytes,\r
  OUT    EFI_PHYSICAL_ADDRESS           *DeviceAddress,\r
  OUT    VOID                           **Mapping\r
  );\r
\r
/**\r
  Completes the Map() operation and releases any corresponding resources.\r
\r
  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
  @param  Mapping               The mapping value returned from Map().\r
\r
  @retval EFI_SUCCESS           The range was unmapped.\r
  @retval EFI_DEVICE_ERROR      The data was not committed to the target system memory.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_UNMAP)(\r
  IN EFI_PCI_IO_PROTOCOL           *This,\r
  IN  VOID                         *Mapping\r
  );\r
\r
/**\r
  Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer\r
  or EfiPciOperationBusMasterCommonBuffer64 mapping.\r
\r
  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
  @param  Type                  This parameter is not used and must be ignored.\r
  @param  MemoryType            The type of memory to allocate, EfiBootServicesData or\r
                                EfiRuntimeServicesData.\r
  @param  Pages                 The number of pages to allocate.\r
  @param  HostAddress           A pointer to store the base system memory address of the\r
                                allocated range.\r
  @param  Attributes            The requested bit mask of attributes for the allocated range.\r
\r
  @retval EFI_SUCCESS           The requested memory pages were allocated.\r
  @retval EFI_UNSUPPORTED       Attributes is unsupported. The only legal attribute bits are\r
                                MEMORY_WRITE_COMBINE, MEMORY_CACHED and DUAL_ADDRESS_CYCLE.\r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
  @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER)(\r
  IN EFI_PCI_IO_PROTOCOL           *This,\r
  IN  EFI_ALLOCATE_TYPE            Type,\r
  IN  EFI_MEMORY_TYPE              MemoryType,\r
  IN  UINTN                        Pages,\r
  OUT VOID                         **HostAddress,\r
  IN  UINT64                       Attributes\r
  );\r
\r
/**\r
  Frees memory that was allocated with AllocateBuffer().\r
\r
  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
  @param  Pages                 The number of pages to free.\r
  @param  HostAddress           The base system memory address of the allocated range.\r
\r
  @retval EFI_SUCCESS           The requested memory pages were freed.\r
  @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
                                was not allocated with AllocateBuffer().\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_FREE_BUFFER)(\r
  IN EFI_PCI_IO_PROTOCOL           *This,\r
  IN  UINTN                        Pages,\r
  IN  VOID                         *HostAddress\r
  );\r
\r
/**\r
  Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r
\r
  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
\r
  @retval EFI_SUCCESS           The PCI posted write transactions were flushed from the PCI host\r
                                bridge to system memory.\r
  @retval EFI_DEVICE_ERROR      The PCI posted write transactions were not flushed from the PCI\r
                                host bridge due to a hardware error.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_FLUSH)(\r
  IN EFI_PCI_IO_PROTOCOL  *This\r
  );\r
\r
/**\r
  Retrieves this PCI controller's current PCI bus number, device number, and function number.\r
\r
  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
  @param  SegmentNumber         The PCI controller's current PCI segment number.\r
  @param  BusNumber             The PCI controller's current PCI bus number.\r
  @param  DeviceNumber          The PCI controller's current PCI device number.\r
  @param  FunctionNumber        The PCI controller's current PCI function number.\r
\r
  @retval EFI_SUCCESS           The PCI controller location was returned.\r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_GET_LOCATION)(\r
  IN EFI_PCI_IO_PROTOCOL          *This,\r
  OUT UINTN                       *SegmentNumber,\r
  OUT UINTN                       *BusNumber,\r
  OUT UINTN                       *DeviceNumber,\r
  OUT UINTN                       *FunctionNumber\r
  );\r
\r
/**\r
  Performs an operation on the attributes that this PCI controller supports. The operations include\r
  getting the set of supported attributes, retrieving the current attributes, setting the current\r
  attributes, enabling attributes, and disabling attributes.\r
\r
  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
  @param  Operation             The operation to perform on the attributes for this PCI controller.\r
  @param  Attributes            The mask of attributes that are used for Set, Enable, and Disable\r
                                operations.\r
  @param  Result                A pointer to the result mask of attributes that are returned for the Get\r
                                and Supported operations.\r
\r
  @retval EFI_SUCCESS           The operation on the PCI controller's attributes was completed.\r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
  @retval EFI_UNSUPPORTED       one or more of the bits set in\r
                                Attributes are not supported by this PCI controller or one of\r
                                its parent bridges when Operation is Set, Enable or Disable.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_ATTRIBUTES)(\r
  IN EFI_PCI_IO_PROTOCOL                       *This,\r
  IN  EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION  Operation,\r
  IN  UINT64                                   Attributes,\r
  OUT UINT64                                   *Result OPTIONAL\r
  );\r
\r
/**\r
  Gets the attributes that this PCI controller supports setting on a BAR using\r
  SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.\r
\r
  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
  @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the\r
                                base address for resource range. The legal range for this field is 0..5.\r
  @param  Supports              A pointer to the mask of attributes that this PCI controller supports\r
                                setting for this BAR with SetBarAttributes().\r
  @param  Resources             A pointer to the resource descriptors that describe the current\r
                                configuration of this BAR of the PCI controller.\r
\r
  @retval EFI_SUCCESS           If Supports is not NULL, then the attributes that the PCI\r
                                controller supports are returned in Supports. If Resources\r
                                is not NULL, then the resource descriptors that the PCI\r
                                controller is currently using are returned in Resources.\r
  @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
  @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.\r
  @retval EFI_OUT_OF_RESOURCES  There are not enough resources available to allocate\r
                                Resources.\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES)(\r
  IN EFI_PCI_IO_PROTOCOL             *This,\r
  IN  UINT8                          BarIndex,\r
  OUT UINT64                         *Supports, OPTIONAL\r
  OUT VOID                           **Resources OPTIONAL\r
  );\r
\r
/**\r
  Sets the attributes for a range of a BAR on a PCI controller.\r
\r
  @param  This                  A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
  @param  Attributes            The mask of attributes to set for the resource range specified by\r
                                BarIndex, Offset, and Length.\r
  @param  BarIndex              The BAR index of the standard PCI Configuration header to use as the\r
                                base address for resource range. The legal range for this field is 0..5.\r
  @param  Offset                A pointer to the BAR relative base address of the resource range to be\r
                                modified by the attributes specified by Attributes.\r
  @param  Length                A pointer to the length of the resource range to be modified by the\r
                                attributes specified by Attributes.\r
\r
  @retval EFI_SUCCESS           The set of attributes specified by Attributes for the resource\r
                                range specified by BarIndex, Offset, and Length were\r
                                set on the PCI controller, and the actual resource range is returned\r
                                in Offset and Length.\r
  @retval EFI_INVALID_PARAMETER Offset or Length is NULL.\r
  @retval EFI_UNSUPPORTED       BarIndex not valid for this PCI controller.\r
  @retval EFI_OUT_OF_RESOURCES  There are not enough resources to set the attributes on the\r
                                resource range specified by BarIndex, Offset, and\r
                                Length.\r
\r
**/\r
typedef\r
EFI_STATUS\r
(EFIAPI *EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES)(\r
  IN EFI_PCI_IO_PROTOCOL              *This,\r
  IN     UINT64                       Attributes,\r
  IN     UINT8                        BarIndex,\r
  IN OUT UINT64                       *Offset,\r
  IN OUT UINT64                       *Length\r
  );\r
\r
///\r
/// The EFI_PCI_IO_PROTOCOL provides the basic Memory, I/O, PCI configuration,\r
/// and DMA interfaces used to abstract accesses to PCI controllers.\r
/// There is one EFI_PCI_IO_PROTOCOL instance for each PCI controller on a PCI bus.\r
/// A device driver that wishes to manage a PCI controller in a system will have to\r
/// retrieve the EFI_PCI_IO_PROTOCOL instance that is associated with the PCI controller.\r
///\r
struct _EFI_PCI_IO_PROTOCOL {\r
  EFI_PCI_IO_PROTOCOL_POLL_IO_MEM         PollMem;\r
  EFI_PCI_IO_PROTOCOL_POLL_IO_MEM         PollIo;\r
  EFI_PCI_IO_PROTOCOL_ACCESS              Mem;\r
  EFI_PCI_IO_PROTOCOL_ACCESS              Io;\r
  EFI_PCI_IO_PROTOCOL_CONFIG_ACCESS       Pci;\r
  EFI_PCI_IO_PROTOCOL_COPY_MEM            CopyMem;\r
  EFI_PCI_IO_PROTOCOL_MAP                 Map;\r
  EFI_PCI_IO_PROTOCOL_UNMAP               Unmap;\r
  EFI_PCI_IO_PROTOCOL_ALLOCATE_BUFFER     AllocateBuffer;\r
  EFI_PCI_IO_PROTOCOL_FREE_BUFFER         FreeBuffer;\r
  EFI_PCI_IO_PROTOCOL_FLUSH               Flush;\r
  EFI_PCI_IO_PROTOCOL_GET_LOCATION        GetLocation;\r
  EFI_PCI_IO_PROTOCOL_ATTRIBUTES          Attributes;\r
  EFI_PCI_IO_PROTOCOL_GET_BAR_ATTRIBUTES  GetBarAttributes;\r
  EFI_PCI_IO_PROTOCOL_SET_BAR_ATTRIBUTES  SetBarAttributes;\r
\r
  ///\r
  /// The size, in bytes, of the ROM image.\r
  ///\r
  UINT64                                  RomSize;\r
\r
  ///\r
  /// A pointer to the in memory copy of the ROM image. The PCI Bus Driver is responsible\r
  /// for allocating memory for the ROM image, and copying the contents of the ROM to memory.\r
  /// The contents of this buffer are either from the PCI option ROM that can be accessed\r
  /// through the ROM BAR of the PCI controller, or it is from a platform-specific location.\r
  /// The Attributes() function can be used to determine from which of these two sources\r
  /// the RomImage buffer was initialized.\r
  ///\r
  VOID                                    *RomImage;\r
};\r
\r
extern EFI_GUID gEfiPciIoProtocolGuid;\r
\r
#endif\r