[mirror_edk2.git] / MdePkg / Include / Protocol / PciIo.h

/** @file\r
  EFI PCI I/O Protocol provides the basic Memory, I/O, PCI configuration, \r
  and DMA interfaces that a driver uses to access its PCI controller.\r
\r
  Copyright (c) 2006 - 2008, Intel Corporation                                                         \r
  All rights reserved. This program and the accompanying materials                          \r
  are licensed and made available under the terms and conditions of the BSD License         \r
  which accompanies this distribution.  The full text of the license may be found at        \r
  http://opensource.org/licenses/bsd-license.php                                            \r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
\r
**/\r
\r
#ifndef __PCI_IO_H__\r
#define __PCI_IO_H__\r
\r
///\r
/// Global ID for the PCI I/O Protocol\r
///\r
#define EFI_PCI_IO_PROTOCOL_GUID \\r
  { \\r
    0x4cf5b200, 0x68b8, 0x4ca5, {0x9e, 0xec, 0xb2, 0x3e, 0x3f, 0x50, 0x2, 0x9a } \\r
  }\r
\r
typedef struct _EFI_PCI_IO_PROTOCOL  EFI_PCI_IO_PROTOCOL;\r
\r
///\r
/// *******************************************************\r
/// EFI_PCI_IO_PROTOCOL_WIDTH\r
/// *******************************************************\r
///\r
typedef enum {\r
  EfiPciIoWidthUint8      = 0,\r
  EfiPciIoWidthUint16,\r
  EfiPciIoWidthUint32,\r
  EfiPciIoWidthUint64,\r
  EfiPciIoWidthFifoUint8,\r
  EfiPciIoWidthFifoUint16,\r
  EfiPciIoWidthFifoUint32,\r
  EfiPciIoWidthFifoUint64,\r
  EfiPciIoWidthFillUint8,\r
  EfiPciIoWidthFillUint16,\r
  EfiPciIoWidthFillUint32,\r
  EfiPciIoWidthFillUint64,\r
  EfiPciIoWidthMaximum\r
} EFI_PCI_IO_PROTOCOL_WIDTH;\r
\r
//\r
// Complete PCI address generater\r
//\r
#define EFI_PCI_IO_PASS_THROUGH_BAR               0xff    ///< Special BAR that passes a memory or I/O cycle through unchanged\r
#define EFI_PCI_IO_ATTRIBUTE_MASK                 0x077f  ///< All the following I/O and Memory cycles\r
#define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO   0x0001  ///< I/O cycles 0x0000-0x00FF (10 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_ISA_IO               0x0002  ///< I/O cycles 0x0100-0x03FF or greater (10 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO       0x0004  ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (10 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY           0x0008  ///< MEM cycles 0xA0000-0xBFFFF (24 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_VGA_IO               0x0010  ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO       0x0020  ///< I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO     0x0040  ///< I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080  ///< Map a memory range so write are combined\r
#define EFI_PCI_IO_ATTRIBUTE_IO                   0x0100  ///< Enable the I/O decode bit in the PCI Config Header\r
#define EFI_PCI_IO_ATTRIBUTE_MEMORY               0x0200  ///< Enable the Memory decode bit in the PCI Config Header\r
#define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER           0x0400  ///< Enable the DMA bit in the PCI Config Header\r
#define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED        0x0800  ///< Map a memory range so all r/w accesses are cached\r
#define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE       0x1000  ///< Disable a memory range\r
#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE      0x2000  ///< Clear for an add-in PCI Device\r
#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM         0x4000  ///< Clear for a physical PCI Option ROM accessed through ROM BAR\r
#define EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE   0x8000  ///< Clear for PCI controllers that can not genrate a DAC\r
#define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16            0x10000 ///< I/O cycles 0x0100-0x03FF or greater (16 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16    0x20000 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (16 bit decode)\r
#define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16            0x30000 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode)\r
\r
#define EFI_PCI_DEVICE_ENABLE                     (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER)\r
#define EFI_VGA_DEVICE_ENABLE                     (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY | EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_IO)\r
\r
///\r
/// *******************************************************\r
/// EFI_PCI_IO_PROTOCOL_OPERATION\r
/// *******************************************************\r
///\r
typedef enum {\r
  ///\r
  /// A read operation from system memory by a bus master.\r
  ///\r
  EfiPciIoOperationBusMasterRead,\r
  ///\r
  /// A write operation from system memory by a bus master.\r
  ///\r
  EfiPciIoOperationBusMasterWrite,\r
  ///\r
  /// Provides both read and write access to system memory by both the processor and a\r
Commit	Line	Data
d1f95000	1	/** @file\r
4ca9b6c4 LG	2	EFI PCI I/O Protocol provides the basic Memory, I/O, PCI configuration, \r
4ca9b6c4 LG	3	and DMA interfaces that a driver uses to access its PCI controller.\r
d1f95000	4	\r
4ca9b6c4	5	Copyright (c) 2006 - 2008, Intel Corporation \r
d1f95000	6	All rights reserved. This program and the accompanying materials \r
	7	are licensed and made available under the terms and conditions of the BSD License \r
	8	which accompanies this distribution. The full text of the license may be found at \r
	9	http://opensource.org/licenses/bsd-license.php \r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
	13	\r
d1f95000	14	**/\r
	15	\r
	16	#ifndef __PCI_IO_H__\r
	17	#define __PCI_IO_H__\r
	18	\r
99e8ed21	19	///\r
	20	/// Global ID for the PCI I/O Protocol\r
	21	///\r
d1f95000	22	#define EFI_PCI_IO_PROTOCOL_GUID \\r
	23	{ \\r
	24	0x4cf5b200, 0x68b8, 0x4ca5, {0x9e, 0xec, 0xb2, 0x3e, 0x3f, 0x50, 0x2, 0x9a } \\r
	25	}\r
	26	\r
	27	typedef struct _EFI_PCI_IO_PROTOCOL EFI_PCI_IO_PROTOCOL;\r
	28	\r
99e8ed21	29	///\r
9319d2c2 LG	30	/// *******************************************************\r
	31	/// EFI_PCI_IO_PROTOCOL_WIDTH\r
	32	/// *******************************************************\r
99e8ed21	33	///\r
d1f95000	34	typedef enum {\r
	35	EfiPciIoWidthUint8 = 0,\r
	36	EfiPciIoWidthUint16,\r
	37	EfiPciIoWidthUint32,\r
	38	EfiPciIoWidthUint64,\r
	39	EfiPciIoWidthFifoUint8,\r
	40	EfiPciIoWidthFifoUint16,\r
	41	EfiPciIoWidthFifoUint32,\r
	42	EfiPciIoWidthFifoUint64,\r
	43	EfiPciIoWidthFillUint8,\r
	44	EfiPciIoWidthFillUint16,\r
	45	EfiPciIoWidthFillUint32,\r
	46	EfiPciIoWidthFillUint64,\r
	47	EfiPciIoWidthMaximum\r
	48	} EFI_PCI_IO_PROTOCOL_WIDTH;\r
	49	\r
	50	//\r
	51	// Complete PCI address generater\r
	52	//\r
cce6f7aa	53	#define EFI_PCI_IO_PASS_THROUGH_BAR 0xff ///< Special BAR that passes a memory or I/O cycle through unchanged\r
	54	#define EFI_PCI_IO_ATTRIBUTE_MASK 0x077f ///< All the following I/O and Memory cycles\r
	55	#define EFI_PCI_IO_ATTRIBUTE_ISA_MOTHERBOARD_IO 0x0001 ///< I/O cycles 0x0000-0x00FF (10 bit decode)\r
	56	#define EFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 ///< I/O cycles 0x0100-0x03FF or greater (10 bit decode)\r
	57	#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO 0x0004 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (10 bit decode)\r
	58	#define EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 ///< MEM cycles 0xA0000-0xBFFFF (24 bit decode)\r
	59	#define EFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode)\r
	60	#define EFI_PCI_IO_ATTRIBUTE_IDE_PRIMARY_IO 0x0020 ///< I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode)\r
	61	#define EFI_PCI_IO_ATTRIBUTE_IDE_SECONDARY_IO 0x0040 ///< I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode)\r
	62	#define EFI_PCI_IO_ATTRIBUTE_MEMORY_WRITE_COMBINE 0x0080 ///< Map a memory range so write are combined\r
	63	#define EFI_PCI_IO_ATTRIBUTE_IO 0x0100 ///< Enable the I/O decode bit in the PCI Config Header\r
	64	#define EFI_PCI_IO_ATTRIBUTE_MEMORY 0x0200 ///< Enable the Memory decode bit in the PCI Config Header\r
	65	#define EFI_PCI_IO_ATTRIBUTE_BUS_MASTER 0x0400 ///< Enable the DMA bit in the PCI Config Header\r
	66	#define EFI_PCI_IO_ATTRIBUTE_MEMORY_CACHED 0x0800 ///< Map a memory range so all r/w accesses are cached\r
	67	#define EFI_PCI_IO_ATTRIBUTE_MEMORY_DISABLE 0x1000 ///< Disable a memory range\r
	68	#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEVICE 0x2000 ///< Clear for an add-in PCI Device\r
	69	#define EFI_PCI_IO_ATTRIBUTE_EMBEDDED_ROM 0x4000 ///< Clear for a physical PCI Option ROM accessed through ROM BAR\r
	70	#define EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE 0x8000 ///< Clear for PCI controllers that can not genrate a DAC\r
	71	#define EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 0x10000 ///< I/O cycles 0x0100-0x03FF or greater (16 bit decode)\r
	72	#define EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO_16 0x20000 ///< I/O cycles 0x3C6, 0x3C8, 0x3C9 (16 bit decode)\r
	73	#define EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 0x30000 ///< I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode)\r
d1f95000	74	\r
	75	#define EFI_PCI_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_IO \| EFI_PCI_IO_ATTRIBUTE_MEMORY \| EFI_PCI_IO_ATTRIBUTE_BUS_MASTER)\r
	76	#define EFI_VGA_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO \| EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY \| EFI_PCI_IO_ATTRIBUTE_VGA_IO \| EFI_PCI_IO_ATTRIBUTE_IO)\r
	77	\r
99e8ed21	78	///\r
	79	/// *******************************************************\r
	80	/// EFI_PCI_IO_PROTOCOL_OPERATION\r
	81	/// *******************************************************\r
	82	///\r
d1f95000	83	typedef enum {\r
992f22b9 LG	84	///\r
	85	/// A read operation from system memory by a bus master.\r
	86	///\r
d1f95000	87	EfiPciIoOperationBusMasterRead,\r
992f22b9 LG	88	///\r
	89	/// A write operation from system memory by a bus master.\r
	90	///\r
d1f95000	91	EfiPciIoOperationBusMasterWrite,\r
992f22b9 LG	92	///\r
	93	/// Provides both read and write access to system memory by both the processor and a\r
	94