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[mirror_edk2.git] / MdePkg / Include / Register / Amd / Cpuid.h

/** @file\r
  CPUID leaf definitions.\r
\r
  Provides defines for CPUID leaf indexes.  Data structures are provided for\r
  registers returned by a CPUID leaf that contain one or more bit fields.\r
  If a register returned is a single 32-bit value, then a data structure is\r
  not provided for that register.\r
\r
  Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
  @par Specification Reference:\r
  AMD64 Architecture Programming Manual volume 2, March 2017, Sections 15.34\r
\r
**/\r
\r
#ifndef __AMD_CPUID_H__\r
#define __AMD_CPUID_H__\r
\r
/**\r
CPUID Signature Information\r
\r
@param   EAX  CPUID_SIGNATURE (0x00)\r
\r
@retval  EAX  Returns the highest value the CPUID instruction recognizes for\r
              returning basic processor information. The value is returned is\r
              processor specific.\r
@retval  EBX  First 4 characters of a vendor identification string.\r
@retval  ECX  Last 4 characters of a vendor identification string.\r
@retval  EDX  Middle 4 characters of a vendor identification string.\r
\r
**/\r
\r
///\r
/// @{ CPUID signature values returned by AMD processors\r
///\r
#define CPUID_SIGNATURE_AUTHENTIC_AMD_EBX  SIGNATURE_32 ('A', 'u', 't', 'h')\r
#define CPUID_SIGNATURE_AUTHENTIC_AMD_EDX  SIGNATURE_32 ('e', 'n', 't', 'i')\r
#define CPUID_SIGNATURE_AUTHENTIC_AMD_ECX  SIGNATURE_32 ('c', 'A', 'M', 'D')\r
///\r
/// @}\r
///\r
\r
/**\r
  CPUID Extended Processor Signature and Features\r
\r
  @param   EAX  CPUID_EXTENDED_CPU_SIG (0x80000001)\r
\r
  @retval  EAX  Extended Family, Model, Stepping Identifiers\r
                described by the type CPUID_AMD_EXTENDED_CPU_SIG_EAX.\r
  @retval  EBX  Brand Identifier\r
                described by the type CPUID_AMD_EXTENDED_CPU_SIG_EBX.\r
  @retval  ECX  Extended Feature Identifiers\r
                described by the type CPUID_AMD_EXTENDED_CPU_SIG_ECX.\r
  @retval  EDX  Extended Feature Identifiers\r
                described by the type CPUID_AMD_EXTENDED_CPU_SIG_EDX.\r
**/\r
\r
/**\r
  CPUID Extended Processor Signature and Features EAX for CPUID leaf\r
  #CPUID_EXTENDED_CPU_SIG.\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 3:0] Stepping.\r
    ///\r
    UINT32    Stepping   : 4;\r
    ///\r
    /// [Bits 7:4] Base Model.\r
    ///\r
    UINT32    BaseModel  : 4;\r
    ///\r
    /// [Bits 11:8] Base Family.\r
    ///\r
    UINT32    BaseFamily : 4;\r
    ///\r
    /// [Bit 15:12] Reserved.\r
    ///\r
    UINT32    Reserved1  : 4;\r
    ///\r
    /// [Bits 19:16] Extended Model.\r
    ///\r
    UINT32    ExtModel   : 4;\r
    ///\r
    /// [Bits 27:20] Extended Family.\r
    ///\r
    UINT32    ExtFamily  : 8;\r
    ///\r
    /// [Bit 31:28] Reserved.\r
    ///\r
    UINT32    Reserved2  : 4;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
} CPUID_AMD_EXTENDED_CPU_SIG_EAX;\r
\r
/**\r
  CPUID Extended Processor Signature and Features EBX for CPUID leaf\r
  #CPUID_EXTENDED_CPU_SIG.\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 27:0] Reserved.\r
    ///\r
    UINT32    Reserved : 28;\r
    ///\r
    /// [Bit 31:28] Package Type.\r
    ///\r
    UINT32    PkgType  : 4;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
} CPUID_AMD_EXTENDED_CPU_SIG_EBX;\r
\r
/**\r
  CPUID Extended Processor Signature and Features ECX for CPUID leaf\r
  #CPUID_EXTENDED_CPU_SIG.\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] LAHF/SAHF available in 64-bit mode.\r
    ///\r
    UINT32    LAHF_SAHF               : 1;\r
    ///\r
    /// [Bit 1] Core multi-processing legacy mode.\r
    ///\r
    UINT32    CmpLegacy               : 1;\r
    ///\r
    /// [Bit 2] Secure Virtual Mode feature.\r
    ///\r
    UINT32    SVM                     : 1;\r
    ///\r
    /// [Bit 3] Extended APIC register space.\r
    ///\r
    UINT32    ExtApicSpace            : 1;\r
    ///\r
    /// [Bit 4] LOCK MOV CR0 means MOV CR8.\r
    ///\r
    UINT32    AltMovCr8               : 1;\r
    ///\r
    /// [Bit 5] LZCNT instruction support.\r
    ///\r
    UINT32    LZCNT                   : 1;\r
    ///\r
    /// [Bit 6] SSE4A instruction support.\r
    ///\r
    UINT32    SSE4A                   : 1;\r
    ///\r
    /// [Bit 7] Misaligned SSE Mode.\r
    ///\r
    UINT32    MisAlignSse             : 1;\r
    ///\r
    /// [Bit 8] ThreeDNow Prefetch instructions.\r
    ///\r
    UINT32    PREFETCHW               : 1;\r
    ///\r
    /// [Bit 9] OS Visible Work-around support.\r
    ///\r
    UINT32    OSVW                    : 1;\r
    ///\r
    /// [Bit 10] Instruction Based Sampling.\r
    ///\r
    UINT32    IBS                     : 1;\r
    ///\r
    /// [Bit 11] Extended Operation Support.\r
    ///\r
    UINT32    XOP                     : 1;\r
    ///\r
    /// [Bit 12] SKINIT and STGI support.\r
    ///\r
    UINT32    SKINIT                  : 1;\r
    ///\r
    /// [Bit 13] Watchdog Timer support.\r
    ///\r
    UINT32    WDT                     : 1;\r
    ///\r
    /// [Bit 14] Reserved.\r
    ///\r
    UINT32    Reserved1               : 1;\r
    ///\r
    /// [Bit 15] Lightweight Profiling support.\r
    ///\r
    UINT32    LWP                     : 1;\r
    ///\r
    /// [Bit 16] 4-Operand FMA instruction support.\r
    ///\r
    UINT32    FMA4                    : 1;\r
    ///\r
    /// [Bit 17] Translation Cache Extension.\r
    ///\r
    UINT32    TCE                     : 1;\r
    ///\r
    /// [Bit 21:18] Reserved.\r
    ///\r
    UINT32    Reserved2               : 4;\r
    ///\r
    /// [Bit 22] Topology Extensions support.\r
    ///\r
    UINT32    TopologyExtensions      : 1;\r
    ///\r
    /// [Bit 23] Core Performance Counter Extensions.\r
    ///\r
    UINT32    PerfCtrExtCore          : 1;\r
    ///\r
    /// [Bit 25:24] Reserved.\r
    ///\r
    UINT32    Reserved3               : 2;\r
    ///\r
    /// [Bit 26] Data Breakpoint Extension.\r
    ///\r
    UINT32    DataBreakpointExtension : 1;\r
    ///\r
    /// [Bit 27] Performance Time-Stamp Counter.\r
    ///\r
    UINT32    PerfTsc                 : 1;\r
    ///\r
    /// [Bit 28] L3 Performance Counter Extensions.\r
    ///\r
    UINT32    PerfCtrExtL3            : 1;\r
    ///\r
    /// [Bit 29] MWAITX and MONITORX capability.\r
    ///\r
    UINT32    MwaitExtended           : 1;\r
    ///\r
    /// [Bit 31:30] Reserved.\r
    ///\r
    UINT32    Reserved4               : 2;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
} CPUID_AMD_EXTENDED_CPU_SIG_ECX;\r
\r
/**\r
  CPUID Extended Processor Signature and Features EDX for CPUID leaf\r
  #CPUID_EXTENDED_CPU_SIG.\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] x87 floating point unit on-chip.\r
    ///\r
    UINT32    FPU            : 1;\r
    ///\r
    /// [Bit 1] Virtual-mode enhancements.\r
    ///\r
    UINT32    VME            : 1;\r
    ///\r
    /// [Bit 2] Debugging extensions, IO breakpoints, CR4.DE.\r
    ///\r
    UINT32    DE             : 1;\r
    ///\r
    /// [Bit 3] Page-size extensions (4 MB pages).\r
    ///\r
    UINT32    PSE            : 1;\r
    ///\r
    /// [Bit 4] Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD.\r
    ///\r
    UINT32    TSC            : 1;\r
    ///\r
    /// [Bit 5] MSRs, with RDMSR and WRMSR instructions.\r
    ///\r
    UINT32    MSR            : 1;\r
    ///\r
    /// [Bit 6] Physical-address extensions (PAE).\r
    ///\r
    UINT32    PAE            : 1;\r
    ///\r
    /// [Bit 7] Machine check exception, CR4.MCE.\r
    ///\r
    UINT32    MCE            : 1;\r
    ///\r
    /// [Bit 8] CMPXCHG8B instruction.\r
    ///\r
    UINT32    CMPXCHG8B      : 1;\r
    ///\r
    /// [Bit 9] APIC exists and is enabled.\r
    ///\r
    UINT32    APIC           : 1;\r
    ///\r
    /// [Bit 10] Reserved.\r
    ///\r
    UINT32    Reserved1      : 1;\r
    ///\r
    /// [Bit 11] SYSCALL and SYSRET instructions.\r
    ///\r
    UINT32    SYSCALL_SYSRET : 1;\r
    ///\r
    /// [Bit 12] Memory-type range registers.\r
    ///\r
    UINT32    MTRR           : 1;\r
    ///\r
    /// [Bit 13] Page global extension, CR4.PGE.\r
    ///\r
    UINT32    PGE            : 1;\r
    ///\r
    /// [Bit 14] Machine check architecture, MCG_CAP.\r
    ///\r
    UINT32    MCA            : 1;\r
    ///\r
    /// [Bit 15] Conditional move instructions, CMOV, FCOMI, FCMOV.\r
    ///\r
    UINT32    CMOV           : 1;\r
    ///\r
    /// [Bit 16] Page attribute table.\r
    ///\r
    UINT32    PAT            : 1;\r
    ///\r
    /// [Bit 17] Page-size extensions.\r
    ///\r
    UINT32    PSE36          : 1;\r
    ///\r
    /// [Bit 19:18] Reserved.\r
    ///\r
    UINT32    Reserved2      : 2;\r
    ///\r
    /// [Bit 20] No-execute page protection.\r
    ///\r
    UINT32    NX             : 1;\r
    ///\r
    /// [Bit 21] Reserved.\r
    ///\r
    UINT32    Reserved3      : 1;\r
    ///\r
    /// [Bit 22] AMD Extensions to MMX instructions.\r
    ///\r
    UINT32    MmxExt         : 1;\r
    ///\r
    /// [Bit 23] MMX instructions.\r
    ///\r
    UINT32    MMX            : 1;\r
    ///\r
    /// [Bit 24] FXSAVE and FXRSTOR instructions.\r
    ///\r
    UINT32    FFSR           : 1;\r
    ///\r
    /// [Bit 25] FXSAVE and FXRSTOR instruction optimizations.\r
    ///\r
    UINT32    FFXSR          : 1;\r
    ///\r
    /// [Bit 26] 1-GByte large page support.\r
    ///\r
    UINT32    Page1GB        : 1;\r
    ///\r
    /// [Bit 27] RDTSCP instructions.\r
    ///\r
    UINT32    RDTSCP         : 1;\r
    ///\r
    /// [Bit 28] Reserved.\r
    ///\r
    UINT32    Reserved4      : 1;\r
    ///\r
    /// [Bit 29] Long Mode.\r
    ///\r
    UINT32    LM             : 1;\r
    ///\r
    /// [Bit 30] 3DNow! instructions.\r
    ///\r
    UINT32    ThreeDNow      : 1;\r
    ///\r
    /// [Bit 31] AMD Extensions to 3DNow! instructions.\r
    ///\r
    UINT32    ThreeDNowExt   : 1;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
} CPUID_AMD_EXTENDED_CPU_SIG_EDX;\r
\r
/**\r
CPUID Linear Physical Address Size\r
\r
@param   EAX  CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)\r
\r
@retval  EAX  Linear/Physical Address Size described by the type\r
              CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX.\r
@retval  EBX  Linear/Physical Address Size described by the type\r
              CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX.\r
@retval  ECX  Linear/Physical Address Size described by the type\r
              CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX.\r
@retval  EDX  Reserved.\r
**/\r
\r
/**\r
  CPUID Linear Physical Address Size EAX for CPUID leaf\r
  #CPUID_VIR_PHY_ADDRESS_SIZE.\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 7:0] Maximum physical byte address size in bits.\r
    ///\r
    UINT32    PhysicalAddressBits : 8;\r
    ///\r
    /// [Bits 15:8] Maximum linear byte address size in bits.\r
    ///\r
    UINT32    LinearAddressBits   : 8;\r
    ///\r
    /// [Bits 23:16] Maximum guest physical byte address size in bits.\r
    ///\r
    UINT32    GuestPhysAddrSize   : 8;\r
    ///\r
    /// [Bit 31:24] Reserved.\r
    ///\r
    UINT32    Reserved            : 8;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX;\r
\r
/**\r
  CPUID Linear Physical Address Size EBX for CPUID leaf\r
  #CPUID_VIR_PHY_ADDRESS_SIZE.\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 0] Clear Zero Instruction.\r
    ///\r
    UINT32    CLZERO     : 1;\r
    ///\r
    /// [Bits 1] Instructions retired count support.\r
    ///\r
    UINT32    IRPerf     : 1;\r
    ///\r
    /// [Bits 2] Restore error pointers for XSave instructions.\r
    ///\r
    UINT32    XSaveErPtr : 1;\r
    ///\r
    /// [Bit 31:3] Reserved.\r
    ///\r
    UINT32    Reserved   : 29;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX;\r
\r
/**\r
  CPUID Linear Physical Address Size ECX for CPUID leaf\r
  #CPUID_VIR_PHY_ADDRESS_SIZE.\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 7:0] Number of threads - 1.\r
    ///\r
    UINT32    NC               : 8;\r
    ///\r
    /// [Bit 11:8] Reserved.\r
    ///\r
    UINT32    Reserved1        : 4;\r
    ///\r
    /// [Bits 15:12] APIC ID size.\r
    ///\r
    UINT32    ApicIdCoreIdSize : 4;\r
    ///\r
    /// [Bits 17:16] Performance time-stamp counter size.\r
    ///\r
    UINT32    PerfTscSize      : 2;\r
    ///\r
    /// [Bit 31:18] Reserved.\r
    ///\r
    UINT32    Reserved2        : 14;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX;\r
\r
/**\r
  CPUID AMD Processor Topology\r
\r
  @param   EAX  CPUID_AMD_PROCESSOR_TOPOLOGY (0x8000001E)\r
\r
  @retval  EAX  Extended APIC ID described by the type\r
                CPUID_AMD_PROCESSOR_TOPOLOGY_EAX.\r
  @retval  EBX  Core Identifiers described by the type\r
                CPUID_AMD_PROCESSOR_TOPOLOGY_EBX.\r
  @retval  ECX  Node Identifiers described by the type\r
                CPUID_AMD_PROCESSOR_TOPOLOGY_ECX.\r
  @retval  EDX  Reserved.\r
**/\r
#define CPUID_AMD_PROCESSOR_TOPOLOGY  0x8000001E\r
\r
/**\r
  CPUID AMD Processor Topology EAX for CPUID leaf\r
  #CPUID_AMD_PROCESSOR_TOPOLOGY.\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 31:0] Extended APIC Id.\r
    ///\r
    UINT32    ExtendedApicId;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
} CPUID_AMD_PROCESSOR_TOPOLOGY_EAX;\r
\r
/**\r
  CPUID AMD Processor Topology EBX for CPUID leaf\r
  #CPUID_AMD_PROCESSOR_TOPOLOGY.\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 7:0] Core Id.\r
    ///\r
    UINT32    CoreId         : 8;\r
    ///\r
    /// [Bits 15:8] Threads per core.\r
    ///\r
    UINT32    ThreadsPerCore : 8;\r
    ///\r
    /// [Bit 31:16] Reserved.\r
    ///\r
    UINT32    Reserved       : 16;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
} CPUID_AMD_PROCESSOR_TOPOLOGY_EBX;\r
\r
/**\r
  CPUID AMD Processor Topology ECX for CPUID leaf\r
  #CPUID_AMD_PROCESSOR_TOPOLOGY.\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 7:0] Node Id.\r
    ///\r
    UINT32    NodeId            : 8;\r
    ///\r
    /// [Bits 10:8] Nodes per processor.\r
    ///\r
    UINT32    NodesPerProcessor : 3;\r
    ///\r
    /// [Bit 31:11] Reserved.\r
    ///\r
    UINT32    Reserved          : 21;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
} CPUID_AMD_PROCESSOR_TOPOLOGY_ECX;\r
\r
/**\r
  CPUID Memory Encryption Information\r
\r
  @param   EAX  CPUID_MEMORY_ENCRYPTION_INFO (0x8000001F)\r
\r
  @retval  EAX  Returns the memory encryption feature support status.\r
  @retval  EBX  If memory encryption feature is present then return\r
                the page table bit number used to enable memory encryption support\r
                and reducing of physical address space in bits.\r
  @retval  ECX  Returns number of encrypted guest supported simultaneously.\r
  @retval  EDX  Returns minimum SEV enabled and SEV disabled ASID.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT32 Eax;\r
  UINT32 Ebx;\r
  UINT32 Ecx;\r
  UINT32 Edx;\r
\r
  AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, &Eax, &Ebx, &Ecx, &Edx);\r
  @endcode\r
**/\r
\r
#define CPUID_MEMORY_ENCRYPTION_INFO  0x8000001F\r
\r
/**\r
  CPUID Memory Encryption support information EAX for CPUID leaf\r
  #CPUID_MEMORY_ENCRYPTION_INFO.\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Secure Memory Encryption (Sme) Support\r
    ///\r
    UINT32    SmeBit          : 1;\r
\r
    ///\r
    /// [Bit 1] Secure Encrypted Virtualization (Sev) Support\r
    ///\r
    UINT32    SevBit          : 1;\r
\r
    ///\r
    /// [Bit 2] Page flush MSR support\r
    ///\r
    UINT32    PageFlushMsrBit : 1;\r
\r
    ///\r
    /// [Bit 3] Encrypted state support\r
    ///\r
    UINT32    SevEsBit        : 1;\r
\r
    ///\r
    /// [Bit 31:4] Reserved\r
    ///\r
    UINT32    ReservedBits    : 28;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
} CPUID_MEMORY_ENCRYPTION_INFO_EAX;\r
\r
/**\r
  CPUID Memory Encryption support information EBX for CPUID leaf\r
  #CPUID_MEMORY_ENCRYPTION_INFO.\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 5:0] Page table bit number used to enable memory encryption\r
    ///\r
    UINT32    PtePosBits      : 6;\r
\r
    ///\r
    /// [Bit 11:6] Reduction of system physical address space bits when\r
    ///  memory encryption is enabled\r
    ///\r
    UINT32    ReducedPhysBits : 5;\r
\r
    ///\r
    /// [Bit 31:12] Reserved\r
    ///\r
    UINT32    ReservedBits    : 21;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
} CPUID_MEMORY_ENCRYPTION_INFO_EBX;\r
\r
/**\r
  CPUID Memory Encryption support information ECX for CPUID leaf\r
  #CPUID_MEMORY_ENCRYPTION_INFO.\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 31:0] Number of encrypted guest supported simultaneously\r
    ///\r
    UINT32    NumGuests;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
} CPUID_MEMORY_ENCRYPTION_INFO_ECX;\r
\r
/**\r
  CPUID Memory Encryption support information EDX for CPUID leaf\r
  #CPUID_MEMORY_ENCRYPTION_INFO.\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 31:0] Minimum SEV enabled, SEV-ES disabled ASID\r
    ///\r
    UINT32    MinAsid;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
} CPUID_MEMORY_ENCRYPTION_INFO_EDX;\r
\r
#endif\r