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[mirror_edk2.git] / MdePkg / Include / Register / Amd / Fam17Msr.h

/** @file\r
  MSR Definitions.\r
\r
  Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
  are provided for MSRs that contain one or more bit fields.  If the MSR value\r
  returned is a single 32-bit or 64-bit value, then a data structure is not\r
  provided for that MSR.\r
\r
  Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
  @par Specification Reference:\r
  AMD64 Architecture Programming Manual volume 2, March 2017, Sections 15.34\r
\r
**/\r
\r
#ifndef __FAM17_MSR_H__\r
#define __FAM17_MSR_H__\r
\r
/**\r
  Secure Encrypted Virtualization - Encrypted State (SEV-ES) GHCB register\r
\r
**/\r
#define MSR_SEV_ES_GHCB  0xc0010130\r
\r
/**\r
  MSR information returned for #MSR_SEV_ES_GHCB\r
**/\r
typedef union {\r
  struct {\r
    UINT32    Function  : 12;\r
    UINT32    Reserved1 : 20;\r
    UINT32    Reserved2 : 32;\r
  } GhcbInfo;\r
\r
  struct {\r
    UINT8     Reserved[3];\r
    UINT8     SevEncryptionBitPos;\r
    UINT16    SevEsProtocolMin;\r
    UINT16    SevEsProtocolMax;\r
  } GhcbProtocol;\r
\r
  struct {\r
    UINT32    Function      : 12;\r
    UINT32    ReasonCodeSet : 4;\r
    UINT32    ReasonCode    : 8;\r
    UINT32    Reserved1     : 8;\r
    UINT32    Reserved2     : 32;\r
  } GhcbTerminate;\r
\r
  struct {\r
    UINT64    Function : 12;\r
    UINT64    Features : 52;\r
  } GhcbHypervisorFeatures;\r
\r
  struct {\r
    UINT64    Function         : 12;\r
    UINT64    GuestFrameNumber : 52;\r
  } GhcbGpaRegister;\r
\r
  struct {\r
    UINT64    Function         : 12;\r
    UINT64    GuestFrameNumber : 40;\r
    UINT64    Operation        : 4;\r
    UINT64    Reserved         : 8;\r
  } SnpPageStateChangeRequest;\r
\r
  struct {\r
    UINT32    Function : 12;\r
    UINT32    Reserved : 20;\r
    UINT32    ErrorCode;\r
  } SnpPageStateChangeResponse;\r
\r
  VOID      *Ghcb;\r
\r
  UINT64    GhcbPhysicalAddress;\r
} MSR_SEV_ES_GHCB_REGISTER;\r
\r
#define GHCB_INFO_SEV_INFO                        1\r
#define GHCB_INFO_SEV_INFO_GET                    2\r
#define GHCB_INFO_CPUID_REQUEST                   4\r
#define GHCB_INFO_CPUID_RESPONSE                  5\r
#define GHCB_INFO_GHCB_GPA_REGISTER_REQUEST       18\r
#define GHCB_INFO_GHCB_GPA_REGISTER_RESPONSE      19\r
#define GHCB_INFO_SNP_PAGE_STATE_CHANGE_REQUEST   20\r
#define GHCB_INFO_SNP_PAGE_STATE_CHANGE_RESPONSE  21\r
#define GHCB_HYPERVISOR_FEATURES_REQUEST          128\r
#define GHCB_HYPERVISOR_FEATURES_RESPONSE         129\r
#define GHCB_INFO_TERMINATE_REQUEST               256\r
\r
#define GHCB_TERMINATE_GHCB           0\r
#define GHCB_TERMINATE_GHCB_GENERAL   0\r
#define GHCB_TERMINATE_GHCB_PROTOCOL  1\r
\r
/**\r
  Secure Encrypted Virtualization (SEV) status register\r
\r
**/\r
#define MSR_SEV_STATUS  0xc0010131\r
\r
/**\r
  MSR information returned for #MSR_SEV_STATUS\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Secure Encrypted Virtualization (Sev) is enabled\r
    ///\r
    UINT32    SevBit    : 1;\r
\r
    ///\r
    /// [Bit 1] Secure Encrypted Virtualization Encrypted State (SevEs) is enabled\r
    ///\r
    UINT32    SevEsBit  : 1;\r
\r
    ///\r
    /// [Bit 2] Secure Nested Paging (SevSnp) is enabled\r
    ///\r
    UINT32    SevSnpBit : 1;\r
\r
    UINT32    Reserved2 : 29;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64    Uint64;\r
} MSR_SEV_STATUS_REGISTER;\r
\r
#endif\r