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236d5c66 RN |
1 | /** @file\r |
2 | Intel CPUID leaf definitions.\r | |
3 | \r | |
4 | Provides defines for CPUID leaf indexes. Data structures are provided for\r | |
5 | registers returned by a CPUID leaf that contain one or more bit fields.\r | |
6 | If a register returned is a single 32-bit value, then a data structure is\r | |
7 | not provided for that register.\r | |
8 | \r | |
0bbc2072 | 9 | Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.<BR>\r |
236d5c66 RN |
10 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
11 | \r | |
12 | @par Specification Reference:\r | |
13 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A,\r | |
14 | November 2018, CPUID instruction.\r | |
15 | \r | |
16 | **/\r | |
17 | \r | |
18 | #ifndef __INTEL_CPUID_H__\r | |
19 | #define __INTEL_CPUID_H__\r | |
20 | \r | |
21 | /**\r | |
22 | CPUID Signature Information\r | |
23 | \r | |
24 | @param EAX CPUID_SIGNATURE (0x00)\r | |
25 | \r | |
26 | @retval EAX Returns the highest value the CPUID instruction recognizes for\r | |
27 | returning basic processor information. The value is returned is\r | |
28 | processor specific.\r | |
29 | @retval EBX First 4 characters of a vendor identification string.\r | |
30 | @retval ECX Last 4 characters of a vendor identification string.\r | |
31 | @retval EDX Middle 4 characters of a vendor identification string.\r | |
32 | \r | |
33 | <b>Example usage</b>\r | |
34 | @code\r | |
35 | UINT32 Eax;\r | |
36 | UINT32 Ebx;\r | |
37 | UINT32 Ecx;\r | |
38 | UINT32 Edx;\r | |
39 | \r | |
40 | AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);\r | |
41 | @endcode\r | |
42 | **/\r | |
2f88bd3a | 43 | #define CPUID_SIGNATURE 0x00\r |
236d5c66 RN |
44 | \r |
45 | ///\r | |
46 | /// @{ CPUID signature values returned by Intel processors\r | |
47 | ///\r | |
48 | #define CPUID_SIGNATURE_GENUINE_INTEL_EBX SIGNATURE_32 ('G', 'e', 'n', 'u')\r | |
49 | #define CPUID_SIGNATURE_GENUINE_INTEL_EDX SIGNATURE_32 ('i', 'n', 'e', 'I')\r | |
50 | #define CPUID_SIGNATURE_GENUINE_INTEL_ECX SIGNATURE_32 ('n', 't', 'e', 'l')\r | |
51 | ///\r | |
52 | /// @}\r | |
53 | ///\r | |
54 | \r | |
236d5c66 RN |
55 | /**\r |
56 | CPUID Version Information\r | |
57 | \r | |
58 | @param EAX CPUID_VERSION_INFO (0x01)\r | |
59 | \r | |
60 | @retval EAX Returns Model, Family, Stepping Information described by the\r | |
61 | type CPUID_VERSION_INFO_EAX.\r | |
62 | @retval EBX Returns Brand, Cache Line Size, and Initial APIC ID described by\r | |
63 | the type CPUID_VERSION_INFO_EBX.\r | |
64 | @retval ECX CPU Feature Information described by the type\r | |
65 | CPUID_VERSION_INFO_ECX.\r | |
66 | @retval EDX CPU Feature Information described by the type\r | |
67 | CPUID_VERSION_INFO_EDX.\r | |
68 | \r | |
69 | <b>Example usage</b>\r | |
70 | @code\r | |
71 | CPUID_VERSION_INFO_EAX Eax;\r | |
72 | CPUID_VERSION_INFO_EBX Ebx;\r | |
73 | CPUID_VERSION_INFO_ECX Ecx;\r | |
74 | CPUID_VERSION_INFO_EDX Edx;\r | |
75 | \r | |
76 | AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r | |
77 | @endcode\r | |
78 | **/\r | |
2f88bd3a | 79 | #define CPUID_VERSION_INFO 0x01\r |
236d5c66 RN |
80 | \r |
81 | /**\r | |
82 | CPUID Version Information returned in EAX for CPUID leaf\r | |
83 | #CPUID_VERSION_INFO.\r | |
84 | **/\r | |
85 | typedef union {\r | |
86 | ///\r | |
87 | /// Individual bit fields\r | |
88 | ///\r | |
89 | struct {\r | |
2f88bd3a MK |
90 | UINT32 SteppingId : 4; ///< [Bits 3:0] Stepping ID\r |
91 | UINT32 Model : 4; ///< [Bits 7:4] Model\r | |
92 | UINT32 FamilyId : 4; ///< [Bits 11:8] Family\r | |
93 | UINT32 ProcessorType : 2; ///< [Bits 13:12] Processor Type\r | |
94 | UINT32 Reserved1 : 2; ///< [Bits 15:14] Reserved\r | |
95 | UINT32 ExtendedModelId : 4; ///< [Bits 19:16] Extended Model ID\r | |
96 | UINT32 ExtendedFamilyId : 8; ///< [Bits 27:20] Extended Family ID\r | |
97 | UINT32 Reserved2 : 4; ///< Reserved\r | |
236d5c66 RN |
98 | } Bits;\r |
99 | ///\r | |
100 | /// All bit fields as a 32-bit value\r | |
101 | ///\r | |
102 | UINT32 Uint32;\r | |
103 | } CPUID_VERSION_INFO_EAX;\r | |
104 | \r | |
105 | ///\r | |
106 | /// @{ Define value for bit field CPUID_VERSION_INFO_EAX.ProcessorType\r | |
107 | ///\r | |
108 | #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_ORIGINAL_OEM_PROCESSOR 0x00\r | |
109 | #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_INTEL_OVERDRIVE_PROCESSOR 0x01\r | |
110 | #define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_DUAL_PROCESSOR 0x02\r | |
111 | ///\r | |
112 | /// @}\r | |
113 | ///\r | |
114 | \r | |
115 | /**\r | |
116 | CPUID Version Information returned in EBX for CPUID leaf\r | |
117 | #CPUID_VERSION_INFO.\r | |
118 | **/\r | |
119 | typedef union {\r | |
120 | ///\r | |
121 | /// Individual bit fields\r | |
122 | ///\r | |
123 | struct {\r | |
124 | ///\r | |
125 | /// [Bits 7:0] Provides an entry into a brand string table that contains\r | |
126 | /// brand strings for IA-32 processors.\r | |
127 | ///\r | |
2f88bd3a | 128 | UINT32 BrandIndex : 8;\r |
236d5c66 RN |
129 | ///\r |
130 | /// [Bits 15:8] Indicates the size of the cache line flushed by the CLFLUSH\r | |
131 | /// and CLFLUSHOPT instructions in 8-byte increments. This field was\r | |
132 | /// introduced in the Pentium 4 processor.\r | |
133 | ///\r | |
2f88bd3a | 134 | UINT32 CacheLineSize : 8;\r |
236d5c66 RN |
135 | ///\r |
136 | /// [Bits 23:16] Maximum number of addressable IDs for logical processors\r | |
137 | /// in this physical package.\r | |
138 | ///\r | |
139 | /// @note\r | |
140 | /// The nearest power-of-2 integer that is not smaller than EBX[23:16] is\r | |
141 | /// the number of unique initial APICIDs reserved for addressing different\r | |
142 | /// logical processors in a physical package. This field is only valid if\r | |
143 | /// CPUID.1.EDX.HTT[bit 28]= 1.\r | |
144 | ///\r | |
2f88bd3a | 145 | UINT32 MaximumAddressableIdsForLogicalProcessors : 8;\r |
236d5c66 RN |
146 | ///\r |
147 | /// [Bits 31:24] The 8-bit ID that is assigned to the local APIC on the\r | |
148 | /// processor during power up. This field was introduced in the Pentium 4\r | |
149 | /// processor.\r | |
150 | ///\r | |
2f88bd3a | 151 | UINT32 InitialLocalApicId : 8;\r |
236d5c66 RN |
152 | } Bits;\r |
153 | ///\r | |
154 | /// All bit fields as a 32-bit value\r | |
155 | ///\r | |
156 | UINT32 Uint32;\r | |
157 | } CPUID_VERSION_INFO_EBX;\r | |
158 | \r | |
159 | /**\r | |
160 | CPUID Version Information returned in ECX for CPUID leaf\r | |
161 | #CPUID_VERSION_INFO.\r | |
162 | **/\r | |
163 | typedef union {\r | |
164 | ///\r | |
165 | /// Individual bit fields\r | |
166 | ///\r | |
167 | struct {\r | |
168 | ///\r | |
169 | /// [Bit 0] Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the\r | |
170 | /// processor supports this technology\r | |
171 | ///\r | |
2f88bd3a | 172 | UINT32 SSE3 : 1;\r |
236d5c66 RN |
173 | ///\r |
174 | /// [Bit 1] A value of 1 indicates the processor supports the PCLMULQDQ\r | |
175 | /// instruction. Carryless Multiplication\r | |
176 | ///\r | |
2f88bd3a | 177 | UINT32 PCLMULQDQ : 1;\r |
236d5c66 RN |
178 | ///\r |
179 | /// [Bit 2] 64-bit DS Area. A value of 1 indicates the processor supports\r | |
180 | /// DS area using 64-bit layout.\r | |
181 | ///\r | |
2f88bd3a | 182 | UINT32 DTES64 : 1;\r |
236d5c66 RN |
183 | ///\r |
184 | /// [Bit 3] MONITOR/MWAIT. A value of 1 indicates the processor supports\r | |
185 | /// this feature.\r | |
186 | ///\r | |
2f88bd3a | 187 | UINT32 MONITOR : 1;\r |
236d5c66 RN |
188 | ///\r |
189 | /// [Bit 4] CPL Qualified Debug Store. A value of 1 indicates the processor\r | |
190 | /// supports the extensions to the Debug Store feature to allow for branch\r | |
191 | /// message storage qualified by CPL\r | |
192 | ///\r | |
2f88bd3a | 193 | UINT32 DS_CPL : 1;\r |
236d5c66 RN |
194 | ///\r |
195 | /// [Bit 5] Virtual Machine Extensions. A value of 1 indicates that the\r | |
196 | /// processor supports this technology.\r | |
197 | ///\r | |
2f88bd3a | 198 | UINT32 VMX : 1;\r |
236d5c66 RN |
199 | ///\r |
200 | /// [Bit 6] Safer Mode Extensions. A value of 1 indicates that the processor\r | |
201 | /// supports this technology\r | |
202 | ///\r | |
2f88bd3a | 203 | UINT32 SMX : 1;\r |
236d5c66 RN |
204 | ///\r |
205 | /// [Bit 7] Enhanced Intel SpeedStep(R) technology. A value of 1 indicates\r | |
206 | /// that the processor supports this technology\r | |
207 | ///\r | |
2f88bd3a | 208 | UINT32 EIST : 1;\r |
236d5c66 RN |
209 | ///\r |
210 | /// [Bit 8] Thermal Monitor 2. A value of 1 indicates whether the processor\r | |
211 | /// supports this technology\r | |
212 | ///\r | |
2f88bd3a | 213 | UINT32 TM2 : 1;\r |
236d5c66 RN |
214 | ///\r |
215 | /// [Bit 9] A value of 1 indicates the presence of the Supplemental Streaming\r | |
216 | /// SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction\r | |
217 | /// extensions are not present in the processor.\r | |
218 | ///\r | |
2f88bd3a | 219 | UINT32 SSSE3 : 1;\r |
236d5c66 RN |
220 | ///\r |
221 | /// [Bit 10] L1 Context ID. A value of 1 indicates the L1 data cache mode\r | |
222 | /// can be set to either adaptive mode or shared mode. A value of 0 indicates\r | |
223 | /// this feature is not supported. See definition of the IA32_MISC_ENABLE MSR\r | |
224 | /// Bit 24 (L1 Data Cache Context Mode) for details\r | |
225 | ///\r | |
2f88bd3a | 226 | UINT32 CNXT_ID : 1;\r |
236d5c66 RN |
227 | ///\r |
228 | /// [Bit 11] A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE\r | |
229 | /// MSR for silicon debug\r | |
230 | ///\r | |
2f88bd3a | 231 | UINT32 SDBG : 1;\r |
236d5c66 RN |
232 | ///\r |
233 | /// [Bit 12] A value of 1 indicates the processor supports FMA (Fused Multiple\r | |
234 | /// Add) extensions using YMM state.\r | |
235 | ///\r | |
2f88bd3a | 236 | UINT32 FMA : 1;\r |
236d5c66 RN |
237 | ///\r |
238 | /// [Bit 13] CMPXCHG16B Available. A value of 1 indicates that the feature\r | |
239 | /// is available.\r | |
240 | ///\r | |
2f88bd3a | 241 | UINT32 CMPXCHG16B : 1;\r |
236d5c66 RN |
242 | ///\r |
243 | /// [Bit 14] xTPR Update Control. A value of 1 indicates that the processor\r | |
244 | /// supports changing IA32_MISC_ENABLE[Bit 23].\r | |
245 | ///\r | |
2f88bd3a | 246 | UINT32 xTPR_Update_Control : 1;\r |
236d5c66 RN |
247 | ///\r |
248 | /// [Bit 15] Perfmon and Debug Capability: A value of 1 indicates the\r | |
249 | /// processor supports the performance and debug feature indication MSR\r | |
250 | /// IA32_PERF_CAPABILITIES.\r | |
251 | ///\r | |
2f88bd3a MK |
252 | UINT32 PDCM : 1;\r |
253 | UINT32 Reserved : 1;\r | |
236d5c66 RN |
254 | ///\r |
255 | /// [Bit 17] Process-context identifiers. A value of 1 indicates that the\r | |
256 | /// processor supports PCIDs and that software may set CR4.PCIDE to 1.\r | |
257 | ///\r | |
2f88bd3a | 258 | UINT32 PCID : 1;\r |
236d5c66 RN |
259 | ///\r |
260 | /// [Bit 18] A value of 1 indicates the processor supports the ability to\r | |
261 | /// prefetch data from a memory mapped device. Direct Cache Access.\r | |
262 | ///\r | |
2f88bd3a | 263 | UINT32 DCA : 1;\r |
236d5c66 RN |
264 | ///\r |
265 | /// [Bit 19] A value of 1 indicates that the processor supports SSE4.1.\r | |
266 | ///\r | |
2f88bd3a | 267 | UINT32 SSE4_1 : 1;\r |
236d5c66 RN |
268 | ///\r |
269 | /// [Bit 20] A value of 1 indicates that the processor supports SSE4.2.\r | |
270 | ///\r | |
2f88bd3a | 271 | UINT32 SSE4_2 : 1;\r |
236d5c66 RN |
272 | ///\r |
273 | /// [Bit 21] A value of 1 indicates that the processor supports x2APIC\r | |
274 | /// feature.\r | |
275 | ///\r | |
2f88bd3a | 276 | UINT32 x2APIC : 1;\r |
236d5c66 RN |
277 | ///\r |
278 | /// [Bit 22] A value of 1 indicates that the processor supports MOVBE\r | |
279 | /// instruction.\r | |
280 | ///\r | |
2f88bd3a | 281 | UINT32 MOVBE : 1;\r |
236d5c66 RN |
282 | ///\r |
283 | /// [Bit 23] A value of 1 indicates that the processor supports the POPCNT\r | |
284 | /// instruction.\r | |
285 | ///\r | |
2f88bd3a | 286 | UINT32 POPCNT : 1;\r |
236d5c66 RN |
287 | ///\r |
288 | /// [Bit 24] A value of 1 indicates that the processor's local APIC timer\r | |
289 | /// supports one-shot operation using a TSC deadline value.\r | |
290 | ///\r | |
2f88bd3a | 291 | UINT32 TSC_Deadline : 1;\r |
236d5c66 RN |
292 | ///\r |
293 | /// [Bit 25] A value of 1 indicates that the processor supports the AESNI\r | |
294 | /// instruction extensions.\r | |
295 | ///\r | |
2f88bd3a | 296 | UINT32 AESNI : 1;\r |
236d5c66 RN |
297 | ///\r |
298 | /// [Bit 26] A value of 1 indicates that the processor supports the\r | |
299 | /// XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV\r | |
300 | /// instructions, and XCR0.\r | |
301 | ///\r | |
2f88bd3a | 302 | UINT32 XSAVE : 1;\r |
236d5c66 RN |
303 | ///\r |
304 | /// [Bit 27] A value of 1 indicates that the OS has set CR4.OSXSAVE[Bit 18]\r | |
305 | /// to enable XSETBV/XGETBV instructions to access XCR0 and to support\r | |
306 | /// processor extended state management using XSAVE/XRSTOR.\r | |
307 | ///\r | |
2f88bd3a | 308 | UINT32 OSXSAVE : 1;\r |
236d5c66 RN |
309 | ///\r |
310 | /// [Bit 28] A value of 1 indicates the processor supports the AVX instruction\r | |
311 | /// extensions.\r | |
312 | ///\r | |
2f88bd3a | 313 | UINT32 AVX : 1;\r |
236d5c66 RN |
314 | ///\r |
315 | /// [Bit 29] A value of 1 indicates that processor supports 16-bit\r | |
316 | /// floating-point conversion instructions.\r | |
317 | ///\r | |
2f88bd3a | 318 | UINT32 F16C : 1;\r |
236d5c66 RN |
319 | ///\r |
320 | /// [Bit 30] A value of 1 indicates that processor supports RDRAND instruction.\r | |
321 | ///\r | |
2f88bd3a | 322 | UINT32 RDRAND : 1;\r |
236d5c66 RN |
323 | ///\r |
324 | /// [Bit 31] Always returns 0.\r | |
325 | ///\r | |
2f88bd3a | 326 | UINT32 NotUsed : 1;\r |
236d5c66 RN |
327 | } Bits;\r |
328 | ///\r | |
329 | /// All bit fields as a 32-bit value\r | |
330 | ///\r | |
331 | UINT32 Uint32;\r | |
332 | } CPUID_VERSION_INFO_ECX;\r | |
333 | \r | |
334 | /**\r | |
335 | CPUID Version Information returned in EDX for CPUID leaf\r | |
336 | #CPUID_VERSION_INFO.\r | |
337 | **/\r | |
338 | typedef union {\r | |
339 | ///\r | |
340 | /// Individual bit fields\r | |
341 | ///\r | |
342 | struct {\r | |
343 | ///\r | |
344 | /// [Bit 0] Floating Point Unit On-Chip. The processor contains an x87 FPU.\r | |
345 | ///\r | |
2f88bd3a | 346 | UINT32 FPU : 1;\r |
236d5c66 RN |
347 | ///\r |
348 | /// [Bit 1] Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements,\r | |
349 | /// including CR4.VME for controlling the feature, CR4.PVI for protected\r | |
350 | /// mode virtual interrupts, software interrupt indirection, expansion of\r | |
351 | /// the TSS with the software indirection bitmap, and EFLAGS.VIF and\r | |
352 | /// EFLAGS.VIP flags.\r | |
353 | ///\r | |
2f88bd3a | 354 | UINT32 VME : 1;\r |
236d5c66 RN |
355 | ///\r |
356 | /// [Bit 2] Debugging Extensions. Support for I/O breakpoints, including\r | |
357 | /// CR4.DE for controlling the feature, and optional trapping of accesses to\r | |
358 | /// DR4 and DR5.\r | |
359 | ///\r | |
2f88bd3a | 360 | UINT32 DE : 1;\r |
236d5c66 RN |
361 | ///\r |
362 | /// [Bit 3] Page Size Extension. Large pages of size 4 MByte are supported,\r | |
363 | /// including CR4.PSE for controlling the feature, the defined dirty bit in\r | |
364 | /// PDE (Page Directory Entries), optional reserved bit trapping in CR3,\r | |
365 | /// PDEs, and PTEs.\r | |
366 | ///\r | |
2f88bd3a | 367 | UINT32 PSE : 1;\r |
236d5c66 RN |
368 | ///\r |
369 | /// [Bit 4] Time Stamp Counter. The RDTSC instruction is supported,\r | |
370 | /// including CR4.TSD for controlling privilege.\r | |
371 | ///\r | |
2f88bd3a | 372 | UINT32 TSC : 1;\r |
236d5c66 RN |
373 | ///\r |
374 | /// [Bit 5] Model Specific Registers RDMSR and WRMSR Instructions. The\r | |
375 | /// RDMSR and WRMSR instructions are supported. Some of the MSRs are\r | |
376 | /// implementation dependent.\r | |
377 | ///\r | |
2f88bd3a | 378 | UINT32 MSR : 1;\r |
236d5c66 RN |
379 | ///\r |
380 | /// [Bit 6] Physical Address Extension. Physical addresses greater than 32\r | |
381 | /// bits are supported: extended page table entry formats, an extra level in\r | |
382 | /// the page translation tables is defined, 2-MByte pages are supported\r | |
383 | /// instead of 4 Mbyte pages if PAE bit is 1.\r | |
384 | ///\r | |
2f88bd3a | 385 | UINT32 PAE : 1;\r |
236d5c66 RN |
386 | ///\r |
387 | /// [Bit 7] Machine Check Exception. Exception 18 is defined for Machine\r | |
388 | /// Checks, including CR4.MCE for controlling the feature. This feature does\r | |
389 | /// not define the model-specific implementations of machine-check error\r | |
390 | /// logging, reporting, and processor shutdowns. Machine Check exception\r | |
391 | /// handlers may have to depend on processor version to do model specific\r | |
392 | /// processing of the exception, or test for the presence of the Machine\r | |
393 | /// Check feature.\r | |
394 | ///\r | |
2f88bd3a | 395 | UINT32 MCE : 1;\r |
236d5c66 RN |
396 | ///\r |
397 | /// [Bit 8] CMPXCHG8B Instruction. The compare-and-exchange 8 bytes(64 bits)\r | |
398 | /// instruction is supported (implicitly locked and atomic).\r | |
399 | ///\r | |
2f88bd3a | 400 | UINT32 CX8 : 1;\r |
236d5c66 RN |
401 | ///\r |
402 | /// [Bit 9] APIC On-Chip. The processor contains an Advanced Programmable\r | |
403 | /// Interrupt Controller (APIC), responding to memory mapped commands in the\r | |
404 | /// physical address range FFFE0000H to FFFE0FFFH (by default - some\r | |
405 | /// processors permit the APIC to be relocated).\r | |
406 | ///\r | |
2f88bd3a MK |
407 | UINT32 APIC : 1;\r |
408 | UINT32 Reserved1 : 1;\r | |
236d5c66 RN |
409 | ///\r |
410 | /// [Bit 11] SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT\r | |
411 | /// and associated MSRs are supported.\r | |
412 | ///\r | |
2f88bd3a | 413 | UINT32 SEP : 1;\r |
236d5c66 RN |
414 | ///\r |
415 | /// [Bit 12] Memory Type Range Registers. MTRRs are supported. The MTRRcap\r | |
416 | /// MSR contains feature bits that describe what memory types are supported,\r | |
417 | /// how many variable MTRRs are supported, and whether fixed MTRRs are\r | |
418 | /// supported.\r | |
419 | ///\r | |
2f88bd3a | 420 | UINT32 MTRR : 1;\r |
236d5c66 RN |
421 | ///\r |
422 | /// [Bit 13] Page Global Bit. The global bit is supported in paging-structure\r | |
423 | /// entries that map a page, indicating TLB entries that are common to\r | |
424 | /// different processes and need not be flushed. The CR4.PGE bit controls\r | |
425 | /// this feature.\r | |
426 | ///\r | |
2f88bd3a | 427 | UINT32 PGE : 1;\r |
236d5c66 RN |
428 | ///\r |
429 | /// [Bit 14] Machine Check Architecture. A value of 1 indicates the Machine\r | |
430 | /// Check Architecture of reporting machine errors is supported. The MCG_CAP\r | |
431 | /// MSR contains feature bits describing how many banks of error reporting\r | |
432 | /// MSRs are supported.\r | |
433 | ///\r | |
2f88bd3a | 434 | UINT32 MCA : 1;\r |
236d5c66 RN |
435 | ///\r |
436 | /// [Bit 15] Conditional Move Instructions. The conditional move instruction\r | |
437 | /// CMOV is supported. In addition, if x87 FPU is present as indicated by the\r | |
438 | /// CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported.\r | |
439 | ///\r | |
2f88bd3a | 440 | UINT32 CMOV : 1;\r |
236d5c66 RN |
441 | ///\r |
442 | /// [Bit 16] Page Attribute Table. Page Attribute Table is supported. This\r | |
443 | /// feature augments the Memory Type Range Registers (MTRRs), allowing an\r | |
444 | /// operating system to specify attributes of memory accessed through a\r | |
445 | /// linear address on a 4KB granularity.\r | |
446 | ///\r | |
2f88bd3a | 447 | UINT32 PAT : 1;\r |
236d5c66 RN |
448 | ///\r |
449 | /// [Bit 17] 36-Bit Page Size Extension. 4-MByte pages addressing physical\r | |
450 | /// memory beyond 4 GBytes are supported with 32-bit paging. This feature\r | |
451 | /// indicates that upper bits of the physical address of a 4-MByte page are\r | |
452 | /// encoded in bits 20:13 of the page-directory entry. Such physical\r | |
453 | /// addresses are limited by MAXPHYADDR and may be up to 40 bits in size.\r | |
454 | ///\r | |
2f88bd3a | 455 | UINT32 PSE_36 : 1;\r |
236d5c66 RN |
456 | ///\r |
457 | /// [Bit 18] Processor Serial Number. The processor supports the 96-bit\r | |
458 | /// processor identification number feature and the feature is enabled.\r | |
459 | ///\r | |
2f88bd3a | 460 | UINT32 PSN : 1;\r |
236d5c66 RN |
461 | ///\r |
462 | /// [Bit 19] CLFLUSH Instruction. CLFLUSH Instruction is supported.\r | |
463 | ///\r | |
2f88bd3a MK |
464 | UINT32 CLFSH : 1;\r |
465 | UINT32 Reserved2 : 1;\r | |
236d5c66 RN |
466 | ///\r |
467 | /// [Bit 21] Debug Store. The processor supports the ability to write debug\r | |
468 | /// information into a memory resident buffer. This feature is used by the\r | |
469 | /// branch trace store (BTS) and precise event-based sampling (PEBS)\r | |
470 | /// facilities.\r | |
471 | ///\r | |
2f88bd3a | 472 | UINT32 DS : 1;\r |
236d5c66 RN |
473 | ///\r |
474 | /// [Bit 22] Thermal Monitor and Software Controlled Clock Facilities. The\r | |
475 | /// processor implements internal MSRs that allow processor temperature to\r | |
476 | /// be monitored and processor performance to be modulated in predefined\r | |
477 | /// duty cycles under software control.\r | |
478 | ///\r | |
2f88bd3a | 479 | UINT32 ACPI : 1;\r |
236d5c66 RN |
480 | ///\r |
481 | /// [Bit 23] Intel MMX Technology. The processor supports the Intel MMX\r | |
482 | /// technology.\r | |
483 | ///\r | |
2f88bd3a | 484 | UINT32 MMX : 1;\r |
236d5c66 RN |
485 | ///\r |
486 | /// [Bit 24] FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR\r | |
487 | /// instructions are supported for fast save and restore of the floating\r | |
488 | /// point context. Presence of this bit also indicates that CR4.OSFXSR is\r | |
489 | /// available for an operating system to indicate that it supports the\r | |
490 | /// FXSAVE and FXRSTOR instructions.\r | |
491 | ///\r | |
2f88bd3a | 492 | UINT32 FXSR : 1;\r |
236d5c66 RN |
493 | ///\r |
494 | /// [Bit 25] SSE. The processor supports the SSE extensions.\r | |
495 | ///\r | |
2f88bd3a | 496 | UINT32 SSE : 1;\r |
236d5c66 RN |
497 | ///\r |
498 | /// [Bit 26] SSE2. The processor supports the SSE2 extensions.\r | |
499 | ///\r | |
2f88bd3a | 500 | UINT32 SSE2 : 1;\r |
236d5c66 RN |
501 | ///\r |
502 | /// [Bit 27] Self Snoop. The processor supports the management of\r | |
503 | /// conflicting memory types by performing a snoop of its own cache\r | |
504 | /// structure for transactions issued to the bus.\r | |
505 | ///\r | |
2f88bd3a | 506 | UINT32 SS : 1;\r |
236d5c66 RN |
507 | ///\r |
508 | /// [Bit 28] Max APIC IDs reserved field is Valid. A value of 0 for HTT\r | |
509 | /// indicates there is only a single logical processor in the package and\r | |
510 | /// software should assume only a single APIC ID is reserved. A value of 1\r | |
511 | /// for HTT indicates the value in CPUID.1.EBX[23:16] (the Maximum number of\r | |
512 | /// addressable IDs for logical processors in this package) is valid for the\r | |
513 | /// package.\r | |
514 | ///\r | |
2f88bd3a | 515 | UINT32 HTT : 1;\r |
236d5c66 RN |
516 | ///\r |
517 | /// [Bit 29] Thermal Monitor. The processor implements the thermal monitor\r | |
518 | /// automatic thermal control circuitry (TCC).\r | |
519 | ///\r | |
2f88bd3a MK |
520 | UINT32 TM : 1;\r |
521 | UINT32 Reserved3 : 1;\r | |
236d5c66 RN |
522 | ///\r |
523 | /// [Bit 31] Pending Break Enable. The processor supports the use of the\r | |
524 | /// FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is\r | |
525 | /// asserted) to signal the processor that an interrupt is pending and that\r | |
526 | /// the processor should return to normal operation to handle the interrupt.\r | |
527 | /// Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability.\r | |
528 | ///\r | |
2f88bd3a | 529 | UINT32 PBE : 1;\r |
236d5c66 RN |
530 | } Bits;\r |
531 | ///\r | |
532 | /// All bit fields as a 32-bit value\r | |
533 | ///\r | |
534 | UINT32 Uint32;\r | |
535 | } CPUID_VERSION_INFO_EDX;\r | |
536 | \r | |
236d5c66 RN |
537 | /**\r |
538 | CPUID Cache and TLB Information\r | |
539 | \r | |
540 | @param EAX CPUID_CACHE_INFO (0x02)\r | |
541 | \r | |
542 | @retval EAX Cache and TLB Information described by the type\r | |
543 | CPUID_CACHE_INFO_CACHE_TLB.\r | |
544 | CPUID_CACHE_INFO_CACHE_TLB.CacheDescriptor[0] always returns\r | |
545 | 0x01 and must be ignored. Only valid if\r | |
546 | CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.\r | |
547 | @retval EBX Cache and TLB Information described by the type\r | |
548 | CPUID_CACHE_INFO_CACHE_TLB. Only valid if\r | |
549 | CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.\r | |
550 | @retval ECX Cache and TLB Information described by the type\r | |
551 | CPUID_CACHE_INFO_CACHE_TLB. Only valid if\r | |
552 | CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.\r | |
553 | @retval EDX Cache and TLB Information described by the type\r | |
554 | CPUID_CACHE_INFO_CACHE_TLB. Only valid if\r | |
555 | CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.\r | |
556 | \r | |
557 | <b>Example usage</b>\r | |
558 | @code\r | |
559 | CPUID_CACHE_INFO_CACHE_TLB Eax;\r | |
560 | CPUID_CACHE_INFO_CACHE_TLB Ebx;\r | |
561 | CPUID_CACHE_INFO_CACHE_TLB Ecx;\r | |
562 | CPUID_CACHE_INFO_CACHE_TLB Edx;\r | |
563 | \r | |
564 | AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r | |
565 | @endcode\r | |
566 | \r | |
567 | <b>Cache Descriptor values</b>\r | |
568 | <table>\r | |
569 | <tr><th>Value </th><th> Type </th><th> Description </th></tr>\r | |
570 | <tr><td> 0x00 </td><td> General </td><td> Null descriptor, this byte contains no information</td></tr>\r | |
571 | <tr><td> 0x01 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries</td></tr>\r | |
572 | <tr><td> 0x02 </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, fully associative, 2 entries</td></tr>\r | |
573 | <tr><td> 0x03 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 64 entries</td></tr>\r | |
574 | <tr><td> 0x04 </td><td> TLB </td><td> Data TLB: 4 MByte pages, 4-way set associative, 8 entries</td></tr>\r | |
575 | <tr><td> 0x05 </td><td> TLB </td><td> Data TLB1: 4 MByte pages, 4-way set associative, 32 entries</td></tr>\r | |
576 | <tr><td> 0x06 </td><td> Cache </td><td> 1st-level instruction cache: 8 KBytes, 4-way set associative,\r | |
577 | 32 byte line size</td></tr>\r | |
578 | <tr><td> 0x08 </td><td> Cache </td><td> 1st-level instruction cache: 16 KBytes, 4-way set associative,\r | |
579 | 32 byte line size</td></tr>\r | |
580 | <tr><td> 0x09 </td><td> Cache </td><td> 1st-level instruction cache: 32KBytes, 4-way set associative,\r | |
581 | 64 byte line size</td></tr>\r | |
582 | <tr><td> 0x0A </td><td> Cache </td><td> 1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size</td></tr>\r | |
583 | <tr><td> 0x0B </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries</td></tr>\r | |
584 | <tr><td> 0x0C </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size</td></tr>\r | |
585 | <tr><td> 0x0D </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size</td></tr>\r | |
586 | <tr><td> 0x0E </td><td> Cache </td><td> 1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size</td></tr>\r | |
587 | <tr><td> 0x1D </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size</td></tr>\r | |
588 | <tr><td> 0x21 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size</td></tr>\r | |
589 | <tr><td> 0x22 </td><td> Cache </td><td> 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size,\r | |
590 | 2 lines per sector</td></tr>\r | |
591 | <tr><td> 0x23 </td><td> Cache </td><td> 3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size,\r | |
592 | 2 lines per sector</td></tr>\r | |
593 | <tr><td> 0x24 </td><td> Cache </td><td> 2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size</td></tr>\r | |
594 | <tr><td> 0x25 </td><td> Cache </td><td> 3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size,\r | |
595 | 2 lines per sector</td></tr>\r | |
596 | <tr><td> 0x29 </td><td> Cache </td><td> 3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size,\r | |
597 | 2 lines per sector</td></tr>\r | |
598 | <tr><td> 0x2C </td><td> Cache </td><td> 1st-level data cache: 32 KBytes, 8-way set associative,\r | |
599 | 64 byte line size</td></tr>\r | |
600 | <tr><td> 0x30 </td><td> Cache </td><td> 1st-level instruction cache: 32 KBytes, 8-way set associative,\r | |
601 | 64 byte line size</td></tr>\r | |
602 | <tr><td> 0x40 </td><td> Cache </td><td> No 2nd-level cache or, if processor contains a valid 2nd-level cache,\r | |
603 | no 3rd-level cache</td></tr>\r | |
604 | <tr><td> 0x41 </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size</td></tr>\r | |
605 | <tr><td> 0x42 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size</td></tr>\r | |
606 | <tr><td> 0x43 </td><td> Cache </td><td> 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size</td></tr>\r | |
607 | <tr><td> 0x44 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size</td></tr>\r | |
608 | <tr><td> 0x45 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size</td></tr>\r | |
609 | <tr><td> 0x46 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size</td></tr>\r | |
610 | <tr><td> 0x47 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size</td></tr>\r | |
611 | <tr><td> 0x48 </td><td> Cache </td><td> 2nd-level cache: 3MByte, 12-way set associative, 64 byte line size</td></tr>\r | |
612 | <tr><td> 0x49 </td><td> Cache </td><td> 3rd-level cache: 4MB, 16-way set associative, 64-byte line size\r | |
613 | (Intel Xeon processor MP, Family 0FH, Model 06H)<BR>\r | |
614 | 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>\r | |
615 | <tr><td> 0x4A </td><td> Cache </td><td> 3rd-level cache: 6MByte, 12-way set associative, 64 byte line size</td></tr>\r | |
616 | <tr><td> 0x4B </td><td> Cache </td><td> 3rd-level cache: 8MByte, 16-way set associative, 64 byte line size</td></tr>\r | |
617 | <tr><td> 0x4C </td><td> Cache </td><td> 3rd-level cache: 12MByte, 12-way set associative, 64 byte line size</td></tr>\r | |
618 | <tr><td> 0x4D </td><td> Cache </td><td> 3rd-level cache: 16MByte, 16-way set associative, 64 byte line size</td></tr>\r | |
619 | <tr><td> 0x4E </td><td> Cache </td><td> 2nd-level cache: 6MByte, 24-way set associative, 64 byte line size</td></tr>\r | |
620 | <tr><td> 0x4F </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 32 entries</td></tr>\r | |
621 | <tr><td> 0x50 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries</td></tr>\r | |
622 | <tr><td> 0x51 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries</td></tr>\r | |
623 | <tr><td> 0x52 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries</td></tr>\r | |
624 | <tr><td> 0x55 </td><td> TLB </td><td> Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries</td></tr>\r | |
625 | <tr><td> 0x56 </td><td> TLB </td><td> Data TLB0: 4 MByte pages, 4-way set associative, 16 entries</td></tr>\r | |
626 | <tr><td> 0x57 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, 4-way associative, 16 entries</td></tr>\r | |
627 | <tr><td> 0x59 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, fully associative, 16 entries</td></tr>\r | |
628 | <tr><td> 0x5A </td><td> TLB </td><td> Data TLB0: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries</td></tr>\r | |
629 | <tr><td> 0x5B </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 64 entries</td></tr>\r | |
630 | <tr><td> 0x5C </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,128 entries</td></tr>\r | |
631 | <tr><td> 0x5D </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,256 entries</td></tr>\r | |
632 | <tr><td> 0x60 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size</td></tr>\r | |
633 | <tr><td> 0x61 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, fully associative, 48 entries</td></tr>\r | |
634 | <tr><td> 0x63 </td><td> TLB </td><td> Data TLB: 2 MByte or 4 MByte pages, 4-way set associative,\r | |
635 | 32 entries and a separate array with 1 GByte pages, 4-way set associative,\r | |
636 | 4 entries</td></tr>\r | |
637 | <tr><td> 0x64 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 512 entries</td></tr>\r | |
638 | <tr><td> 0x66 </td><td> Cache </td><td> 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size</td></tr>\r | |
639 | <tr><td> 0x67 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size</td></tr>\r | |
640 | <tr><td> 0x68 </td><td> Cache </td><td> 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size</td></tr>\r | |
641 | <tr><td> 0x6A </td><td> Cache </td><td> uTLB: 4 KByte pages, 8-way set associative, 64 entries</td></tr>\r | |
642 | <tr><td> 0x6B </td><td> Cache </td><td> DTLB: 4 KByte pages, 8-way set associative, 256 entries</td></tr>\r | |
643 | <tr><td> 0x6C </td><td> Cache </td><td> DTLB: 2M/4M pages, 8-way set associative, 128 entries</td></tr>\r | |
644 | <tr><td> 0x6D </td><td> Cache </td><td> DTLB: 1 GByte pages, fully associative, 16 entries</td></tr>\r | |
645 | <tr><td> 0x70 </td><td> Cache </td><td> Trace cache: 12 K-uop, 8-way set associative</td></tr>\r | |
646 | <tr><td> 0x71 </td><td> Cache </td><td> Trace cache: 16 K-uop, 8-way set associative</td></tr>\r | |
647 | <tr><td> 0x72 </td><td> Cache </td><td> Trace cache: 32 K-uop, 8-way set associative</td></tr>\r | |
648 | <tr><td> 0x76 </td><td> TLB </td><td> Instruction TLB: 2M/4M pages, fully associative, 8 entries</td></tr>\r | |
649 | <tr><td> 0x78 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 64byte line size</td></tr>\r | |
650 | <tr><td> 0x79 </td><td> Cache </td><td> 2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size,\r | |
651 | 2 lines per sector</td></tr>\r | |
652 | <tr><td> 0x7A </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size,\r | |
653 | 2 lines per sector</td></tr>\r | |
654 | <tr><td> 0x7B </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size,\r | |
655 | 2 lines per sector</td></tr>\r | |
656 | <tr><td> 0x7C </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size,\r | |
657 | 2 lines per sector</td></tr>\r | |
658 | <tr><td> 0x7D </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 64byte line size</td></tr>\r | |
659 | <tr><td> 0x7F </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size</td></tr>\r | |
660 | <tr><td> 0x80 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size</td></tr>\r | |
661 | <tr><td> 0x82 </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size</td></tr>\r | |
662 | <tr><td> 0x83 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size</td></tr>\r | |
663 | <tr><td> 0x84 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size</td></tr>\r | |
664 | <tr><td> 0x85 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size</td></tr>\r | |
665 | <tr><td> 0x86 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>\r | |
666 | <tr><td> 0x87 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>\r | |
667 | <tr><td> 0xA0 </td><td> DTLB </td><td> DTLB: 4k pages, fully associative, 32 entries</td></tr>\r | |
668 | <tr><td> 0xB0 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>\r | |
669 | <tr><td> 0xB1 </td><td> TLB </td><td> Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries</td></tr>\r | |
670 | <tr><td> 0xB2 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 4-way set associative, 64 entries</td></tr>\r | |
671 | <tr><td> 0xB3 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>\r | |
672 | <tr><td> 0xB4 </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 256 entries</td></tr>\r | |
673 | <tr><td> 0xB5 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative, 64 entries</td></tr>\r | |
674 | <tr><td> 0xB6 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative,\r | |
675 | 128 entries</td></tr>\r | |
676 | <tr><td> 0xBA </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 64 entries</td></tr>\r | |
677 | <tr><td> 0xC0 </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries</td></tr>\r | |
678 | <tr><td> 0xC1 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative,\r | |
679 | 1024 entries</td></tr>\r | |
680 | <tr><td> 0xC2 </td><td> DTLB </td><td> DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries</td></tr>\r | |
681 | <tr><td> 0xC3 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative,\r | |
682 | 1536 entries. Also 1GBbyte pages, 4-way, 16 entries.</td></tr>\r | |
683 | <tr><td> 0xC4 </td><td> DTLB </td><td> DTLB: 2M/4M Byte pages, 4-way associative, 32 entries</td></tr>\r | |
684 | <tr><td> 0xCA </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries</td></tr>\r | |
685 | <tr><td> 0xD0 </td><td> Cache </td><td> 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>\r | |
686 | <tr><td> 0xD1 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size</td></tr>\r | |
687 | <tr><td> 0xD2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size</td></tr>\r | |
688 | <tr><td> 0xD6 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>\r | |
689 | <tr><td> 0xD7 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size</td></tr>\r | |
690 | <tr><td> 0xD8 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size</td></tr>\r | |
691 | <tr><td> 0xDC </td><td> Cache </td><td> 3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size</td></tr>\r | |
692 | <tr><td> 0xDD </td><td> Cache </td><td> 3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size</td></tr>\r | |
693 | <tr><td> 0xDE </td><td> Cache </td><td> 3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size</td></tr>\r | |
694 | <tr><td> 0xE2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size</td></tr>\r | |
695 | <tr><td> 0xE3 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>\r | |
696 | <tr><td> 0xE4 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size</td></tr>\r | |
697 | <tr><td> 0xEA </td><td> Cache </td><td> 3rd-level cache: 12MByte, 24-way set associative, 64 byte line size</td></tr>\r | |
698 | <tr><td> 0xEB </td><td> Cache </td><td> 3rd-level cache: 18MByte, 24-way set associative, 64 byte line size</td></tr>\r | |
699 | <tr><td> 0xEC </td><td> Cache </td><td> 3rd-level cache: 24MByte, 24-way set associative, 64 byte line size</td></tr>\r | |
700 | <tr><td> 0xF0 </td><td> Prefetch</td><td> 64-Byte prefetching</td></tr>\r | |
701 | <tr><td> 0xF1 </td><td> Prefetch</td><td> 128-Byte prefetching</td></tr>\r | |
702 | <tr><td> 0xFE </td><td> General </td><td> CPUID leaf 2 does not report TLB descriptor information; use CPUID\r | |
703 | leaf 18H to query TLB and other address translation parameters.</td></tr>\r | |
704 | <tr><td> 0xFF </td><td> General </td><td> CPUID leaf 2 does not report cache descriptor information,\r | |
705 | use CPUID leaf 4 to query cache parameters</td></tr>\r | |
706 | </table>\r | |
707 | **/\r | |
2f88bd3a | 708 | #define CPUID_CACHE_INFO 0x02\r |
236d5c66 RN |
709 | \r |
710 | /**\r | |
711 | CPUID Cache and TLB Information returned in EAX, EBX, ECX, and EDX for CPUID\r | |
712 | leaf #CPUID_CACHE_INFO.\r | |
713 | **/\r | |
714 | typedef union {\r | |
715 | ///\r | |
716 | /// Individual bit fields\r | |
717 | ///\r | |
718 | struct {\r | |
2f88bd3a | 719 | UINT32 Reserved : 31;\r |
236d5c66 RN |
720 | ///\r |
721 | /// [Bit 31] If 0, then the cache descriptor bytes in the register are valid.\r | |
722 | /// if 1, then none of the cache descriptor bytes in the register are valid.\r | |
723 | ///\r | |
2f88bd3a | 724 | UINT32 NotValid : 1;\r |
236d5c66 RN |
725 | } Bits;\r |
726 | ///\r | |
727 | /// Array of Cache and TLB descriptor bytes\r | |
728 | ///\r | |
2f88bd3a | 729 | UINT8 CacheDescriptor[4];\r |
236d5c66 RN |
730 | ///\r |
731 | /// All bit fields as a 32-bit value\r | |
732 | ///\r | |
2f88bd3a | 733 | UINT32 Uint32;\r |
236d5c66 RN |
734 | } CPUID_CACHE_INFO_CACHE_TLB;\r |
735 | \r | |
236d5c66 RN |
736 | /**\r |
737 | CPUID Processor Serial Number\r | |
738 | \r | |
739 | Processor serial number (PSN) is not supported in the Pentium 4 processor\r | |
740 | or later. On all models, use the PSN flag (returned using CPUID) to check\r | |
741 | for PSN support before accessing the feature.\r | |
742 | \r | |
743 | @param EAX CPUID_SERIAL_NUMBER (0x03)\r | |
744 | \r | |
745 | @retval EAX Reserved.\r | |
746 | @retval EBX Reserved.\r | |
747 | @retval ECX Bits 31:0 of 96 bit processor serial number. (Available in\r | |
748 | Pentium III processor only; otherwise, the value in this\r | |
749 | register is reserved.)\r | |
750 | @retval EDX Bits 63:32 of 96 bit processor serial number. (Available in\r | |
751 | Pentium III processor only; otherwise, the value in this\r | |
752 | register is reserved.)\r | |
753 | \r | |
754 | <b>Example usage</b>\r | |
755 | @code\r | |
756 | UINT32 Ecx;\r | |
757 | UINT32 Edx;\r | |
758 | \r | |
759 | AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx);\r | |
760 | @endcode\r | |
761 | **/\r | |
2f88bd3a | 762 | #define CPUID_SERIAL_NUMBER 0x03\r |
236d5c66 RN |
763 | \r |
764 | /**\r | |
765 | CPUID Cache Parameters\r | |
766 | \r | |
767 | @param EAX CPUID_CACHE_PARAMS (0x04)\r | |
768 | @param ECX Cache Level. Valid values start at 0. Software can enumerate\r | |
769 | the deterministic cache parameters for each level of the cache\r | |
770 | hierarchy starting with an index value of 0, until the\r | |
771 | parameters report the value associated with the CacheType\r | |
772 | field in CPUID_CACHE_PARAMS_EAX is 0.\r | |
773 | \r | |
774 | @retval EAX Returns cache type information described by the type\r | |
775 | CPUID_CACHE_PARAMS_EAX.\r | |
776 | @retval EBX Returns cache line and associativity information described by\r | |
777 | the type CPUID_CACHE_PARAMS_EBX.\r | |
778 | @retval ECX Returns the number of sets in the cache.\r | |
779 | @retval EDX Returns cache WINVD/INVD behavior described by the type\r | |
780 | CPUID_CACHE_PARAMS_EDX.\r | |
781 | \r | |
782 | <b>Example usage</b>\r | |
783 | @code\r | |
784 | UINT32 CacheLevel;\r | |
785 | CPUID_CACHE_PARAMS_EAX Eax;\r | |
786 | CPUID_CACHE_PARAMS_EBX Ebx;\r | |
787 | UINT32 Ecx;\r | |
788 | CPUID_CACHE_PARAMS_EDX Edx;\r | |
789 | \r | |
790 | CacheLevel = 0;\r | |
791 | do {\r | |
792 | AsmCpuidEx (\r | |
793 | CPUID_CACHE_PARAMS, CacheLevel,\r | |
794 | &Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32\r | |
795 | );\r | |
796 | CacheLevel++;\r | |
797 | } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);\r | |
798 | @endcode\r | |
799 | **/\r | |
2f88bd3a | 800 | #define CPUID_CACHE_PARAMS 0x04\r |
236d5c66 RN |
801 | \r |
802 | /**\r | |
803 | CPUID Cache Parameters Information returned in EAX for CPUID leaf\r | |
804 | #CPUID_CACHE_PARAMS.\r | |
805 | **/\r | |
806 | typedef union {\r | |
807 | ///\r | |
808 | /// Individual bit fields\r | |
809 | ///\r | |
810 | struct {\r | |
811 | ///\r | |
812 | /// [Bits 4:0] Cache type field. If #CPUID_CACHE_PARAMS_CACHE_TYPE_NULL,\r | |
813 | /// then there is no information for the requested cache level.\r | |
814 | ///\r | |
2f88bd3a | 815 | UINT32 CacheType : 5;\r |
236d5c66 RN |
816 | ///\r |
817 | /// [Bits 7:5] Cache level (Starts at 1).\r | |
818 | ///\r | |
2f88bd3a | 819 | UINT32 CacheLevel : 3;\r |
236d5c66 RN |
820 | ///\r |
821 | /// [Bit 8] Self Initializing cache level (does not need SW initialization).\r | |
822 | ///\r | |
2f88bd3a | 823 | UINT32 SelfInitializingCache : 1;\r |
236d5c66 RN |
824 | ///\r |
825 | /// [Bit 9] Fully Associative cache.\r | |
826 | ///\r | |
2f88bd3a | 827 | UINT32 FullyAssociativeCache : 1;\r |
236d5c66 RN |
828 | ///\r |
829 | /// [Bits 13:10] Reserved.\r | |
830 | ///\r | |
2f88bd3a | 831 | UINT32 Reserved : 4;\r |
236d5c66 RN |
832 | ///\r |
833 | /// [Bits 25:14] Maximum number of addressable IDs for logical processors\r | |
834 | /// sharing this cache.\r | |
835 | ///\r | |
836 | /// Add one to the return value to get the result.\r | |
837 | /// The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14])\r | |
838 | /// is the number of unique initial APIC IDs reserved for addressing\r | |
839 | /// different logical processors sharing this cache.\r | |
840 | ///\r | |
2f88bd3a | 841 | UINT32 MaximumAddressableIdsForLogicalProcessors : 12;\r |
236d5c66 RN |
842 | ///\r |
843 | /// [Bits 31:26] Maximum number of addressable IDs for processor cores in\r | |
844 | /// the physical package.\r | |
845 | ///\r | |
846 | /// The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26])\r | |
847 | /// is the number of unique Core_IDs reserved for addressing different\r | |
848 | /// processor cores in a physical package. Core ID is a subset of bits of\r | |
849 | /// the initial APIC ID.\r | |
850 | /// The returned value is constant for valid initial values in ECX. Valid\r | |
851 | /// ECX values start from 0.\r | |
852 | ///\r | |
2f88bd3a | 853 | UINT32 MaximumAddressableIdsForProcessorCores : 6;\r |
236d5c66 RN |
854 | } Bits;\r |
855 | ///\r | |
856 | /// All bit fields as a 32-bit value\r | |
857 | ///\r | |
2f88bd3a | 858 | UINT32 Uint32;\r |
236d5c66 RN |
859 | } CPUID_CACHE_PARAMS_EAX;\r |
860 | \r | |
861 | ///\r | |
862 | /// @{ Define value for bit field CPUID_CACHE_PARAMS_EAX.CacheType\r | |
863 | ///\r | |
864 | #define CPUID_CACHE_PARAMS_CACHE_TYPE_NULL 0x00\r | |
865 | #define CPUID_CACHE_PARAMS_CACHE_TYPE_DATA 0x01\r | |
866 | #define CPUID_CACHE_PARAMS_CACHE_TYPE_INSTRUCTION 0x02\r | |
867 | #define CPUID_CACHE_PARAMS_CACHE_TYPE_UNIFIED 0x03\r | |
868 | ///\r | |
869 | /// @}\r | |
870 | ///\r | |
871 | \r | |
872 | /**\r | |
873 | CPUID Cache Parameters Information returned in EBX for CPUID leaf\r | |
874 | #CPUID_CACHE_PARAMS.\r | |
875 | **/\r | |
876 | typedef union {\r | |
877 | ///\r | |
878 | /// Individual bit fields\r | |
879 | ///\r | |
880 | struct {\r | |
881 | ///\r | |
882 | /// [Bits 11:0] System Coherency Line Size. Add one to the return value to\r | |
883 | /// get the result.\r | |
884 | ///\r | |
2f88bd3a | 885 | UINT32 LineSize : 12;\r |
236d5c66 RN |
886 | ///\r |
887 | /// [Bits 21:12] Physical Line Partitions. Add one to the return value to\r | |
888 | /// get the result.\r | |
889 | ///\r | |
2f88bd3a | 890 | UINT32 LinePartitions : 10;\r |
236d5c66 RN |
891 | ///\r |
892 | /// [Bits 31:22] Ways of associativity. Add one to the return value to get\r | |
893 | /// the result.\r | |
894 | ///\r | |
2f88bd3a | 895 | UINT32 Ways : 10;\r |
236d5c66 RN |
896 | } Bits;\r |
897 | ///\r | |
898 | /// All bit fields as a 32-bit value\r | |
899 | ///\r | |
2f88bd3a | 900 | UINT32 Uint32;\r |
236d5c66 RN |
901 | } CPUID_CACHE_PARAMS_EBX;\r |
902 | \r | |
903 | /**\r | |
904 | CPUID Cache Parameters Information returned in EDX for CPUID leaf\r | |
905 | #CPUID_CACHE_PARAMS.\r | |
906 | **/\r | |
907 | typedef union {\r | |
908 | ///\r | |
909 | /// Individual bit fields\r | |
910 | ///\r | |
911 | struct {\r | |
912 | ///\r | |
913 | /// [Bit 0] Write-Back Invalidate/Invalidate.\r | |
914 | /// 0 = WBINVD/INVD from threads sharing this cache acts upon lower level\r | |
915 | /// caches for threads sharing this cache.\r | |
916 | /// 1 = WBINVD/INVD is not guaranteed to act upon lower level caches of\r | |
917 | /// non-originating threads sharing this cache.\r | |
918 | ///\r | |
2f88bd3a | 919 | UINT32 Invalidate : 1;\r |
236d5c66 RN |
920 | ///\r |
921 | /// [Bit 1] Cache Inclusiveness.\r | |
922 | /// 0 = Cache is not inclusive of lower cache levels.\r | |
923 | /// 1 = Cache is inclusive of lower cache levels.\r | |
924 | ///\r | |
2f88bd3a | 925 | UINT32 CacheInclusiveness : 1;\r |
236d5c66 RN |
926 | ///\r |
927 | /// [Bit 2] Complex Cache Indexing.\r | |
928 | /// 0 = Direct mapped cache.\r | |
929 | /// 1 = A complex function is used to index the cache, potentially using all\r | |
930 | /// address bits.\r | |
931 | ///\r | |
2f88bd3a MK |
932 | UINT32 ComplexCacheIndexing : 1;\r |
933 | UINT32 Reserved : 29;\r | |
236d5c66 RN |
934 | } Bits;\r |
935 | ///\r | |
936 | /// All bit fields as a 32-bit value\r | |
937 | ///\r | |
2f88bd3a | 938 | UINT32 Uint32;\r |
236d5c66 RN |
939 | } CPUID_CACHE_PARAMS_EDX;\r |
940 | \r | |
236d5c66 RN |
941 | /**\r |
942 | CPUID MONITOR/MWAIT Information\r | |
943 | \r | |
944 | @param EAX CPUID_MONITOR_MWAIT (0x05)\r | |
945 | \r | |
946 | @retval EAX Smallest monitor-line size in bytes described by the type\r | |
947 | CPUID_MONITOR_MWAIT_EAX.\r | |
948 | @retval EBX Largest monitor-line size in bytes described by the type\r | |
949 | CPUID_MONITOR_MWAIT_EBX.\r | |
950 | @retval ECX Enumeration of Monitor-Mwait extensions support described by\r | |
951 | the type CPUID_MONITOR_MWAIT_ECX.\r | |
952 | @retval EDX Sub C-states supported described by the type\r | |
953 | CPUID_MONITOR_MWAIT_EDX.\r | |
954 | \r | |
955 | <b>Example usage</b>\r | |
956 | @code\r | |
957 | CPUID_MONITOR_MWAIT_EAX Eax;\r | |
958 | CPUID_MONITOR_MWAIT_EBX Ebx;\r | |
959 | CPUID_MONITOR_MWAIT_ECX Ecx;\r | |
960 | CPUID_MONITOR_MWAIT_EDX Edx;\r | |
961 | \r | |
962 | AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r | |
963 | @endcode\r | |
964 | **/\r | |
2f88bd3a | 965 | #define CPUID_MONITOR_MWAIT 0x05\r |
236d5c66 RN |
966 | \r |
967 | /**\r | |
968 | CPUID MONITOR/MWAIT Information returned in EAX for CPUID leaf\r | |
969 | #CPUID_MONITOR_MWAIT.\r | |
970 | **/\r | |
971 | typedef union {\r | |
972 | ///\r | |
973 | /// Individual bit fields\r | |
974 | ///\r | |
975 | struct {\r | |
976 | ///\r | |
977 | /// [Bits 15:0] Smallest monitor-line size in bytes (default is processor's\r | |
978 | /// monitor granularity).\r | |
979 | ///\r | |
2f88bd3a MK |
980 | UINT32 SmallestMonitorLineSize : 16;\r |
981 | UINT32 Reserved : 16;\r | |
236d5c66 RN |
982 | } Bits;\r |
983 | ///\r | |
984 | /// All bit fields as a 32-bit value\r | |
985 | ///\r | |
2f88bd3a | 986 | UINT32 Uint32;\r |
236d5c66 RN |
987 | } CPUID_MONITOR_MWAIT_EAX;\r |
988 | \r | |
989 | /**\r | |
990 | CPUID MONITOR/MWAIT Information returned in EBX for CPUID leaf\r | |
991 | #CPUID_MONITOR_MWAIT.\r | |
992 | **/\r | |
993 | typedef union {\r | |
994 | ///\r | |
995 | /// Individual bit fields\r | |
996 | ///\r | |
997 | struct {\r | |
998 | ///\r | |
999 | /// [Bits 15:0] Largest monitor-line size in bytes (default is processor's\r | |
1000 | /// monitor granularity).\r | |
1001 | ///\r | |
2f88bd3a MK |
1002 | UINT32 LargestMonitorLineSize : 16;\r |
1003 | UINT32 Reserved : 16;\r | |
236d5c66 RN |
1004 | } Bits;\r |
1005 | ///\r | |
1006 | /// All bit fields as a 32-bit value\r | |
1007 | ///\r | |
2f88bd3a | 1008 | UINT32 Uint32;\r |
236d5c66 RN |
1009 | } CPUID_MONITOR_MWAIT_EBX;\r |
1010 | \r | |
1011 | /**\r | |
1012 | CPUID MONITOR/MWAIT Information returned in ECX for CPUID leaf\r | |
1013 | #CPUID_MONITOR_MWAIT.\r | |
1014 | **/\r | |
1015 | typedef union {\r | |
1016 | ///\r | |
1017 | /// Individual bit fields\r | |
1018 | ///\r | |
1019 | struct {\r | |
1020 | ///\r | |
1021 | /// [Bit 0] If 0, then only EAX and EBX are valid. If 1, then EAX, EBX, ECX,\r | |
1022 | /// and EDX are valid.\r | |
1023 | ///\r | |
2f88bd3a | 1024 | UINT32 ExtensionsSupported : 1;\r |
236d5c66 RN |
1025 | ///\r |
1026 | /// [Bit 1] Supports treating interrupts as break-event for MWAIT, even when\r | |
1027 | /// interrupts disabled.\r | |
1028 | ///\r | |
2f88bd3a MK |
1029 | UINT32 InterruptAsBreak : 1;\r |
1030 | UINT32 Reserved : 30;\r | |
236d5c66 RN |
1031 | } Bits;\r |
1032 | ///\r | |
1033 | /// All bit fields as a 32-bit value\r | |
1034 | ///\r | |
2f88bd3a | 1035 | UINT32 Uint32;\r |
236d5c66 RN |
1036 | } CPUID_MONITOR_MWAIT_ECX;\r |
1037 | \r | |
1038 | /**\r | |
1039 | CPUID MONITOR/MWAIT Information returned in EDX for CPUID leaf\r | |
1040 | #CPUID_MONITOR_MWAIT.\r | |
1041 | \r | |
1042 | @note\r | |
1043 | The definition of C0 through C7 states for MWAIT extension are\r | |
1044 | processor-specific C-states, not ACPI C-states.\r | |
1045 | **/\r | |
1046 | typedef union {\r | |
1047 | ///\r | |
1048 | /// Individual bit fields\r | |
1049 | ///\r | |
1050 | struct {\r | |
1051 | ///\r | |
1052 | /// [Bits 3:0] Number of C0 sub C-states supported using MWAIT.\r | |
1053 | ///\r | |
2f88bd3a | 1054 | UINT32 C0States : 4;\r |
236d5c66 RN |
1055 | ///\r |
1056 | /// [Bits 7:4] Number of C1 sub C-states supported using MWAIT.\r | |
1057 | ///\r | |
2f88bd3a | 1058 | UINT32 C1States : 4;\r |
236d5c66 RN |
1059 | ///\r |
1060 | /// [Bits 11:8] Number of C2 sub C-states supported using MWAIT.\r | |
1061 | ///\r | |
2f88bd3a | 1062 | UINT32 C2States : 4;\r |
236d5c66 RN |
1063 | ///\r |
1064 | /// [Bits 15:12] Number of C3 sub C-states supported using MWAIT.\r | |
1065 | ///\r | |
2f88bd3a | 1066 | UINT32 C3States : 4;\r |
236d5c66 RN |
1067 | ///\r |
1068 | /// [Bits 19:16] Number of C4 sub C-states supported using MWAIT.\r | |
1069 | ///\r | |
2f88bd3a | 1070 | UINT32 C4States : 4;\r |
236d5c66 RN |
1071 | ///\r |
1072 | /// [Bits 23:20] Number of C5 sub C-states supported using MWAIT.\r | |
1073 | ///\r | |
2f88bd3a | 1074 | UINT32 C5States : 4;\r |
236d5c66 RN |
1075 | ///\r |
1076 | /// [Bits 27:24] Number of C6 sub C-states supported using MWAIT.\r | |
1077 | ///\r | |
2f88bd3a | 1078 | UINT32 C6States : 4;\r |
236d5c66 RN |
1079 | ///\r |
1080 | /// [Bits 31:28] Number of C7 sub C-states supported using MWAIT.\r | |
1081 | ///\r | |
2f88bd3a | 1082 | UINT32 C7States : 4;\r |
236d5c66 RN |
1083 | } Bits;\r |
1084 | ///\r | |
1085 | /// All bit fields as a 32-bit value\r | |
1086 | ///\r | |
2f88bd3a | 1087 | UINT32 Uint32;\r |
236d5c66 RN |
1088 | } CPUID_MONITOR_MWAIT_EDX;\r |
1089 | \r | |
236d5c66 RN |
1090 | /**\r |
1091 | CPUID Thermal and Power Management\r | |
1092 | \r | |
1093 | @param EAX CPUID_THERMAL_POWER_MANAGEMENT (0x06)\r | |
1094 | \r | |
1095 | @retval EAX Thermal and power management features described by the type\r | |
1096 | CPUID_THERMAL_POWER_MANAGEMENT_EAX.\r | |
1097 | @retval EBX Number of Interrupt Thresholds in Digital Thermal Sensor\r | |
1098 | described by the type CPUID_THERMAL_POWER_MANAGEMENT_EBX.\r | |
1099 | @retval ECX Performance features described by the type\r | |
1100 | CPUID_THERMAL_POWER_MANAGEMENT_ECX.\r | |
1101 | @retval EDX Reserved.\r | |
1102 | \r | |
1103 | <b>Example usage</b>\r | |
1104 | @code\r | |
1105 | CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax;\r | |
1106 | CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx;\r | |
1107 | CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx;\r | |
1108 | \r | |
1109 | AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);\r | |
1110 | @endcode\r | |
1111 | **/\r | |
2f88bd3a | 1112 | #define CPUID_THERMAL_POWER_MANAGEMENT 0x06\r |
236d5c66 RN |
1113 | \r |
1114 | /**\r | |
1115 | CPUID Thermal and Power Management Information returned in EAX for CPUID leaf\r | |
1116 | #CPUID_THERMAL_POWER_MANAGEMENT.\r | |
1117 | **/\r | |
1118 | typedef union {\r | |
1119 | ///\r | |
1120 | /// Individual bit fields\r | |
1121 | ///\r | |
1122 | struct {\r | |
1123 | ///\r | |
1124 | /// [Bit 0] Digital temperature sensor is supported if set.\r | |
1125 | ///\r | |
2f88bd3a | 1126 | UINT32 DigitalTemperatureSensor : 1;\r |
236d5c66 RN |
1127 | ///\r |
1128 | /// [Bit 1] Intel Turbo Boost Technology Available (see IA32_MISC_ENABLE[38]).\r | |
1129 | ///\r | |
2f88bd3a | 1130 | UINT32 TurboBoostTechnology : 1;\r |
236d5c66 RN |
1131 | ///\r |
1132 | /// [Bit 2] APIC-Timer-always-running feature is supported if set.\r | |
1133 | ///\r | |
2f88bd3a MK |
1134 | UINT32 ARAT : 1;\r |
1135 | UINT32 Reserved1 : 1;\r | |
236d5c66 RN |
1136 | ///\r |
1137 | /// [Bit 4] Power limit notification controls are supported if set.\r | |
1138 | ///\r | |
2f88bd3a | 1139 | UINT32 PLN : 1;\r |
236d5c66 RN |
1140 | ///\r |
1141 | /// [Bit 5] Clock modulation duty cycle extension is supported if set.\r | |
1142 | ///\r | |
2f88bd3a | 1143 | UINT32 ECMD : 1;\r |
236d5c66 RN |
1144 | ///\r |
1145 | /// [Bit 6] Package thermal management is supported if set.\r | |
1146 | ///\r | |
2f88bd3a | 1147 | UINT32 PTM : 1;\r |
236d5c66 RN |
1148 | ///\r |
1149 | /// [Bit 7] HWP base registers (IA32_PM_ENABLE[Bit 0], IA32_HWP_CAPABILITIES,\r | |
1150 | /// IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.\r | |
1151 | ///\r | |
2f88bd3a | 1152 | UINT32 HWP : 1;\r |
236d5c66 RN |
1153 | ///\r |
1154 | /// [Bit 8] IA32_HWP_INTERRUPT MSR is supported if set.\r | |
1155 | ///\r | |
2f88bd3a | 1156 | UINT32 HWP_Notification : 1;\r |
236d5c66 RN |
1157 | ///\r |
1158 | /// [Bit 9] IA32_HWP_REQUEST[Bits 41:32] is supported if set.\r | |
1159 | ///\r | |
2f88bd3a | 1160 | UINT32 HWP_Activity_Window : 1;\r |
236d5c66 RN |
1161 | ///\r |
1162 | /// [Bit 10] IA32_HWP_REQUEST[Bits 31:24] is supported if set.\r | |
1163 | ///\r | |
2f88bd3a | 1164 | UINT32 HWP_Energy_Performance_Preference : 1;\r |
236d5c66 RN |
1165 | ///\r |
1166 | /// [Bit 11] IA32_HWP_REQUEST_PKG MSR is supported if set.\r | |
1167 | ///\r | |
2f88bd3a MK |
1168 | UINT32 HWP_Package_Level_Request : 1;\r |
1169 | UINT32 Reserved2 : 1;\r | |
236d5c66 RN |
1170 | ///\r |
1171 | /// [Bit 13] HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1,\r | |
1172 | /// IA32_THREAD_STALL MSRs are supported if set.\r | |
1173 | ///\r | |
2f88bd3a | 1174 | UINT32 HDC : 1;\r |
236d5c66 RN |
1175 | ///\r |
1176 | /// [Bit 14] Intel Turbo Boost Max Technology 3.0 available.\r | |
1177 | ///\r | |
2f88bd3a | 1178 | UINT32 TurboBoostMaxTechnology30 : 1;\r |
236d5c66 RN |
1179 | ///\r |
1180 | /// [Bit 15] HWP Capabilities.\r | |
1181 | /// Highest Performance change is supported if set.\r | |
1182 | ///\r | |
2f88bd3a | 1183 | UINT32 HWPCapabilities : 1;\r |
236d5c66 RN |
1184 | ///\r |
1185 | /// [Bit 16] HWP PECI override is supported if set.\r | |
1186 | ///\r | |
2f88bd3a | 1187 | UINT32 HWPPECIOverride : 1;\r |
236d5c66 RN |
1188 | ///\r |
1189 | /// [Bit 17] Flexible HWP is supported if set.\r | |
1190 | ///\r | |
2f88bd3a | 1191 | UINT32 FlexibleHWP : 1;\r |
236d5c66 RN |
1192 | ///\r |
1193 | /// [Bit 18] Fast access mode for the IA32_HWP_REQUEST MSR is supported if set.\r | |
1194 | ///\r | |
2f88bd3a MK |
1195 | UINT32 FastAccessMode : 1;\r |
1196 | UINT32 Reserved4 : 1;\r | |
236d5c66 RN |
1197 | ///\r |
1198 | /// [Bit 20] Ignoring Idle Logical Processor HWP request is supported if set.\r | |
1199 | ///\r | |
2f88bd3a MK |
1200 | UINT32 IgnoringIdleLogicalProcessorHWPRequest : 1;\r |
1201 | UINT32 Reserved5 : 11;\r | |
236d5c66 RN |
1202 | } Bits;\r |
1203 | ///\r | |
1204 | /// All bit fields as a 32-bit value\r | |
1205 | ///\r | |
2f88bd3a | 1206 | UINT32 Uint32;\r |
236d5c66 RN |
1207 | } CPUID_THERMAL_POWER_MANAGEMENT_EAX;\r |
1208 | \r | |
1209 | /**\r | |
1210 | CPUID Thermal and Power Management Information returned in EBX for CPUID leaf\r | |
1211 | #CPUID_THERMAL_POWER_MANAGEMENT.\r | |
1212 | **/\r | |
1213 | typedef union {\r | |
1214 | ///\r | |
1215 | /// Individual bit fields\r | |
1216 | ///\r | |
1217 | struct {\r | |
1218 | ///\r | |
1219 | /// {Bits 3:0] Number of Interrupt Thresholds in Digital Thermal Sensor.\r | |
1220 | ///\r | |
2f88bd3a MK |
1221 | UINT32 InterruptThresholds : 4;\r |
1222 | UINT32 Reserved : 28;\r | |
236d5c66 RN |
1223 | } Bits;\r |
1224 | ///\r | |
1225 | /// All bit fields as a 32-bit value\r | |
1226 | ///\r | |
2f88bd3a | 1227 | UINT32 Uint32;\r |
236d5c66 RN |
1228 | } CPUID_THERMAL_POWER_MANAGEMENT_EBX;\r |
1229 | \r | |
1230 | /**\r | |
1231 | CPUID Thermal and Power Management Information returned in ECX for CPUID leaf\r | |
1232 | #CPUID_THERMAL_POWER_MANAGEMENT.\r | |
1233 | **/\r | |
1234 | typedef union {\r | |
1235 | ///\r | |
1236 | /// Individual bit fields\r | |
1237 | ///\r | |
1238 | struct {\r | |
1239 | ///\r | |
1240 | /// [Bit 0] Hardware Coordination Feedback Capability (Presence of IA32_MPERF\r | |
1241 | /// and IA32_APERF). The capability to provide a measure of delivered\r | |
1242 | /// processor performance (since last reset of the counters), as a percentage\r | |
1243 | /// of the expected processor performance when running at the TSC frequency.\r | |
1244 | ///\r | |
2f88bd3a MK |
1245 | UINT32 HardwareCoordinationFeedback : 1;\r |
1246 | UINT32 Reserved1 : 2;\r | |
236d5c66 RN |
1247 | ///\r |
1248 | /// [Bit 3] If this bit is set, then the processor supports performance-energy\r | |
1249 | /// bias preference and the architectural MSR called IA32_ENERGY_PERF_BIAS\r | |
1250 | /// (1B0H).\r | |
1251 | ///\r | |
2f88bd3a MK |
1252 | UINT32 PerformanceEnergyBias : 1;\r |
1253 | UINT32 Reserved2 : 28;\r | |
236d5c66 RN |
1254 | } Bits;\r |
1255 | ///\r | |
1256 | /// All bit fields as a 32-bit value\r | |
1257 | ///\r | |
2f88bd3a | 1258 | UINT32 Uint32;\r |
236d5c66 RN |
1259 | } CPUID_THERMAL_POWER_MANAGEMENT_ECX;\r |
1260 | \r | |
236d5c66 RN |
1261 | /**\r |
1262 | CPUID Structured Extended Feature Flags Enumeration\r | |
1263 | \r | |
1264 | @param EAX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07)\r | |
1265 | @param ECX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO (0x00).\r | |
1266 | \r | |
1267 | @note\r | |
1268 | If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf\r | |
1269 | index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX.\r | |
1270 | \r | |
1271 | @retval EAX The maximum input value for ECX to retrieve sub-leaf information.\r | |
1272 | @retval EBX Structured Extended Feature Flags described by the type\r | |
1273 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX.\r | |
79f3404a | 1274 | @retval ECX Structured Extended Feature Flags described by the type\r |
236d5c66 RN |
1275 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX.\r |
1276 | @retval EDX Reserved.\r | |
1277 | \r | |
1278 | <b>Example usage</b>\r | |
1279 | @code\r | |
1280 | UINT32 Eax;\r | |
1281 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;\r | |
1282 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx;\r | |
1283 | UINT32 SubLeaf;\r | |
1284 | \r | |
1285 | AsmCpuidEx (\r | |
1286 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r | |
1287 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,\r | |
1288 | &Eax, NULL, NULL, NULL\r | |
1289 | );\r | |
1290 | for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) {\r | |
1291 | AsmCpuidEx (\r | |
1292 | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r | |
1293 | SubLeaf,\r | |
1294 | NULL, &Ebx.Uint32, &Ecx.Uint32, NULL\r | |
1295 | );\r | |
1296 | }\r | |
1297 | @endcode\r | |
1298 | **/\r | |
2f88bd3a | 1299 | #define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07\r |
236d5c66 RN |
1300 | \r |
1301 | ///\r | |
1302 | /// CPUID Structured Extended Feature Flags Enumeration sub-leaf\r | |
1303 | ///\r | |
1304 | #define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO 0x00\r | |
1305 | \r | |
1306 | /**\r | |
1307 | CPUID Structured Extended Feature Flags Enumeration in EBX for CPUID leaf\r | |
1308 | #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf\r | |
1309 | #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.\r | |
1310 | **/\r | |
1311 | typedef union {\r | |
1312 | ///\r | |
1313 | /// Individual bit fields\r | |
1314 | ///\r | |
1315 | struct {\r | |
1316 | ///\r | |
1317 | /// [Bit 0] Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.\r | |
1318 | ///\r | |
2f88bd3a | 1319 | UINT32 FSGSBASE : 1;\r |
236d5c66 RN |
1320 | ///\r |
1321 | /// [Bit 1] IA32_TSC_ADJUST MSR is supported if 1.\r | |
1322 | ///\r | |
2f88bd3a | 1323 | UINT32 IA32_TSC_ADJUST : 1;\r |
236d5c66 RN |
1324 | ///\r |
1325 | /// [Bit 2] Intel SGX is supported if 1. See section 37.7 "DISCOVERING SUPPORT\r | |
1326 | /// FOR INTEL(R) SGX AND ENABLING ENCLAVE INSTRUCTIONS".\r | |
1327 | ///\r | |
2f88bd3a | 1328 | UINT32 SGX : 1;\r |
236d5c66 RN |
1329 | ///\r |
1330 | /// [Bit 3] If 1 indicates the processor supports the first group of advanced\r | |
1331 | /// bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT)\r | |
1332 | ///\r | |
2f88bd3a | 1333 | UINT32 BMI1 : 1;\r |
236d5c66 RN |
1334 | ///\r |
1335 | /// [Bit 4] Hardware Lock Elision\r | |
1336 | ///\r | |
2f88bd3a | 1337 | UINT32 HLE : 1;\r |
236d5c66 RN |
1338 | ///\r |
1339 | /// [Bit 5] If 1 indicates the processor supports AVX2 instruction extensions.\r | |
1340 | ///\r | |
2f88bd3a | 1341 | UINT32 AVX2 : 1;\r |
236d5c66 RN |
1342 | ///\r |
1343 | /// [Bit 6] x87 FPU Data Pointer updated only on x87 exceptions if 1.\r | |
1344 | ///\r | |
2f88bd3a | 1345 | UINT32 FDP_EXCPTN_ONLY : 1;\r |
236d5c66 RN |
1346 | ///\r |
1347 | /// [Bit 7] Supports Supervisor-Mode Execution Prevention if 1.\r | |
1348 | ///\r | |
2f88bd3a | 1349 | UINT32 SMEP : 1;\r |
236d5c66 RN |
1350 | ///\r |
1351 | /// [Bit 8] If 1 indicates the processor supports the second group of\r | |
1352 | /// advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX,\r | |
1353 | /// SARX, SHLX, SHRX)\r | |
1354 | ///\r | |
2f88bd3a | 1355 | UINT32 BMI2 : 1;\r |
236d5c66 RN |
1356 | ///\r |
1357 | /// [Bit 9] Supports Enhanced REP MOVSB/STOSB if 1.\r | |
1358 | ///\r | |
2f88bd3a | 1359 | UINT32 EnhancedRepMovsbStosb : 1;\r |
236d5c66 RN |
1360 | ///\r |
1361 | /// [Bit 10] If 1, supports INVPCID instruction for system software that\r | |
1362 | /// manages process-context identifiers.\r | |
1363 | ///\r | |
2f88bd3a | 1364 | UINT32 INVPCID : 1;\r |
236d5c66 RN |
1365 | ///\r |
1366 | /// [Bit 11] Restricted Transactional Memory\r | |
1367 | ///\r | |
2f88bd3a | 1368 | UINT32 RTM : 1;\r |
236d5c66 RN |
1369 | ///\r |
1370 | /// [Bit 12] Supports Intel(R) Resource Director Technology (Intel(R) RDT)\r | |
1371 | /// Monitoring capability if 1.\r | |
1372 | ///\r | |
2f88bd3a | 1373 | UINT32 RDT_M : 1;\r |
236d5c66 RN |
1374 | ///\r |
1375 | /// [Bit 13] Deprecates FPU CS and FPU DS values if 1.\r | |
1376 | ///\r | |
2f88bd3a | 1377 | UINT32 DeprecateFpuCsDs : 1;\r |
236d5c66 RN |
1378 | ///\r |
1379 | /// [Bit 14] Supports Intel(R) Memory Protection Extensions if 1.\r | |
1380 | ///\r | |
2f88bd3a | 1381 | UINT32 MPX : 1;\r |
236d5c66 RN |
1382 | ///\r |
1383 | /// [Bit 15] Supports Intel(R) Resource Director Technology (Intel(R) RDT)\r | |
1384 | /// Allocation capability if 1.\r | |
1385 | ///\r | |
2f88bd3a | 1386 | UINT32 RDT_A : 1;\r |
236d5c66 RN |
1387 | ///\r |
1388 | /// [Bit 16] AVX512F.\r | |
1389 | ///\r | |
2f88bd3a | 1390 | UINT32 AVX512F : 1;\r |
236d5c66 RN |
1391 | ///\r |
1392 | /// [Bit 17] AVX512DQ.\r | |
1393 | ///\r | |
2f88bd3a | 1394 | UINT32 AVX512DQ : 1;\r |
236d5c66 RN |
1395 | ///\r |
1396 | /// [Bit 18] If 1 indicates the processor supports the RDSEED instruction.\r | |
1397 | ///\r | |
2f88bd3a | 1398 | UINT32 RDSEED : 1;\r |
236d5c66 RN |
1399 | ///\r |
1400 | /// [Bit 19] If 1 indicates the processor supports the ADCX and ADOX\r | |
1401 | /// instructions.\r | |
1402 | ///\r | |
2f88bd3a | 1403 | UINT32 ADX : 1;\r |
236d5c66 RN |
1404 | ///\r |
1405 | /// [Bit 20] Supports Supervisor-Mode Access Prevention (and the CLAC/STAC\r | |
1406 | /// instructions) if 1.\r | |
1407 | ///\r | |
2f88bd3a | 1408 | UINT32 SMAP : 1;\r |
236d5c66 RN |
1409 | ///\r |
1410 | /// [Bit 21] AVX512_IFMA.\r | |
1411 | ///\r | |
2f88bd3a MK |
1412 | UINT32 AVX512_IFMA : 1;\r |
1413 | UINT32 Reserved6 : 1;\r | |
236d5c66 RN |
1414 | ///\r |
1415 | /// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction.\r | |
1416 | ///\r | |
2f88bd3a | 1417 | UINT32 CLFLUSHOPT : 1;\r |
236d5c66 RN |
1418 | ///\r |
1419 | /// [Bit 24] If 1 indicates the processor supports the CLWB instruction.\r | |
1420 | ///\r | |
2f88bd3a | 1421 | UINT32 CLWB : 1;\r |
236d5c66 RN |
1422 | ///\r |
1423 | /// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace\r | |
1424 | /// extensions.\r | |
1425 | ///\r | |
2f88bd3a | 1426 | UINT32 IntelProcessorTrace : 1;\r |
236d5c66 RN |
1427 | ///\r |
1428 | /// [Bit 26] AVX512PF. (Intel Xeon Phi only.).\r | |
1429 | ///\r | |
2f88bd3a | 1430 | UINT32 AVX512PF : 1;\r |
236d5c66 RN |
1431 | ///\r |
1432 | /// [Bit 27] AVX512ER. (Intel Xeon Phi only.).\r | |
1433 | ///\r | |
2f88bd3a | 1434 | UINT32 AVX512ER : 1;\r |
236d5c66 RN |
1435 | ///\r |
1436 | /// [Bit 28] AVX512CD.\r | |
1437 | ///\r | |
2f88bd3a | 1438 | UINT32 AVX512CD : 1;\r |
236d5c66 RN |
1439 | ///\r |
1440 | /// [Bit 29] Supports Intel(R) Secure Hash Algorithm Extensions (Intel(R)\r | |
1441 | /// SHA Extensions) if 1.\r | |
1442 | ///\r | |
2f88bd3a | 1443 | UINT32 SHA : 1;\r |
236d5c66 RN |
1444 | ///\r |
1445 | /// [Bit 30] AVX512BW.\r | |
1446 | ///\r | |
2f88bd3a | 1447 | UINT32 AVX512BW : 1;\r |
236d5c66 RN |
1448 | ///\r |
1449 | /// [Bit 31] AVX512VL.\r | |
1450 | ///\r | |
2f88bd3a | 1451 | UINT32 AVX512VL : 1;\r |
236d5c66 RN |
1452 | } Bits;\r |
1453 | ///\r | |
1454 | /// All bit fields as a 32-bit value\r | |
1455 | ///\r | |
2f88bd3a | 1456 | UINT32 Uint32;\r |
236d5c66 RN |
1457 | } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX;\r |
1458 | \r | |
1459 | /**\r | |
1460 | CPUID Structured Extended Feature Flags Enumeration in ECX for CPUID leaf\r | |
1461 | #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf\r | |
1462 | #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.\r | |
1463 | **/\r | |
1464 | typedef union {\r | |
1465 | ///\r | |
1466 | /// Individual bit fields\r | |
1467 | ///\r | |
1468 | struct {\r | |
1469 | ///\r | |
1470 | /// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction.\r | |
1471 | /// (Intel Xeon Phi only.)\r | |
1472 | ///\r | |
2f88bd3a | 1473 | UINT32 PREFETCHWT1 : 1;\r |
236d5c66 RN |
1474 | ///\r |
1475 | /// [Bit 1] AVX512_VBMI.\r | |
1476 | ///\r | |
2f88bd3a | 1477 | UINT32 AVX512_VBMI : 1;\r |
236d5c66 RN |
1478 | ///\r |
1479 | /// [Bit 2] Supports user-mode instruction prevention if 1.\r | |
1480 | ///\r | |
2f88bd3a | 1481 | UINT32 UMIP : 1;\r |
236d5c66 RN |
1482 | ///\r |
1483 | /// [Bit 3] Supports protection keys for user-mode pages if 1.\r | |
1484 | ///\r | |
2f88bd3a | 1485 | UINT32 PKU : 1;\r |
236d5c66 RN |
1486 | ///\r |
1487 | /// [Bit 4] If 1, OS has set CR4.PKE to enable protection keys (and the\r | |
1488 | /// RDPKRU/WRPKRU instructions).\r | |
1489 | ///\r | |
2f88bd3a MK |
1490 | UINT32 OSPKE : 1;\r |
1491 | UINT32 Reserved5 : 9;\r | |
236d5c66 RN |
1492 | ///\r |
1493 | /// [Bits 14] AVX512_VPOPCNTDQ. (Intel Xeon Phi only.).\r | |
1494 | ///\r | |
2f88bd3a MK |
1495 | UINT32 AVX512_VPOPCNTDQ : 1;\r |
1496 | UINT32 Reserved7 : 1;\r | |
236d5c66 RN |
1497 | ///\r |
1498 | /// [Bits 16] Supports 5-level paging if 1.\r | |
1499 | ///\r | |
2f88bd3a | 1500 | UINT32 FiveLevelPage : 1;\r |
236d5c66 RN |
1501 | ///\r |
1502 | /// [Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions\r | |
1503 | /// in 64-bit mode.\r | |
1504 | ///\r | |
2f88bd3a | 1505 | UINT32 MAWAU : 5;\r |
236d5c66 RN |
1506 | ///\r |
1507 | /// [Bit 22] RDPID and IA32_TSC_AUX are available if 1.\r | |
1508 | ///\r | |
2f88bd3a MK |
1509 | UINT32 RDPID : 1;\r |
1510 | UINT32 Reserved3 : 7;\r | |
236d5c66 RN |
1511 | ///\r |
1512 | /// [Bit 30] Supports SGX Launch Configuration if 1.\r | |
1513 | ///\r | |
2f88bd3a MK |
1514 | UINT32 SGX_LC : 1;\r |
1515 | UINT32 Reserved4 : 1;\r | |
236d5c66 RN |
1516 | } Bits;\r |
1517 | ///\r | |
1518 | /// All bit fields as a 32-bit value\r | |
1519 | ///\r | |
2f88bd3a | 1520 | UINT32 Uint32;\r |
236d5c66 RN |
1521 | } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX;\r |
1522 | \r | |
1523 | /**\r | |
1524 | CPUID Structured Extended Feature Flags Enumeration in EDX for CPUID leaf\r | |
1525 | #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf\r | |
1526 | #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.\r | |
1527 | **/\r | |
1528 | typedef union {\r | |
1529 | ///\r | |
1530 | /// Individual bit fields\r | |
1531 | ///\r | |
1532 | struct {\r | |
1533 | ///\r | |
1534 | /// [Bit 1:0] Reserved.\r | |
1535 | ///\r | |
2f88bd3a | 1536 | UINT32 Reserved1 : 2;\r |
236d5c66 RN |
1537 | ///\r |
1538 | /// [Bit 2] AVX512_4VNNIW. (Intel Xeon Phi only.)\r | |
1539 | ///\r | |
2f88bd3a | 1540 | UINT32 AVX512_4VNNIW : 1;\r |
236d5c66 RN |
1541 | ///\r |
1542 | /// [Bit 3] AVX512_4FMAPS. (Intel Xeon Phi only.)\r | |
1543 | ///\r | |
2f88bd3a | 1544 | UINT32 AVX512_4FMAPS : 1;\r |
236d5c66 | 1545 | ///\r |
0bbc2072 | 1546 | /// [Bit 14:4] Reserved.\r |
236d5c66 | 1547 | ///\r |
2f88bd3a | 1548 | UINT32 Reserved4 : 11;\r |
0bbc2072 J |
1549 | ///\r |
1550 | /// [Bit 15] Hybrid. If 1, the processor is identified as a hybrid part.\r | |
1551 | ///\r | |
2f88bd3a | 1552 | UINT32 Hybrid : 1;\r |
0bbc2072 J |
1553 | ///\r |
1554 | /// [Bit 25:16] Reserved.\r | |
1555 | ///\r | |
2f88bd3a | 1556 | UINT32 Reserved5 : 10;\r |
236d5c66 RN |
1557 | ///\r |
1558 | /// [Bit 26] Enumerates support for indirect branch restricted speculation\r | |
1559 | /// (IBRS) and the indirect branch pre-dictor barrier (IBPB). Processors\r | |
1560 | /// that set this bit support the IA32_SPEC_CTRL MSR and the IA32_PRED_CMD\r | |
1561 | /// MSR. They allow software to set IA32_SPEC_CTRL[0] (IBRS) and\r | |
1562 | /// IA32_PRED_CMD[0] (IBPB).\r | |
1563 | ///\r | |
2f88bd3a | 1564 | UINT32 EnumeratesSupportForIBRSAndIBPB : 1;\r |
236d5c66 RN |
1565 | ///\r |
1566 | /// [Bit 27] Enumerates support for single thread indirect branch\r | |
1567 | /// predictors (STIBP). Processors that set this bit support the\r | |
1568 | /// IA32_SPEC_CTRL MSR. They allow software to set IA32_SPEC_CTRL[1]\r | |
1569 | /// (STIBP).\r | |
1570 | ///\r | |
2f88bd3a | 1571 | UINT32 EnumeratesSupportForSTIBP : 1;\r |
236d5c66 RN |
1572 | ///\r |
1573 | /// [Bit 28] Enumerates support for L1D_FLUSH. Processors that set this bit\r | |
1574 | /// support the IA32_FLUSH_CMD MSR. They allow software to set\r | |
1575 | /// IA32_FLUSH_CMD[0] (L1D_FLUSH).\r | |
1576 | ///\r | |
2f88bd3a | 1577 | UINT32 EnumeratesSupportForL1D_FLUSH : 1;\r |
236d5c66 RN |
1578 | ///\r |
1579 | /// [Bit 29] Enumerates support for the IA32_ARCH_CAPABILITIES MSR.\r | |
1580 | ///\r | |
2f88bd3a | 1581 | UINT32 EnumeratesSupportForCapability : 1;\r |
236d5c66 | 1582 | ///\r |
bb146ce3 | 1583 | /// [Bit 30] Enumerates support for the IA32_CORE_CAPABILITIES MSR.\r |
236d5c66 | 1584 | ///\r |
2f88bd3a | 1585 | UINT32 EnumeratesSupportForCoreCapabilitiesMsr : 1;\r |
236d5c66 RN |
1586 | ///\r |
1587 | /// [Bit 31] Enumerates support for Speculative Store Bypass Disable (SSBD).\r | |
1588 | /// Processors that set this bit sup-port the IA32_SPEC_CTRL MSR. They allow\r | |
1589 | /// software to set IA32_SPEC_CTRL[2] (SSBD).\r | |
1590 | ///\r | |
2f88bd3a | 1591 | UINT32 EnumeratesSupportForSSBD : 1;\r |
236d5c66 RN |
1592 | } Bits;\r |
1593 | ///\r | |
1594 | /// All bit fields as a 32-bit value\r | |
1595 | ///\r | |
2f88bd3a | 1596 | UINT32 Uint32;\r |
236d5c66 RN |
1597 | } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX;\r |
1598 | \r | |
1599 | /**\r | |
1600 | CPUID Direct Cache Access Information\r | |
1601 | \r | |
1602 | @param EAX CPUID_DIRECT_CACHE_ACCESS_INFO (0x09)\r | |
1603 | \r | |
1604 | @retval EAX Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H).\r | |
1605 | @retval EBX Reserved.\r | |
1606 | @retval ECX Reserved.\r | |
1607 | @retval EDX Reserved.\r | |
1608 | \r | |
1609 | <b>Example usage</b>\r | |
1610 | @code\r | |
1611 | UINT32 Eax;\r | |
1612 | \r | |
1613 | AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL);\r | |
1614 | @endcode\r | |
1615 | **/\r | |
2f88bd3a | 1616 | #define CPUID_DIRECT_CACHE_ACCESS_INFO 0x09\r |
236d5c66 RN |
1617 | \r |
1618 | /**\r | |
1619 | CPUID Architectural Performance Monitoring\r | |
1620 | \r | |
1621 | @param EAX CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (0x0A)\r | |
1622 | \r | |
1623 | @retval EAX Architectural Performance Monitoring information described by\r | |
1624 | the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX.\r | |
1625 | @retval EBX Architectural Performance Monitoring information described by\r | |
1626 | the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX.\r | |
1627 | @retval ECX Reserved.\r | |
1628 | @retval EDX Architectural Performance Monitoring information described by\r | |
1629 | the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX.\r | |
1630 | \r | |
1631 | <b>Example usage</b>\r | |
1632 | @code\r | |
1633 | CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX Eax;\r | |
1634 | CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX Ebx;\r | |
1635 | CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX Edx;\r | |
1636 | \r | |
1637 | AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32);\r | |
1638 | @endcode\r | |
1639 | **/\r | |
1640 | #define CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING 0x0A\r | |
1641 | \r | |
1642 | /**\r | |
1643 | CPUID Architectural Performance Monitoring EAX for CPUID leaf\r | |
1644 | #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.\r | |
1645 | **/\r | |
1646 | typedef union {\r | |
1647 | ///\r | |
1648 | /// Individual bit fields\r | |
1649 | ///\r | |
1650 | struct {\r | |
1651 | ///\r | |
1652 | /// [Bit 7:0] Version ID of architectural performance monitoring.\r | |
1653 | ///\r | |
2f88bd3a | 1654 | UINT32 ArchPerfMonVerID : 8;\r |
236d5c66 RN |
1655 | ///\r |
1656 | /// [Bits 15:8] Number of general-purpose performance monitoring counter\r | |
1657 | /// per logical processor.\r | |
1658 | ///\r | |
1659 | /// IA32_PERFEVTSELx MSRs start at address 186H and occupy a contiguous\r | |
1660 | /// block of MSR address space. Each performance event select register is\r | |
1661 | /// paired with a corresponding performance counter in the 0C1H address\r | |
1662 | /// block.\r | |
1663 | ///\r | |
2f88bd3a | 1664 | UINT32 PerformanceMonitorCounters : 8;\r |
236d5c66 RN |
1665 | ///\r |
1666 | /// [Bits 23:16] Bit width of general-purpose, performance monitoring counter.\r | |
1667 | ///\r | |
1668 | /// The bit width of an IA32_PMCx MSR. This the number of valid bits for\r | |
1669 | /// read operation. On write operations, the lower-order 32 bits of the MSR\r | |
1670 | /// may be written with any value, and the high-order bits are sign-extended\r | |
1671 | /// from the value of bit 31.\r | |
1672 | ///\r | |
2f88bd3a | 1673 | UINT32 PerformanceMonitorCounterWidth : 8;\r |
236d5c66 RN |
1674 | ///\r |
1675 | /// [Bits 31:24] Length of EBX bit vector to enumerate architectural\r | |
1676 | /// performance monitoring events.\r | |
1677 | ///\r | |
2f88bd3a | 1678 | UINT32 EbxBitVectorLength : 8;\r |
236d5c66 RN |
1679 | } Bits;\r |
1680 | ///\r | |
1681 | /// All bit fields as a 32-bit value\r | |
1682 | ///\r | |
2f88bd3a | 1683 | UINT32 Uint32;\r |
236d5c66 RN |
1684 | } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX;\r |
1685 | \r | |
1686 | /**\r | |
1687 | CPUID Architectural Performance Monitoring EBX for CPUID leaf\r | |
1688 | #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.\r | |
1689 | **/\r | |
1690 | typedef union {\r | |
1691 | ///\r | |
1692 | /// Individual bit fields\r | |
1693 | ///\r | |
1694 | struct {\r | |
1695 | ///\r | |
1696 | /// [Bit 0] Core cycle event not available if 1.\r | |
1697 | ///\r | |
2f88bd3a | 1698 | UINT32 UnhaltedCoreCycles : 1;\r |
236d5c66 RN |
1699 | ///\r |
1700 | /// [Bit 1] Instruction retired event not available if 1.\r | |
1701 | ///\r | |
2f88bd3a | 1702 | UINT32 InstructionsRetired : 1;\r |
236d5c66 RN |
1703 | ///\r |
1704 | /// [Bit 2] Reference cycles event not available if 1.\r | |
1705 | ///\r | |
2f88bd3a | 1706 | UINT32 UnhaltedReferenceCycles : 1;\r |
236d5c66 RN |
1707 | ///\r |
1708 | /// [Bit 3] Last-level cache reference event not available if 1.\r | |
1709 | ///\r | |
2f88bd3a | 1710 | UINT32 LastLevelCacheReferences : 1;\r |
236d5c66 RN |
1711 | ///\r |
1712 | /// [Bit 4] Last-level cache misses event not available if 1.\r | |
1713 | ///\r | |
2f88bd3a | 1714 | UINT32 LastLevelCacheMisses : 1;\r |
236d5c66 RN |
1715 | ///\r |
1716 | /// [Bit 5] Branch instruction retired event not available if 1.\r | |
1717 | ///\r | |
2f88bd3a | 1718 | UINT32 BranchInstructionsRetired : 1;\r |
236d5c66 RN |
1719 | ///\r |
1720 | /// [Bit 6] Branch mispredict retired event not available if 1.\r | |
1721 | ///\r | |
2f88bd3a MK |
1722 | UINT32 AllBranchMispredictRetired : 1;\r |
1723 | UINT32 Reserved : 25;\r | |
236d5c66 RN |
1724 | } Bits;\r |
1725 | ///\r | |
1726 | /// All bit fields as a 32-bit value\r | |
1727 | ///\r | |
2f88bd3a | 1728 | UINT32 Uint32;\r |
236d5c66 RN |
1729 | } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX;\r |
1730 | \r | |
1731 | /**\r | |
1732 | CPUID Architectural Performance Monitoring EDX for CPUID leaf\r | |
1733 | #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.\r | |
1734 | **/\r | |
1735 | typedef union {\r | |
1736 | ///\r | |
1737 | /// Individual bit fields\r | |
1738 | ///\r | |
1739 | struct {\r | |
1740 | ///\r | |
1741 | /// [Bits 4:0] Number of fixed-function performance counters\r | |
1742 | /// (if Version ID > 1).\r | |
1743 | ///\r | |
2f88bd3a | 1744 | UINT32 FixedFunctionPerformanceCounters : 5;\r |
236d5c66 RN |
1745 | ///\r |
1746 | /// [Bits 12:5] Bit width of fixed-function performance counters\r | |
1747 | /// (if Version ID > 1).\r | |
1748 | ///\r | |
2f88bd3a MK |
1749 | UINT32 FixedFunctionPerformanceCounterWidth : 8;\r |
1750 | UINT32 Reserved1 : 2;\r | |
236d5c66 RN |
1751 | ///\r |
1752 | /// [Bits 15] AnyThread deprecation.\r | |
1753 | ///\r | |
2f88bd3a MK |
1754 | UINT32 AnyThreadDeprecation : 1;\r |
1755 | UINT32 Reserved2 : 16;\r | |
236d5c66 RN |
1756 | } Bits;\r |
1757 | ///\r | |
1758 | /// All bit fields as a 32-bit value\r | |
1759 | ///\r | |
2f88bd3a | 1760 | UINT32 Uint32;\r |
236d5c66 RN |
1761 | } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX;\r |
1762 | \r | |
236d5c66 RN |
1763 | /**\r |
1764 | CPUID Extended Topology Information\r | |
1765 | \r | |
1766 | @note\r | |
1767 | CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first\r | |
1768 | checking for the existence of Leaf 1FH before using leaf 0BH.\r | |
1769 | Most of Leaf 0BH output depends on the initial value in ECX. The EDX output\r | |
1770 | of leaf 0BH is always valid and does not vary with input value in ECX. Output\r | |
1771 | value in ECX[7:0] always equals input value in ECX[7:0].\r | |
1772 | Sub-leaf index 0 enumerates SMT level. Each subsequent higher sub-leaf index\r | |
1773 | enumerates a higher-level topological entity in hierarchical order.\r | |
1774 | For sub-leaves that return an invalid level-type of 0 in ECX[15:8]; EAX and\r | |
1775 | EBX will return 0.\r | |
1776 | If an input value n in ECX returns the invalid level-type of 0 in ECX[15:8],\r | |
1777 | other input values with ECX > n also return 0 in ECX[15:8].\r | |
1778 | \r | |
1779 | @param EAX CPUID_EXTENDED_TOPOLOGY (0x0B)\r | |
1780 | @param ECX Level number\r | |
1781 | \r | |
1782 | @retval EAX Extended topology information described by the type\r | |
1783 | CPUID_EXTENDED_TOPOLOGY_EAX.\r | |
1784 | @retval EBX Extended topology information described by the type\r | |
1785 | CPUID_EXTENDED_TOPOLOGY_EBX.\r | |
1786 | @retval ECX Extended topology information described by the type\r | |
1787 | CPUID_EXTENDED_TOPOLOGY_ECX.\r | |
1788 | @retval EDX x2APIC ID the current logical processor.\r | |
1789 | \r | |
1790 | <b>Example usage</b>\r | |
1791 | @code\r | |
1792 | CPUID_EXTENDED_TOPOLOGY_EAX Eax;\r | |
1793 | CPUID_EXTENDED_TOPOLOGY_EBX Ebx;\r | |
1794 | CPUID_EXTENDED_TOPOLOGY_ECX Ecx;\r | |
1795 | UINT32 Edx;\r | |
1796 | UINT32 LevelNumber;\r | |
1797 | \r | |
1798 | LevelNumber = 0;\r | |
1799 | do {\r | |
1800 | AsmCpuidEx (\r | |
1801 | CPUID_EXTENDED_TOPOLOGY, LevelNumber,\r | |
1802 | &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx\r | |
1803 | );\r | |
1804 | LevelNumber++;\r | |
1805 | } while (Eax.Bits.ApicIdShift != 0);\r | |
1806 | @endcode\r | |
1807 | **/\r | |
2f88bd3a | 1808 | #define CPUID_EXTENDED_TOPOLOGY 0x0B\r |
236d5c66 RN |
1809 | \r |
1810 | /**\r | |
1811 | CPUID Extended Topology Information EAX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.\r | |
1812 | **/\r | |
1813 | typedef union {\r | |
1814 | ///\r | |
1815 | /// Individual bit fields\r | |
1816 | ///\r | |
1817 | struct {\r | |
1818 | ///\r | |
1819 | /// [Bits 4:0] Number of bits to shift right on x2APIC ID to get a unique\r | |
1820 | /// topology ID of the next level type. All logical processors with the\r | |
1821 | /// same next level ID share current level.\r | |
1822 | ///\r | |
1823 | /// @note\r | |
1824 | /// Software should use this field (EAX[4:0]) to enumerate processor\r | |
1825 | /// topology of the system.\r | |
1826 | ///\r | |
2f88bd3a MK |
1827 | UINT32 ApicIdShift : 5;\r |
1828 | UINT32 Reserved : 27;\r | |
236d5c66 RN |
1829 | } Bits;\r |
1830 | ///\r | |
1831 | /// All bit fields as a 32-bit value\r | |
1832 | ///\r | |
2f88bd3a | 1833 | UINT32 Uint32;\r |
236d5c66 RN |
1834 | } CPUID_EXTENDED_TOPOLOGY_EAX;\r |
1835 | \r | |
1836 | /**\r | |
1837 | CPUID Extended Topology Information EBX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.\r | |
1838 | **/\r | |
1839 | typedef union {\r | |
1840 | ///\r | |
1841 | /// Individual bit fields\r | |
1842 | ///\r | |
1843 | struct {\r | |
1844 | ///\r | |
1845 | /// [Bits 15:0] Number of logical processors at this level type. The number\r | |
1846 | /// reflects configuration as shipped by Intel.\r | |
1847 | ///\r | |
1848 | /// @note\r | |
1849 | /// Software must not use EBX[15:0] to enumerate processor topology of the\r | |
1850 | /// system. This value in this field (EBX[15:0]) is only intended for\r | |
1851 | /// display/diagnostic purposes. The actual number of logical processors\r | |
1852 | /// available to BIOS/OS/Applications may be different from the value of\r | |
1853 | /// EBX[15:0], depending on software and platform hardware configurations.\r | |
1854 | ///\r | |
2f88bd3a MK |
1855 | UINT32 LogicalProcessors : 16;\r |
1856 | UINT32 Reserved : 16;\r | |
236d5c66 RN |
1857 | } Bits;\r |
1858 | ///\r | |
1859 | /// All bit fields as a 32-bit value\r | |
1860 | ///\r | |
2f88bd3a | 1861 | UINT32 Uint32;\r |
236d5c66 RN |
1862 | } CPUID_EXTENDED_TOPOLOGY_EBX;\r |
1863 | \r | |
1864 | /**\r | |
1865 | CPUID Extended Topology Information ECX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.\r | |
1866 | **/\r | |
1867 | typedef union {\r | |
1868 | ///\r | |
1869 | /// Individual bit fields\r | |
1870 | ///\r | |
1871 | struct {\r | |
1872 | ///\r | |
1873 | /// [Bits 7:0] Level number. Same value in ECX input.\r | |
1874 | ///\r | |
2f88bd3a | 1875 | UINT32 LevelNumber : 8;\r |
236d5c66 RN |
1876 | ///\r |
1877 | /// [Bits 15:8] Level type.\r | |
1878 | ///\r | |
1879 | /// @note\r | |
1880 | /// The value of the "level type" field is not related to level numbers in\r | |
1881 | /// any way, higher "level type" values do not mean higher levels.\r | |
1882 | ///\r | |
2f88bd3a MK |
1883 | UINT32 LevelType : 8;\r |
1884 | UINT32 Reserved : 16;\r | |
236d5c66 RN |
1885 | } Bits;\r |
1886 | ///\r | |
1887 | /// All bit fields as a 32-bit value\r | |
1888 | ///\r | |
2f88bd3a | 1889 | UINT32 Uint32;\r |
236d5c66 RN |
1890 | } CPUID_EXTENDED_TOPOLOGY_ECX;\r |
1891 | \r | |
1892 | ///\r | |
1893 | /// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType\r | |
1894 | ///\r | |
2f88bd3a MK |
1895 | #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00\r |
1896 | #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01\r | |
1897 | #define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02\r | |
236d5c66 RN |
1898 | ///\r |
1899 | /// @}\r | |
1900 | ///\r | |
1901 | \r | |
236d5c66 RN |
1902 | /**\r |
1903 | CPUID Extended State Information\r | |
1904 | \r | |
1905 | @param EAX CPUID_EXTENDED_STATE (0x0D)\r | |
1906 | @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00).\r | |
1907 | CPUID_EXTENDED_STATE_SUB_LEAF (0x01).\r | |
1908 | CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02).\r | |
1909 | Sub leafs 2..n based on supported bits in XCR0 or IA32_XSS_MSR.\r | |
1910 | **/\r | |
2f88bd3a | 1911 | #define CPUID_EXTENDED_STATE 0x0D\r |
236d5c66 RN |
1912 | \r |
1913 | /**\r | |
1914 | CPUID Extended State Information Main Leaf\r | |
1915 | \r | |
1916 | @param EAX CPUID_EXTENDED_STATE (0x0D)\r | |
1917 | @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00)\r | |
1918 | \r | |
1919 | @retval EAX Reports the supported bits of the lower 32 bits of XCR0. XCR0[n]\r | |
1920 | can be set to 1 only if EAX[n] is 1. The format of the extended\r | |
1921 | state main leaf is described by the type\r | |
1922 | CPUID_EXTENDED_STATE_MAIN_LEAF_EAX.\r | |
1923 | @retval EBX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save\r | |
1924 | area) required by enabled features in XCR0. May be different than\r | |
1925 | ECX if some features at the end of the XSAVE save area are not\r | |
1926 | enabled.\r | |
1927 | @retval ECX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save\r | |
1928 | area) of the XSAVE/XRSTOR save area required by all supported\r | |
1929 | features in the processor, i.e., all the valid bit fields in XCR0.\r | |
1930 | @retval EDX Reports the supported bits of the upper 32 bits of XCR0.\r | |
1931 | XCR0[n+32] can be set to 1 only if EDX[n] is 1.\r | |
1932 | \r | |
1933 | <b>Example usage</b>\r | |
1934 | @code\r | |
1935 | CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax;\r | |
1936 | UINT32 Ebx;\r | |
1937 | UINT32 Ecx;\r | |
1938 | UINT32 Edx;\r | |
1939 | \r | |
1940 | AsmCpuidEx (\r | |
1941 | CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF,\r | |
1942 | &Eax.Uint32, &Ebx, &Ecx, &Edx\r | |
1943 | );\r | |
1944 | @endcode\r | |
1945 | **/\r | |
2f88bd3a | 1946 | #define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00\r |
236d5c66 RN |
1947 | \r |
1948 | /**\r | |
1949 | CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,\r | |
1950 | sub-leaf #CPUID_EXTENDED_STATE_MAIN_LEAF.\r | |
1951 | **/\r | |
1952 | typedef union {\r | |
1953 | ///\r | |
1954 | /// Individual bit fields\r | |
1955 | ///\r | |
1956 | struct {\r | |
1957 | ///\r | |
1958 | /// [Bit 0] x87 state.\r | |
1959 | ///\r | |
2f88bd3a | 1960 | UINT32 x87 : 1;\r |
236d5c66 RN |
1961 | ///\r |
1962 | /// [Bit 1] SSE state.\r | |
1963 | ///\r | |
2f88bd3a | 1964 | UINT32 SSE : 1;\r |
236d5c66 RN |
1965 | ///\r |
1966 | /// [Bit 2] AVX state.\r | |
1967 | ///\r | |
2f88bd3a | 1968 | UINT32 AVX : 1;\r |
236d5c66 RN |
1969 | ///\r |
1970 | /// [Bits 4:3] MPX state.\r | |
1971 | ///\r | |
2f88bd3a | 1972 | UINT32 MPX : 2;\r |
236d5c66 RN |
1973 | ///\r |
1974 | /// [Bits 7:5] AVX-512 state.\r | |
1975 | ///\r | |
2f88bd3a | 1976 | UINT32 AVX_512 : 3;\r |
236d5c66 RN |
1977 | ///\r |
1978 | /// [Bit 8] Used for IA32_XSS.\r | |
1979 | ///\r | |
2f88bd3a | 1980 | UINT32 IA32_XSS : 1;\r |
236d5c66 RN |
1981 | ///\r |
1982 | /// [Bit 9] PKRU state.\r | |
1983 | ///\r | |
2f88bd3a MK |
1984 | UINT32 PKRU : 1;\r |
1985 | UINT32 Reserved1 : 3;\r | |
236d5c66 RN |
1986 | ///\r |
1987 | /// [Bit 13] Used for IA32_XSS, part 2.\r | |
1988 | ///\r | |
2f88bd3a MK |
1989 | UINT32 IA32_XSS_2 : 1;\r |
1990 | UINT32 Reserved2 : 18;\r | |
236d5c66 RN |
1991 | } Bits;\r |
1992 | ///\r | |
1993 | /// All bit fields as a 32-bit value\r | |
1994 | ///\r | |
2f88bd3a | 1995 | UINT32 Uint32;\r |
236d5c66 RN |
1996 | } CPUID_EXTENDED_STATE_MAIN_LEAF_EAX;\r |
1997 | \r | |
1998 | /**\r | |
1999 | CPUID Extended State Information Sub Leaf\r | |
2000 | \r | |
2001 | @param EAX CPUID_EXTENDED_STATE (0x0D)\r | |
2002 | @param ECX CPUID_EXTENDED_STATE_SUB_LEAF (0x01)\r | |
2003 | \r | |
2004 | @retval EAX The format of the extended state sub-leaf is described by the\r | |
2005 | type CPUID_EXTENDED_STATE_SUB_LEAF_EAX.\r | |
2006 | @retval EBX The size in bytes of the XSAVE area containing all states\r | |
2007 | enabled by XCRO | IA32_XSS.\r | |
2008 | @retval ECX The format of the extended state sub-leaf is described by the\r | |
2009 | type CPUID_EXTENDED_STATE_SUB_LEAF_ECX.\r | |
2010 | @retval EDX Reports the supported bits of the upper 32 bits of the\r | |
2011 | IA32_XSS MSR. IA32_XSS[n+32] can be set to 1 only if EDX[n] is 1.\r | |
2012 | \r | |
2013 | <b>Example usage</b>\r | |
2014 | @code\r | |
2015 | CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax;\r | |
2016 | UINT32 Ebx;\r | |
2017 | CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx;\r | |
2018 | UINT32 Edx;\r | |
2019 | \r | |
2020 | AsmCpuidEx (\r | |
2021 | CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF,\r | |
2022 | &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx\r | |
2023 | );\r | |
2024 | @endcode\r | |
2025 | **/\r | |
2f88bd3a | 2026 | #define CPUID_EXTENDED_STATE_SUB_LEAF 0x01\r |
236d5c66 RN |
2027 | \r |
2028 | /**\r | |
2029 | CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,\r | |
2030 | sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.\r | |
2031 | **/\r | |
2032 | typedef union {\r | |
2033 | ///\r | |
2034 | /// Individual bit fields\r | |
2035 | ///\r | |
2036 | struct {\r | |
2037 | ///\r | |
2038 | /// [Bit 0] XSAVEOPT is available.\r | |
2039 | ///\r | |
2f88bd3a | 2040 | UINT32 XSAVEOPT : 1;\r |
236d5c66 RN |
2041 | ///\r |
2042 | /// [Bit 1] Supports XSAVEC and the compacted form of XRSTOR if set.\r | |
2043 | ///\r | |
2f88bd3a | 2044 | UINT32 XSAVEC : 1;\r |
236d5c66 RN |
2045 | ///\r |
2046 | /// [Bit 2] Supports XGETBV with ECX = 1 if set.\r | |
2047 | ///\r | |
2f88bd3a | 2048 | UINT32 XGETBV : 1;\r |
236d5c66 RN |
2049 | ///\r |
2050 | /// [Bit 3] Supports XSAVES/XRSTORS and IA32_XSS if set.\r | |
2051 | ///\r | |
2f88bd3a MK |
2052 | UINT32 XSAVES : 1;\r |
2053 | UINT32 Reserved : 28;\r | |
236d5c66 RN |
2054 | } Bits;\r |
2055 | ///\r | |
2056 | /// All bit fields as a 32-bit value\r | |
2057 | ///\r | |
2f88bd3a | 2058 | UINT32 Uint32;\r |
236d5c66 RN |
2059 | } CPUID_EXTENDED_STATE_SUB_LEAF_EAX;\r |
2060 | \r | |
2061 | /**\r | |
2062 | CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,\r | |
2063 | sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.\r | |
2064 | **/\r | |
2065 | typedef union {\r | |
2066 | ///\r | |
2067 | /// Individual bit fields\r | |
2068 | ///\r | |
2069 | struct {\r | |
2070 | ///\r | |
2071 | /// [Bits 7:0] Used for XCR0.\r | |
2072 | ///\r | |
2f88bd3a | 2073 | UINT32 XCR0 : 1;\r |
236d5c66 RN |
2074 | ///\r |
2075 | /// [Bit 8] PT STate.\r | |
2076 | ///\r | |
2f88bd3a | 2077 | UINT32 PT : 1;\r |
236d5c66 RN |
2078 | ///\r |
2079 | /// [Bit 9] Used for XCR0.\r | |
2080 | ///\r | |
2f88bd3a MK |
2081 | UINT32 XCR0_1 : 1;\r |
2082 | UINT32 Reserved1 : 3;\r | |
236d5c66 RN |
2083 | ///\r |
2084 | /// [Bit 13] HWP state.\r | |
2085 | ///\r | |
2f88bd3a MK |
2086 | UINT32 HWPState : 1;\r |
2087 | UINT32 Reserved8 : 18;\r | |
236d5c66 RN |
2088 | } Bits;\r |
2089 | ///\r | |
2090 | /// All bit fields as a 32-bit value\r | |
2091 | ///\r | |
2f88bd3a | 2092 | UINT32 Uint32;\r |
236d5c66 RN |
2093 | } CPUID_EXTENDED_STATE_SUB_LEAF_ECX;\r |
2094 | \r | |
2095 | /**\r | |
2096 | CPUID Extended State Information Size and Offset Sub Leaf\r | |
2097 | \r | |
2098 | @note\r | |
2099 | Leaf 0DH output depends on the initial value in ECX.\r | |
2100 | Each sub-leaf index (starting at position 2) is supported if it corresponds to\r | |
2101 | a supported bit in either the XCR0 register or the IA32_XSS MSR.\r | |
2102 | If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf\r | |
2103 | n (0 <= n <= 31) is invalid if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1\r | |
2104 | returns 0 in ECX[n]. Sub-leaf n (32 <= n <= 63) is invalid if sub-leaf 0\r | |
2105 | returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32].\r | |
2106 | \r | |
2107 | @param EAX CPUID_EXTENDED_STATE (0x0D)\r | |
2108 | @param ECX CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02). Sub leafs 2..n based\r | |
2109 | on supported bits in XCR0 or IA32_XSS_MSR.\r | |
2110 | \r | |
2111 | @retval EAX The size in bytes (from the offset specified in EBX) of the save\r | |
2112 | area for an extended state feature associated with a valid\r | |
2113 | sub-leaf index, n.\r | |
2114 | @retval EBX The offset in bytes of this extended state component's save area\r | |
2115 | from the beginning of the XSAVE/XRSTOR area. This field reports\r | |
2116 | 0 if the sub-leaf index, n, does not map to a valid bit in the\r | |
2117 | XCR0 register.\r | |
2118 | @retval ECX The format of the extended state components's save area as\r | |
2119 | described by the type CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX.\r | |
2120 | This field reports 0 if the sub-leaf index, n, is invalid.\r | |
2121 | @retval EDX This field reports 0 if the sub-leaf index, n, is invalid;\r | |
2122 | otherwise it is reserved.\r | |
2123 | \r | |
2124 | <b>Example usage</b>\r | |
2125 | @code\r | |
2126 | UINT32 Eax;\r | |
2127 | UINT32 Ebx;\r | |
2128 | CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX Ecx;\r | |
2129 | UINT32 Edx;\r | |
2130 | UINTN SubLeaf;\r | |
2131 | \r | |
2132 | for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {\r | |
2133 | AsmCpuidEx (\r | |
2134 | CPUID_EXTENDED_STATE, SubLeaf,\r | |
2135 | &Eax, &Ebx, &Ecx.Uint32, &Edx\r | |
2136 | );\r | |
2137 | }\r | |
2138 | @endcode\r | |
2139 | **/\r | |
2f88bd3a | 2140 | #define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02\r |
236d5c66 RN |
2141 | \r |
2142 | /**\r | |
2143 | CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,\r | |
2144 | sub-leaf #CPUID_EXTENDED_STATE_SIZE_OFFSET.\r | |
2145 | **/\r | |
2146 | typedef union {\r | |
2147 | ///\r | |
2148 | /// Individual bit fields\r | |
2149 | ///\r | |
2150 | struct {\r | |
2151 | ///\r | |
2152 | /// [Bit 0] Is set if the bit n (corresponding to the sub-leaf index) is\r | |
2153 | /// supported in the IA32_XSS MSR; it is clear if bit n is instead supported\r | |
2154 | /// in XCR0.\r | |
2155 | ///\r | |
2f88bd3a | 2156 | UINT32 XSS : 1;\r |
236d5c66 RN |
2157 | ///\r |
2158 | /// [Bit 1] is set if, when the compacted format of an XSAVE area is used,\r | |
2159 | /// this extended state component located on the next 64-byte boundary\r | |
2160 | /// following the preceding state component (otherwise, it is located\r | |
2161 | /// immediately following the preceding state component).\r | |
2162 | ///\r | |
2f88bd3a MK |
2163 | UINT32 Compacted : 1;\r |
2164 | UINT32 Reserved : 30;\r | |
236d5c66 RN |
2165 | } Bits;\r |
2166 | ///\r | |
2167 | /// All bit fields as a 32-bit value\r | |
2168 | ///\r | |
2f88bd3a | 2169 | UINT32 Uint32;\r |
236d5c66 RN |
2170 | } CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX;\r |
2171 | \r | |
236d5c66 RN |
2172 | /**\r |
2173 | CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information\r | |
2174 | \r | |
2175 | @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)\r | |
2176 | @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00).\r | |
2177 | CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01).\r | |
2178 | \r | |
2179 | **/\r | |
2f88bd3a | 2180 | #define CPUID_INTEL_RDT_MONITORING 0x0F\r |
236d5c66 RN |
2181 | \r |
2182 | /**\r | |
2183 | CPUID Intel Resource Director Technology (Intel RDT) Monitoring Information\r | |
2184 | Enumeration Sub-leaf\r | |
2185 | \r | |
2186 | @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)\r | |
2187 | @param ECX CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF (0x00)\r | |
2188 | \r | |
2189 | @retval EAX Reserved.\r | |
2190 | @retval EBX Maximum range (zero-based) of RMID within this physical\r | |
2191 | processor of all types.\r | |
2192 | @retval ECX Reserved.\r | |
2193 | @retval EDX L3 Cache Intel RDT Monitoring Information Enumeration described by\r | |
2194 | the type CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX.\r | |
2195 | \r | |
2196 | <b>Example usage</b>\r | |
2197 | @code\r | |
2198 | UINT32 Ebx;\r | |
2199 | CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;\r | |
2200 | \r | |
2201 | AsmCpuidEx (\r | |
2202 | CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF,\r | |
2203 | NULL, &Ebx, NULL, &Edx.Uint32\r | |
2204 | );\r | |
2205 | @endcode\r | |
2206 | **/\r | |
2f88bd3a | 2207 | #define CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF 0x00\r |
236d5c66 RN |
2208 | \r |
2209 | /**\r | |
2210 | CPUID Intel RDT Monitoring Information EDX for CPUID leaf\r | |
2211 | #CPUID_INTEL_RDT_MONITORING, sub-leaf\r | |
2212 | #CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF.\r | |
2213 | **/\r | |
2214 | typedef union {\r | |
2215 | ///\r | |
2216 | /// Individual bit fields\r | |
2217 | ///\r | |
2218 | struct {\r | |
2f88bd3a | 2219 | UINT32 Reserved1 : 1;\r |
236d5c66 RN |
2220 | ///\r |
2221 | /// [Bit 1] Supports L3 Cache Intel RDT Monitoring if 1.\r | |
2222 | ///\r | |
2f88bd3a MK |
2223 | UINT32 L3CacheRDT_M : 1;\r |
2224 | UINT32 Reserved2 : 30;\r | |
236d5c66 RN |
2225 | } Bits;\r |
2226 | ///\r | |
2227 | /// All bit fields as a 32-bit value\r | |
2228 | ///\r | |
2f88bd3a | 2229 | UINT32 Uint32;\r |
236d5c66 RN |
2230 | } CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX;\r |
2231 | \r | |
2232 | /**\r | |
2233 | CPUID L3 Cache Intel RDT Monitoring Capability Enumeration Sub-leaf\r | |
2234 | \r | |
2235 | @param EAX CPUID_INTEL_RDT_MONITORING (0x0F)\r | |
2236 | @param ECX CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF (0x01)\r | |
2237 | \r | |
2238 | @retval EAX Reserved.\r | |
2239 | @retval EBX Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes).\r | |
2240 | @retval ECX Maximum range (zero-based) of RMID of this resource type.\r | |
2241 | @retval EDX L3 Cache Intel RDT Monitoring Capability information described by the\r | |
2242 | type CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX.\r | |
2243 | \r | |
2244 | <b>Example usage</b>\r | |
2245 | @code\r | |
2246 | UINT32 Ebx;\r | |
2247 | UINT32 Ecx;\r | |
2248 | CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Edx;\r | |
2249 | \r | |
2250 | AsmCpuidEx (\r | |
2251 | CPUID_INTEL_RDT_MONITORING, CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF,\r | |
2252 | NULL, &Ebx, &Ecx, &Edx.Uint32\r | |
2253 | );\r | |
2254 | @endcode\r | |
2255 | **/\r | |
2f88bd3a | 2256 | #define CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF 0x01\r |
236d5c66 RN |
2257 | \r |
2258 | /**\r | |
2259 | CPUID L3 Cache Intel RDT Monitoring Capability Information EDX for CPUID leaf\r | |
2260 | #CPUID_INTEL_RDT_MONITORING, sub-leaf\r | |
2261 | #CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF.\r | |
2262 | **/\r | |
2263 | typedef union {\r | |
2264 | ///\r | |
2265 | /// Individual bit fields\r | |
2266 | ///\r | |
2267 | struct {\r | |
2268 | ///\r | |
2269 | /// [Bit 0] Supports L3 occupancy monitoring if 1.\r | |
2270 | ///\r | |
2f88bd3a | 2271 | UINT32 L3CacheOccupancyMonitoring : 1;\r |
236d5c66 RN |
2272 | ///\r |
2273 | /// [Bit 1] Supports L3 Total Bandwidth monitoring if 1.\r | |
2274 | ///\r | |
2f88bd3a | 2275 | UINT32 L3CacheTotalBandwidthMonitoring : 1;\r |
236d5c66 RN |
2276 | ///\r |
2277 | /// [Bit 2] Supports L3 Local Bandwidth monitoring if 1.\r | |
2278 | ///\r | |
2f88bd3a MK |
2279 | UINT32 L3CacheLocalBandwidthMonitoring : 1;\r |
2280 | UINT32 Reserved : 29;\r | |
236d5c66 RN |
2281 | } Bits;\r |
2282 | ///\r | |
2283 | /// All bit fields as a 32-bit value\r | |
2284 | ///\r | |
2f88bd3a | 2285 | UINT32 Uint32;\r |
236d5c66 RN |
2286 | } CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX;\r |
2287 | \r | |
236d5c66 RN |
2288 | /**\r |
2289 | CPUID Intel Resource Director Technology (Intel RDT) Allocation Information\r | |
2290 | \r | |
2291 | @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10).\r | |
2292 | @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).\r | |
2293 | CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01).\r | |
2294 | CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02).\r | |
2295 | **/\r | |
2f88bd3a | 2296 | #define CPUID_INTEL_RDT_ALLOCATION 0x10\r |
236d5c66 RN |
2297 | \r |
2298 | /**\r | |
2299 | Intel Resource Director Technology (Intel RDT) Allocation Enumeration Sub-leaf\r | |
2300 | \r | |
2301 | @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)\r | |
2302 | @param ECX CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF (0x00).\r | |
2303 | \r | |
2304 | @retval EAX Reserved.\r | |
2305 | @retval EBX L3 and L2 Cache Allocation Technology information described by\r | |
2306 | the type CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX.\r | |
2307 | @retval ECX Reserved.\r | |
2308 | @retval EDX Reserved.\r | |
2309 | \r | |
2310 | <b>Example usage</b>\r | |
2311 | @code\r | |
2312 | CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX Ebx;\r | |
2313 | \r | |
2314 | AsmCpuidEx (\r | |
2315 | CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF,\r | |
2316 | NULL, &Ebx.Uint32, NULL, NULL\r | |
2317 | );\r | |
2318 | @endcode\r | |
2319 | **/\r | |
2f88bd3a | 2320 | #define CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF 0x00\r |
236d5c66 RN |
2321 | \r |
2322 | /**\r | |
2323 | CPUID L3 and L2 Cache Allocation Support Information EBX for CPUID leaf\r | |
2324 | #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r | |
2325 | #CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF.\r | |
2326 | **/\r | |
2327 | typedef union {\r | |
2328 | ///\r | |
2329 | /// Individual bit fields\r | |
2330 | ///\r | |
2331 | struct {\r | |
2f88bd3a | 2332 | UINT32 Reserved1 : 1;\r |
236d5c66 RN |
2333 | ///\r |
2334 | /// [Bit 1] Supports L3 Cache Allocation Technology if 1.\r | |
2335 | ///\r | |
2f88bd3a | 2336 | UINT32 L3CacheAllocation : 1;\r |
236d5c66 RN |
2337 | ///\r |
2338 | /// [Bit 2] Supports L2 Cache Allocation Technology if 1.\r | |
2339 | ///\r | |
2f88bd3a | 2340 | UINT32 L2CacheAllocation : 1;\r |
236d5c66 RN |
2341 | ///\r |
2342 | /// [Bit 3] Supports Memory Bandwidth Allocation if 1.\r | |
2343 | ///\r | |
2f88bd3a MK |
2344 | UINT32 MemoryBandwidth : 1;\r |
2345 | UINT32 Reserved3 : 28;\r | |
236d5c66 RN |
2346 | } Bits;\r |
2347 | ///\r | |
2348 | /// All bit fields as a 32-bit value\r | |
2349 | ///\r | |
2f88bd3a | 2350 | UINT32 Uint32;\r |
236d5c66 RN |
2351 | } CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX;\r |
2352 | \r | |
236d5c66 RN |
2353 | /**\r |
2354 | L3 Cache Allocation Technology Enumeration Sub-leaf\r | |
2355 | \r | |
2356 | @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)\r | |
2357 | @param ECX CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF (0x01)\r | |
2358 | \r | |
2359 | @retval EAX RESID L3 Cache Allocation Technology information described by\r | |
2360 | the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX.\r | |
2361 | @retval EBX Bit-granular map of isolation/contention of allocation units.\r | |
2362 | @retval ECX RESID L3 Cache Allocation Technology information described by\r | |
2363 | the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX.\r | |
2364 | @retval EDX RESID L3 Cache Allocation Technology information described by\r | |
2365 | the type CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX.\r | |
2366 | \r | |
2367 | <b>Example usage</b>\r | |
2368 | @code\r | |
2369 | CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX Eax;\r | |
2370 | UINT32 Ebx;\r | |
2371 | CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX Ecx;\r | |
2372 | CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Edx;\r | |
2373 | \r | |
2374 | AsmCpuidEx (\r | |
2375 | CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF,\r | |
2376 | &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32\r | |
2377 | );\r | |
2378 | @endcode\r | |
2379 | **/\r | |
2f88bd3a | 2380 | #define CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF 0x01\r |
236d5c66 RN |
2381 | \r |
2382 | /**\r | |
2383 | CPUID L3 Cache Allocation Technology Information EAX for CPUID leaf\r | |
2384 | #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r | |
2385 | #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.\r | |
2386 | **/\r | |
2387 | typedef union {\r | |
2388 | ///\r | |
2389 | /// Individual bit fields\r | |
2390 | ///\r | |
2391 | struct {\r | |
2392 | ///\r | |
2393 | /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID\r | |
2394 | /// using minus-one notation.\r | |
2395 | ///\r | |
2f88bd3a MK |
2396 | UINT32 CapacityLength : 5;\r |
2397 | UINT32 Reserved : 27;\r | |
236d5c66 RN |
2398 | } Bits;\r |
2399 | ///\r | |
2400 | /// All bit fields as a 32-bit value\r | |
2401 | ///\r | |
2f88bd3a | 2402 | UINT32 Uint32;\r |
236d5c66 RN |
2403 | } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX;\r |
2404 | \r | |
2405 | /**\r | |
2406 | CPUID L3 Cache Allocation Technology Information ECX for CPUID leaf\r | |
2407 | #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r | |
2408 | #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.\r | |
2409 | **/\r | |
2410 | typedef union {\r | |
2411 | ///\r | |
2412 | /// Individual bit fields\r | |
2413 | ///\r | |
2414 | struct {\r | |
2f88bd3a | 2415 | UINT32 Reserved3 : 2;\r |
236d5c66 RN |
2416 | ///\r |
2417 | /// [Bit 2] Code and Data Prioritization Technology supported if 1.\r | |
2418 | ///\r | |
2f88bd3a MK |
2419 | UINT32 CodeDataPrioritization : 1;\r |
2420 | UINT32 Reserved2 : 29;\r | |
236d5c66 RN |
2421 | } Bits;\r |
2422 | ///\r | |
2423 | /// All bit fields as a 32-bit value\r | |
2424 | ///\r | |
2f88bd3a | 2425 | UINT32 Uint32;\r |
236d5c66 RN |
2426 | } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX;\r |
2427 | \r | |
2428 | /**\r | |
2429 | CPUID L3 Cache Allocation Technology Information EDX for CPUID leaf\r | |
2430 | #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r | |
2431 | #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.\r | |
2432 | **/\r | |
2433 | typedef union {\r | |
2434 | ///\r | |
2435 | /// Individual bit fields\r | |
2436 | ///\r | |
2437 | struct {\r | |
2438 | ///\r | |
2439 | /// [Bits 15:0] Highest COS number supported for this ResID.\r | |
2440 | ///\r | |
2f88bd3a MK |
2441 | UINT32 HighestCosNumber : 16;\r |
2442 | UINT32 Reserved : 16;\r | |
236d5c66 RN |
2443 | } Bits;\r |
2444 | ///\r | |
2445 | /// All bit fields as a 32-bit value\r | |
2446 | ///\r | |
2f88bd3a | 2447 | UINT32 Uint32;\r |
236d5c66 RN |
2448 | } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX;\r |
2449 | \r | |
2450 | /**\r | |
2451 | L2 Cache Allocation Technology Enumeration Sub-leaf\r | |
2452 | \r | |
2453 | @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)\r | |
2454 | @param ECX CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF (0x02)\r | |
2455 | \r | |
2456 | @retval EAX RESID L2 Cache Allocation Technology information described by\r | |
2457 | the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX.\r | |
2458 | @retval EBX Bit-granular map of isolation/contention of allocation units.\r | |
2459 | @retval ECX Reserved.\r | |
2460 | @retval EDX RESID L2 Cache Allocation Technology information described by\r | |
2461 | the type CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX.\r | |
2462 | \r | |
2463 | <b>Example usage</b>\r | |
2464 | @code\r | |
2465 | CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Eax;\r | |
2466 | UINT32 Ebx;\r | |
2467 | CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Edx;\r | |
2468 | \r | |
2469 | AsmCpuidEx (\r | |
2470 | CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF,\r | |
2471 | &Eax.Uint32, &Ebx, NULL, &Edx.Uint32\r | |
2472 | );\r | |
2473 | @endcode\r | |
2474 | **/\r | |
2f88bd3a | 2475 | #define CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF 0x02\r |
236d5c66 RN |
2476 | \r |
2477 | /**\r | |
2478 | CPUID L2 Cache Allocation Technology Information EAX for CPUID leaf\r | |
2479 | #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r | |
2480 | #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.\r | |
2481 | **/\r | |
2482 | typedef union {\r | |
2483 | ///\r | |
2484 | /// Individual bit fields\r | |
2485 | ///\r | |
2486 | struct {\r | |
2487 | ///\r | |
2488 | /// [Bits 4:0] Length of the capacity bit mask for the corresponding ResID\r | |
2489 | /// using minus-one notation.\r | |
2490 | ///\r | |
2f88bd3a MK |
2491 | UINT32 CapacityLength : 5;\r |
2492 | UINT32 Reserved : 27;\r | |
236d5c66 RN |
2493 | } Bits;\r |
2494 | ///\r | |
2495 | /// All bit fields as a 32-bit value\r | |
2496 | ///\r | |
2f88bd3a | 2497 | UINT32 Uint32;\r |
236d5c66 RN |
2498 | } CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX;\r |
2499 | \r | |
2500 | /**\r | |
2501 | CPUID L2 Cache Allocation Technology Information EDX for CPUID leaf\r | |
2502 | #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r | |
2503 | #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.\r | |
2504 | **/\r | |
2505 | typedef union {\r | |
2506 | ///\r | |
2507 | /// Individual bit fields\r | |
2508 | ///\r | |
2509 | struct {\r | |
2510 | ///\r | |
2511 | /// [Bits 15:0] Highest COS number supported for this ResID.\r | |
2512 | ///\r | |
2f88bd3a MK |
2513 | UINT32 HighestCosNumber : 16;\r |
2514 | UINT32 Reserved : 16;\r | |
236d5c66 RN |
2515 | } Bits;\r |
2516 | ///\r | |
2517 | /// All bit fields as a 32-bit value\r | |
2518 | ///\r | |
2f88bd3a | 2519 | UINT32 Uint32;\r |
236d5c66 RN |
2520 | } CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX;\r |
2521 | \r | |
2522 | /**\r | |
2523 | Memory Bandwidth Allocation Enumeration Sub-leaf\r | |
2524 | \r | |
2525 | @param EAX CPUID_INTEL_RDT_ALLOCATION (0x10)\r | |
2526 | @param ECX CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF (0x03)\r | |
2527 | \r | |
2528 | @retval EAX RESID memory bandwidth Allocation Technology information\r | |
2529 | described by the type\r | |
2530 | CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX.\r | |
2531 | @retval EBX Reserved.\r | |
2532 | @retval ECX RESID memory bandwidth Allocation Technology information\r | |
2533 | described by the type\r | |
2534 | CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX.\r | |
2535 | @retval EDX RESID memory bandwidth Allocation Technology information\r | |
2536 | described by the type\r | |
2537 | CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX.\r | |
2538 | \r | |
2539 | <b>Example usage</b>\r | |
2540 | @code\r | |
2541 | CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX Eax;\r | |
2542 | UINT32 Ebx;\r | |
2543 | CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX Ecx;\r | |
2544 | CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX Edx;\r | |
2545 | \r | |
2546 | \r | |
2547 | AsmCpuidEx (\r | |
2548 | CPUID_INTEL_RDT_ALLOCATION, CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF,\r | |
2549 | &Eax.Uint32, &Ebx, NULL, &Edx.Uint32\r | |
2550 | );\r | |
2551 | @endcode\r | |
2552 | **/\r | |
2f88bd3a | 2553 | #define CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF 0x03\r |
236d5c66 RN |
2554 | \r |
2555 | /**\r | |
2556 | CPUID memory bandwidth Allocation Technology Information EAX for CPUID leaf\r | |
2557 | #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r | |
2558 | #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF.\r | |
2559 | **/\r | |
2560 | typedef union {\r | |
2561 | ///\r | |
2562 | /// Individual bit fields\r | |
2563 | ///\r | |
2564 | struct {\r | |
2565 | ///\r | |
2566 | /// [Bits 11:0] Reports the maximum MBA throttling value supported for\r | |
2567 | /// the corresponding ResID using minus-one notation.\r | |
2568 | ///\r | |
2f88bd3a MK |
2569 | UINT32 MaximumMBAThrottling : 12;\r |
2570 | UINT32 Reserved : 20;\r | |
236d5c66 RN |
2571 | } Bits;\r |
2572 | ///\r | |
2573 | /// All bit fields as a 32-bit value\r | |
2574 | ///\r | |
2f88bd3a | 2575 | UINT32 Uint32;\r |
236d5c66 RN |
2576 | } CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EAX;\r |
2577 | \r | |
2578 | /**\r | |
2579 | CPUID memory bandwidth Allocation Technology Information ECX for CPUID leaf\r | |
2580 | #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r | |
2581 | #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF.\r | |
2582 | **/\r | |
2583 | typedef union {\r | |
2584 | ///\r | |
2585 | /// Individual bit fields\r | |
2586 | ///\r | |
2587 | struct {\r | |
2588 | ///\r | |
2589 | /// [Bits 1:0] Reserved.\r | |
2590 | ///\r | |
2f88bd3a | 2591 | UINT32 Reserved1 : 2;\r |
236d5c66 RN |
2592 | ///\r |
2593 | /// [Bits 3] Reports whether the response of the delay values is linear.\r | |
2594 | ///\r | |
2f88bd3a MK |
2595 | UINT32 Liner : 1;\r |
2596 | UINT32 Reserved2 : 29;\r | |
236d5c66 RN |
2597 | } Bits;\r |
2598 | ///\r | |
2599 | /// All bit fields as a 32-bit value\r | |
2600 | ///\r | |
2f88bd3a | 2601 | UINT32 Uint32;\r |
236d5c66 RN |
2602 | } CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_ECX;\r |
2603 | \r | |
2604 | /**\r | |
2605 | CPUID memory bandwidth Allocation Technology Information EDX for CPUID leaf\r | |
2606 | #CPUID_INTEL_RDT_ALLOCATION, sub-leaf\r | |
2607 | #CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF.\r | |
2608 | **/\r | |
2609 | typedef union {\r | |
2610 | ///\r | |
2611 | /// Individual bit fields\r | |
2612 | ///\r | |
2613 | struct {\r | |
2614 | ///\r | |
2615 | /// [Bits 15:0] Highest COS number supported for this ResID.\r | |
2616 | ///\r | |
2f88bd3a MK |
2617 | UINT32 HighestCosNumber : 16;\r |
2618 | UINT32 Reserved : 16;\r | |
236d5c66 RN |
2619 | } Bits;\r |
2620 | ///\r | |
2621 | /// All bit fields as a 32-bit value\r | |
2622 | ///\r | |
2f88bd3a | 2623 | UINT32 Uint32;\r |
236d5c66 RN |
2624 | } CPUID_INTEL_RDT_ALLOCATION_MEMORY_BANDWIDTH_SUB_LEAF_EDX;\r |
2625 | \r | |
2626 | /**\r | |
2627 | Intel SGX resource capability and configuration.\r | |
2628 | See Section 37.7.2 "Intel(R) SGX Resource Enumeration Leaves".\r | |
2629 | \r | |
2630 | If CPUID.(EAX=07H, ECX=0H):EBX.SGX = 1, the processor also supports querying\r | |
2631 | CPUID with EAX=12H on Intel SGX resource capability and configuration.\r | |
2632 | \r | |
2633 | @param EAX CPUID_INTEL_SGX (0x12)\r | |
2634 | @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00).\r | |
2635 | CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01).\r | |
2636 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02).\r | |
2637 | Sub leafs 2..n based on the sub-leaf-type encoding (returned in EAX[3:0])\r | |
2638 | until the sub-leaf type is invalid.\r | |
2639 | \r | |
2640 | **/\r | |
2f88bd3a | 2641 | #define CPUID_INTEL_SGX 0x12\r |
236d5c66 RN |
2642 | \r |
2643 | /**\r | |
2644 | Sub-Leaf 0 Enumeration of Intel SGX Capabilities.\r | |
2645 | Enumerates Intel SGX capability, including enclave instruction opcode support.\r | |
2646 | \r | |
2647 | @param EAX CPUID_INTEL_SGX (0x12)\r | |
2648 | @param ECX CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF (0x00)\r | |
2649 | \r | |
2650 | @retval EAX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is\r | |
2651 | described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX.\r | |
2652 | @retval EBX MISCSELECT: Reports the bit vector of supported extended features\r | |
2653 | that can be written to the MISC region of the SSA.\r | |
2654 | @retval ECX Reserved.\r | |
2655 | @retval EDX The format of Sub-Leaf 0 Enumeration of Intel SGX Capabilities is\r | |
2656 | described by the type CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX.\r | |
2657 | \r | |
2658 | <b>Example usage</b>\r | |
2659 | @code\r | |
2660 | CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Eax;\r | |
2661 | UINT32 Ebx;\r | |
2662 | CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Edx;\r | |
2663 | \r | |
2664 | AsmCpuidEx (\r | |
2665 | CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF,\r | |
2666 | &Eax.Uint32, &Ebx, NULL, &Edx.Uint32\r | |
2667 | );\r | |
2668 | @endcode\r | |
2669 | **/\r | |
2f88bd3a | 2670 | #define CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF 0x00\r |
236d5c66 RN |
2671 | \r |
2672 | /**\r | |
2673 | Sub-Leaf 0 Enumeration of Intel SGX Capabilities EAX for CPUID leaf #CPUID_INTEL_SGX,\r | |
2674 | sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.\r | |
2675 | **/\r | |
2676 | typedef union {\r | |
2677 | ///\r | |
2678 | /// Individual bit fields\r | |
2679 | ///\r | |
2680 | struct {\r | |
2681 | ///\r | |
2682 | /// [Bit 0] If 1, indicates leaf functions of SGX1 instruction are supported.\r | |
2683 | ///\r | |
2f88bd3a | 2684 | UINT32 SGX1 : 1;\r |
236d5c66 RN |
2685 | ///\r |
2686 | /// [Bit 1] If 1, indicates leaf functions of SGX2 instruction are supported.\r | |
2687 | ///\r | |
2f88bd3a MK |
2688 | UINT32 SGX2 : 1;\r |
2689 | UINT32 Reserved1 : 3;\r | |
236d5c66 RN |
2690 | ///\r |
2691 | /// [Bit 5] If 1, indicates Intel SGX supports ENCLV instruction leaves\r | |
2692 | /// EINCVIRTCHILD, EDECVIRTCHILD, and ESETCONTEXT.\r | |
2693 | ///\r | |
2f88bd3a | 2694 | UINT32 ENCLV : 1;\r |
236d5c66 RN |
2695 | ///\r |
2696 | /// [Bit 6] If 1, indicates Intel SGX supports ENCLS instruction leaves ETRACKC,\r | |
2697 | /// ERDINFO, ELDBC, and ELDUC.\r | |
2698 | ///\r | |
2f88bd3a MK |
2699 | UINT32 ENCLS : 1;\r |
2700 | UINT32 Reserved2 : 25;\r | |
236d5c66 RN |
2701 | } Bits;\r |
2702 | ///\r | |
2703 | /// All bit fields as a 32-bit value\r | |
2704 | ///\r | |
2f88bd3a | 2705 | UINT32 Uint32;\r |
236d5c66 RN |
2706 | } CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX;\r |
2707 | \r | |
2708 | /**\r | |
2709 | Sub-Leaf 0 Enumeration of Intel SGX Capabilities EDX for CPUID leaf #CPUID_INTEL_SGX,\r | |
2710 | sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.\r | |
2711 | **/\r | |
2712 | typedef union {\r | |
2713 | ///\r | |
2714 | /// Individual bit fields\r | |
2715 | ///\r | |
2716 | struct {\r | |
2717 | ///\r | |
2718 | /// [Bit 7:0] The maximum supported enclave size is 2^(EDX[7:0]) bytes\r | |
2719 | /// when not in 64-bit mode.\r | |
2720 | ///\r | |
2f88bd3a | 2721 | UINT32 MaxEnclaveSize_Not64 : 8;\r |
236d5c66 RN |
2722 | ///\r |
2723 | /// [Bit 15:8] The maximum supported enclave size is 2^(EDX[15:8]) bytes\r | |
2724 | /// when operating in 64-bit mode.\r | |
2725 | ///\r | |
2f88bd3a MK |
2726 | UINT32 MaxEnclaveSize_64 : 8;\r |
2727 | UINT32 Reserved : 16;\r | |
236d5c66 RN |
2728 | } Bits;\r |
2729 | ///\r | |
2730 | /// All bit fields as a 32-bit value\r | |
2731 | ///\r | |
2f88bd3a | 2732 | UINT32 Uint32;\r |
236d5c66 RN |
2733 | } CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX;\r |
2734 | \r | |
236d5c66 RN |
2735 | /**\r |
2736 | Sub-Leaf 1 Enumeration of Intel SGX Capabilities.\r | |
2737 | Enumerates Intel SGX capability of processor state configuration and enclave\r | |
2738 | configuration in the SECS structure.\r | |
2739 | \r | |
2740 | @param EAX CPUID_INTEL_SGX (0x12)\r | |
2741 | @param ECX CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF (0x01)\r | |
2742 | \r | |
2743 | @retval EAX Report the valid bits of SECS.ATTRIBUTES[31:0] that software can\r | |
2744 | set with ECREATE. SECS.ATTRIBUTES[n] can be set to 1 using ECREATE\r | |
2745 | only if EAX[n] is 1, where n < 32.\r | |
2746 | @retval EBX Report the valid bits of SECS.ATTRIBUTES[63:32] that software can\r | |
2747 | set with ECREATE. SECS.ATTRIBUTES[n+32] can be set to 1 using ECREATE\r | |
2748 | only if EBX[n] is 1, where n < 32.\r | |
2749 | @retval ECX Report the valid bits of SECS.ATTRIBUTES[95:64] that software can\r | |
2750 | set with ECREATE. SECS.ATTRIBUTES[n+64] can be set to 1 using ECREATE\r | |
2751 | only if ECX[n] is 1, where n < 32.\r | |
2752 | @retval EDX Report the valid bits of SECS.ATTRIBUTES[127:96] that software can\r | |
2753 | set with ECREATE. SECS.ATTRIBUTES[n+96] can be set to 1 using ECREATE\r | |
2754 | only if EDX[n] is 1, where n < 32.\r | |
2755 | \r | |
2756 | <b>Example usage</b>\r | |
2757 | @code\r | |
2758 | UINT32 Eax;\r | |
2759 | UINT32 Ebx;\r | |
2760 | UINT32 Ecx;\r | |
2761 | UINT32 Edx;\r | |
2762 | \r | |
2763 | AsmCpuidEx (\r | |
2764 | CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF,\r | |
2765 | &Eax, &Ebx, &Ecx, &Edx\r | |
2766 | );\r | |
2767 | @endcode\r | |
2768 | **/\r | |
2f88bd3a | 2769 | #define CPUID_INTEL_SGX_CAPABILITIES_1_SUB_LEAF 0x01\r |
236d5c66 RN |
2770 | \r |
2771 | /**\r | |
2772 | Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources.\r | |
2773 | Enumerates available EPC resources.\r | |
2774 | \r | |
2775 | @param EAX CPUID_INTEL_SGX (0x12)\r | |
2776 | @param ECX CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF (0x02)\r | |
2777 | \r | |
2778 | @retval EAX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX\r | |
2779 | Resources is described by the type\r | |
2780 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX.\r | |
2781 | @retval EBX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX\r | |
2782 | Resources is described by the type\r | |
2783 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX.\r | |
2784 | @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX\r | |
2785 | Resources is described by the type\r | |
2786 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX.\r | |
2787 | @retval EDX The format of Sub-Leaf Index 2 or Higher Enumeration of Intel SGX\r | |
2788 | Resources is described by the type\r | |
2789 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX.\r | |
2790 | \r | |
2791 | <b>Example usage</b>\r | |
2792 | @code\r | |
2793 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Eax;\r | |
2794 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Ebx;\r | |
2795 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Ecx;\r | |
2796 | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Edx;\r | |
2797 | \r | |
2798 | AsmCpuidEx (\r | |
2799 | CPUID_INTEL_SGX, CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF,\r | |
2800 | &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r | |
2801 | );\r | |
2802 | @endcode\r | |
2803 | **/\r | |
2804 | #define CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF 0x02\r | |
2805 | \r | |
2806 | /**\r | |
2807 | Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EAX for CPUID\r | |
2808 | leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.\r | |
2809 | **/\r | |
2810 | typedef union {\r | |
2811 | ///\r | |
2812 | /// Individual bit fields\r | |
2813 | ///\r | |
2814 | struct {\r | |
2815 | ///\r | |
2816 | /// [Bit 3:0] Sub-leaf-type encoding.\r | |
2817 | /// 0000b: This sub-leaf is invalid, EBX:EAX and EDX:ECX report 0.\r | |
2818 | /// 0001b: This sub-leaf provides information on the Enclave Page Cache (EPC)\r | |
2819 | /// in EBX:EAX and EDX:ECX.\r | |
2820 | /// All other encoding are reserved.\r | |
2821 | ///\r | |
2f88bd3a MK |
2822 | UINT32 SubLeafType : 4;\r |
2823 | UINT32 Reserved : 8;\r | |
236d5c66 RN |
2824 | ///\r |
2825 | /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the physical address of\r | |
2826 | /// the base of the EPC section.\r | |
2827 | ///\r | |
2f88bd3a | 2828 | UINT32 LowAddressOfEpcSection : 20;\r |
236d5c66 RN |
2829 | } Bits;\r |
2830 | ///\r | |
2831 | /// All bit fields as a 32-bit value\r | |
2832 | ///\r | |
2f88bd3a | 2833 | UINT32 Uint32;\r |
236d5c66 RN |
2834 | } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX;\r |
2835 | \r | |
2836 | /**\r | |
2837 | Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EBX for CPUID\r | |
2838 | leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.\r | |
2839 | **/\r | |
2840 | typedef union {\r | |
2841 | ///\r | |
2842 | /// Individual bit fields\r | |
2843 | ///\r | |
2844 | struct {\r | |
2845 | ///\r | |
2846 | /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the physical address of\r | |
2847 | /// the base of the EPC section.\r | |
2848 | ///\r | |
2f88bd3a MK |
2849 | UINT32 HighAddressOfEpcSection : 20;\r |
2850 | UINT32 Reserved : 12;\r | |
236d5c66 RN |
2851 | } Bits;\r |
2852 | ///\r | |
2853 | /// All bit fields as a 32-bit value\r | |
2854 | ///\r | |
2f88bd3a | 2855 | UINT32 Uint32;\r |
236d5c66 RN |
2856 | } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX;\r |
2857 | \r | |
2858 | /**\r | |
2859 | Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources ECX for CPUID\r | |
2860 | leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.\r | |
2861 | **/\r | |
2862 | typedef union {\r | |
2863 | ///\r | |
2864 | /// Individual bit fields\r | |
2865 | ///\r | |
2866 | struct {\r | |
2867 | ///\r | |
2868 | /// [Bit 3:0] The EPC section encoding.\r | |
2869 | /// 0000b: Not valid.\r | |
2870 | /// 0001b: The EPC section is confidentiality, integrity and replay protected.\r | |
2871 | /// All other encoding are reserved.\r | |
2872 | ///\r | |
2f88bd3a MK |
2873 | UINT32 EpcSection : 4;\r |
2874 | UINT32 Reserved : 8;\r | |
236d5c66 RN |
2875 | ///\r |
2876 | /// [Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the size of the\r | |
2877 | /// corresponding EPC section within the Processor Reserved Memory.\r | |
2878 | ///\r | |
2f88bd3a | 2879 | UINT32 LowSizeOfEpcSection : 20;\r |
236d5c66 RN |
2880 | } Bits;\r |
2881 | ///\r | |
2882 | /// All bit fields as a 32-bit value\r | |
2883 | ///\r | |
2f88bd3a | 2884 | UINT32 Uint32;\r |
236d5c66 RN |
2885 | } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX;\r |
2886 | \r | |
2887 | /**\r | |
2888 | Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EDX for CPUID\r | |
2889 | leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.\r | |
2890 | **/\r | |
2891 | typedef union {\r | |
2892 | ///\r | |
2893 | /// Individual bit fields\r | |
2894 | ///\r | |
2895 | struct {\r | |
2896 | ///\r | |
2897 | /// [Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the size of the\r | |
2898 | /// corresponding EPC section within the Processor Reserved Memory.\r | |
2899 | ///\r | |
2f88bd3a MK |
2900 | UINT32 HighSizeOfEpcSection : 20;\r |
2901 | UINT32 Reserved : 12;\r | |
236d5c66 RN |
2902 | } Bits;\r |
2903 | ///\r | |
2904 | /// All bit fields as a 32-bit value\r | |
2905 | ///\r | |
2f88bd3a | 2906 | UINT32 Uint32;\r |
236d5c66 RN |
2907 | } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX;\r |
2908 | \r | |
236d5c66 RN |
2909 | /**\r |
2910 | CPUID Intel Processor Trace Information\r | |
2911 | \r | |
2912 | @param EAX CPUID_INTEL_PROCESSOR_TRACE (0x14)\r | |
2913 | @param ECX CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF (0x00).\r | |
2914 | CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01).\r | |
2915 | \r | |
2916 | **/\r | |
2f88bd3a | 2917 | #define CPUID_INTEL_PROCESSOR_TRACE 0x14\r |
236d5c66 RN |
2918 | \r |
2919 | /**\r | |
2920 | CPUID Intel Processor Trace Information Main Leaf\r | |
2921 | \r | |
2922 | @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)\r | |
2923 | @param ECX CPUID_INTEL_PROCEDSSOR_TRACE_MAIN_LEAF (0x00)\r | |
2924 | \r | |
2925 | @retval EAX Reports the maximum sub-leaf supported in leaf 14H.\r | |
2926 | @retval EBX Returns Intel processor trace information described by the\r | |
2927 | type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX.\r | |
2928 | @retval ECX Returns Intel processor trace information described by the\r | |
2929 | type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX.\r | |
2930 | @retval EDX Reserved.\r | |
2931 | \r | |
2932 | <b>Example usage</b>\r | |
2933 | @code\r | |
2934 | UINT32 Eax;\r | |
2935 | CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx;\r | |
2936 | CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;\r | |
2937 | \r | |
2938 | AsmCpuidEx (\r | |
2939 | CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,\r | |
2940 | &Eax, &Ebx.Uint32, &Ecx.Uint32, NULL\r | |
2941 | );\r | |
2942 | @endcode\r | |
2943 | **/\r | |
2f88bd3a | 2944 | #define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00\r |
236d5c66 RN |
2945 | \r |
2946 | /**\r | |
2947 | CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,\r | |
2948 | sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.\r | |
2949 | **/\r | |
2950 | typedef union {\r | |
2951 | ///\r | |
2952 | /// Individual bit fields\r | |
2953 | ///\r | |
2954 | struct {\r | |
2955 | ///\r | |
2956 | /// [Bit 0] If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,\r | |
2957 | /// and that IA32_RTIT_CR3_MATCH MSR can be accessed.\r | |
2958 | ///\r | |
2f88bd3a | 2959 | UINT32 Cr3Filter : 1;\r |
236d5c66 RN |
2960 | ///\r |
2961 | /// [Bit 1] If 1, indicates support of Configurable PSB and Cycle-Accurate\r | |
2962 | /// Mode.\r | |
2963 | ///\r | |
2f88bd3a | 2964 | UINT32 ConfigurablePsb : 1;\r |
236d5c66 RN |
2965 | ///\r |
2966 | /// [Bit 2] If 1, indicates support of IP Filtering, TraceStop filtering,\r | |
2967 | /// and preservation of Intel PT MSRs across warm reset.\r | |
2968 | ///\r | |
2f88bd3a | 2969 | UINT32 IpTraceStopFiltering : 1;\r |
236d5c66 RN |
2970 | ///\r |
2971 | /// [Bit 3] If 1, indicates support of MTC timing packet and suppression of\r | |
2972 | /// COFI-based packets.\r | |
2973 | ///\r | |
2f88bd3a | 2974 | UINT32 Mtc : 1;\r |
236d5c66 RN |
2975 | ///\r |
2976 | /// [Bit 4] If 1, indicates support of PTWRITE. Writes can set\r | |
2977 | /// IA32_RTIT_CTL[12] (PTWEn) and IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE\r | |
2978 | /// can generate packets.\r | |
2979 | ///\r | |
2f88bd3a | 2980 | UINT32 PTWrite : 1;\r |
236d5c66 RN |
2981 | ///\r |
2982 | /// [Bit 5] If 1, indicates support of Power Event Trace. Writes can set\r | |
2983 | /// IA32_RTIT_CTL[4] (PwrEvtEn), enabling Power Event Trace packet\r | |
2984 | /// generation.\r | |
2985 | ///\r | |
2f88bd3a MK |
2986 | UINT32 PowerEventTrace : 1;\r |
2987 | UINT32 Reserved : 26;\r | |
236d5c66 RN |
2988 | } Bits;\r |
2989 | ///\r | |
2990 | /// All bit fields as a 32-bit value\r | |
2991 | ///\r | |
2f88bd3a | 2992 | UINT32 Uint32;\r |
236d5c66 RN |
2993 | } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX;\r |
2994 | \r | |
2995 | /**\r | |
2996 | CPUID Intel Processor Trace ECX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,\r | |
2997 | sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.\r | |
2998 | **/\r | |
2999 | typedef union {\r | |
3000 | ///\r | |
3001 | /// Individual bit fields\r | |
3002 | ///\r | |
3003 | struct {\r | |
3004 | ///\r | |
3005 | /// [Bit 0] If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence\r | |
3006 | /// utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and\r | |
3007 | /// IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.\r | |
3008 | ///\r | |
2f88bd3a | 3009 | UINT32 RTIT : 1;\r |
236d5c66 RN |
3010 | ///\r |
3011 | /// [Bit 1] If 1, ToPA tables can hold any number of output entries, up to\r | |
3012 | /// the maximum allowed by the MaskOrTableOffset field of\r | |
3013 | /// IA32_RTIT_OUTPUT_MASK_PTRS.\r | |
3014 | ///\r | |
2f88bd3a | 3015 | UINT32 ToPA : 1;\r |
236d5c66 RN |
3016 | ///\r |
3017 | /// [Bit 2] If 1, indicates support of Single-Range Output scheme.\r | |
3018 | ///\r | |
2f88bd3a | 3019 | UINT32 SingleRangeOutput : 1;\r |
236d5c66 RN |
3020 | ///\r |
3021 | /// [Bit 3] If 1, indicates support of output to Trace Transport subsystem.\r | |
3022 | ///\r | |
2f88bd3a MK |
3023 | UINT32 TraceTransportSubsystem : 1;\r |
3024 | UINT32 Reserved : 27;\r | |
236d5c66 RN |
3025 | ///\r |
3026 | /// [Bit 31] If 1, generated packets which contain IP payloads have LIP\r | |
3027 | /// values, which include the CS base component.\r | |
3028 | ///\r | |
2f88bd3a | 3029 | UINT32 LIP : 1;\r |
236d5c66 RN |
3030 | } Bits;\r |
3031 | ///\r | |
3032 | /// All bit fields as a 32-bit value\r | |
3033 | ///\r | |
2f88bd3a | 3034 | UINT32 Uint32;\r |
236d5c66 RN |
3035 | } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX;\r |
3036 | \r | |
236d5c66 RN |
3037 | /**\r |
3038 | CPUID Intel Processor Trace Information Sub-leaf\r | |
3039 | \r | |
3040 | @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)\r | |
3041 | @param ECX CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01)\r | |
3042 | \r | |
3043 | @retval EAX Returns Intel processor trace information described by the\r | |
3044 | type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX.\r | |
3045 | @retval EBX Returns Intel processor trace information described by the\r | |
3046 | type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX.\r | |
3047 | @retval ECX Reserved.\r | |
3048 | @retval EDX Reserved.\r | |
3049 | \r | |
3050 | <b>Example usage</b>\r | |
3051 | @code\r | |
3052 | UINT32 MaximumSubLeaf;\r | |
3053 | UINT32 SubLeaf;\r | |
3054 | CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX Eax;\r | |
3055 | CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX Ebx;\r | |
3056 | \r | |
3057 | AsmCpuidEx (\r | |
3058 | CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,\r | |
3059 | &MaximumSubLeaf, NULL, NULL, NULL\r | |
3060 | );\r | |
3061 | \r | |
3062 | for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {\r | |
3063 | AsmCpuidEx (\r | |
3064 | CPUID_INTEL_PROCESSOR_TRACE, SubLeaf,\r | |
3065 | &Eax.Uint32, &Ebx.Uint32, NULL, NULL\r | |
3066 | );\r | |
3067 | }\r | |
3068 | @endcode\r | |
3069 | **/\r | |
2f88bd3a | 3070 | #define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01\r |
236d5c66 RN |
3071 | \r |
3072 | /**\r | |
3073 | CPUID Intel Processor Trace EAX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,\r | |
3074 | sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.\r | |
3075 | **/\r | |
3076 | typedef union {\r | |
3077 | ///\r | |
3078 | /// Individual bit fields\r | |
3079 | ///\r | |
3080 | struct {\r | |
3081 | ///\r | |
3082 | /// [Bits 2:0] Number of configurable Address Ranges for filtering.\r | |
3083 | ///\r | |
2f88bd3a MK |
3084 | UINT32 ConfigurableAddressRanges : 3;\r |
3085 | UINT32 Reserved : 13;\r | |
236d5c66 RN |
3086 | ///\r |
3087 | /// [Bits 31:16] Bitmap of supported MTC period encodings\r | |
3088 | ///\r | |
2f88bd3a | 3089 | UINT32 MtcPeriodEncodings : 16;\r |
236d5c66 RN |
3090 | } Bits;\r |
3091 | ///\r | |
3092 | /// All bit fields as a 32-bit value\r | |
3093 | ///\r | |
2f88bd3a | 3094 | UINT32 Uint32;\r |
236d5c66 RN |
3095 | } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX;\r |
3096 | \r | |
3097 | /**\r | |
3098 | CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,\r | |
3099 | sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.\r | |
3100 | **/\r | |
3101 | typedef union {\r | |
3102 | ///\r | |
3103 | /// Individual bit fields\r | |
3104 | ///\r | |
3105 | struct {\r | |
3106 | ///\r | |
3107 | /// [Bits 15:0] Bitmap of supported Cycle Threshold value encodings.\r | |
3108 | ///\r | |
2f88bd3a | 3109 | UINT32 CycleThresholdEncodings : 16;\r |
236d5c66 RN |
3110 | ///\r |
3111 | /// [Bits 31:16] Bitmap of supported Configurable PSB frequency encodings.\r | |
3112 | ///\r | |
2f88bd3a | 3113 | UINT32 PsbFrequencyEncodings : 16;\r |
236d5c66 RN |
3114 | } Bits;\r |
3115 | ///\r | |
3116 | /// All bit fields as a 32-bit value\r | |
3117 | ///\r | |
2f88bd3a | 3118 | UINT32 Uint32;\r |
236d5c66 RN |
3119 | } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX;\r |
3120 | \r | |
236d5c66 RN |
3121 | /**\r |
3122 | CPUID Time Stamp Counter and Nominal Core Crystal Clock Information\r | |
3123 | \r | |
3124 | @note\r | |
3125 | If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated.\r | |
3126 | EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core\r | |
3127 | crystal clock frequency.\r | |
3128 | If ECX is 0, the nominal core crystal clock frequency is not enumerated.\r | |
3129 | "TSC frequency" = "core crystal clock frequency" * EBX/EAX.\r | |
3130 | The core crystal clock may differ from the reference clock, bus clock, or core\r | |
3131 | clock frequencies.\r | |
3132 | \r | |
3133 | @param EAX CPUID_TIME_STAMP_COUNTER (0x15)\r | |
3134 | \r | |
3135 | @retval EAX An unsigned integer which is the denominator of the\r | |
3136 | TSC/"core crystal clock" ratio\r | |
3137 | @retval EBX An unsigned integer which is the numerator of the\r | |
3138 | TSC/"core crystal clock" ratio.\r | |
3139 | @retval ECX An unsigned integer which is the nominal frequency\r | |
3140 | of the core crystal clock in Hz.\r | |
3141 | @retval EDX Reserved.\r | |
3142 | \r | |
3143 | <b>Example usage</b>\r | |
3144 | @code\r | |
3145 | UINT32 Eax;\r | |
3146 | UINT32 Ebx;\r | |
3147 | UINT32 Ecx;\r | |
3148 | \r | |
3149 | AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, &Ecx, NULL);\r | |
3150 | @endcode\r | |
3151 | **/\r | |
2f88bd3a | 3152 | #define CPUID_TIME_STAMP_COUNTER 0x15\r |
236d5c66 RN |
3153 | \r |
3154 | /**\r | |
3155 | CPUID Processor Frequency Information\r | |
3156 | \r | |
3157 | @note\r | |
3158 | Data is returned from this interface in accordance with the processor's\r | |
3159 | specification and does not reflect actual values. Suitable use of this data\r | |
3160 | includes the display of processor information in like manner to the processor\r | |
3161 | brand string and for determining the appropriate range to use when displaying\r | |
3162 | processor information e.g. frequency history graphs. The returned information\r | |
3163 | should not be used for any other purpose as the returned information does not\r | |
3164 | accurately correlate to information / counters returned by other processor\r | |
3165 | interfaces. While a processor may support the Processor Frequency Information\r | |
3166 | leaf, fields that return a value of zero are not supported.\r | |
3167 | \r | |
3168 | @param EAX CPUID_TIME_STAMP_COUNTER (0x16)\r | |
3169 | \r | |
3170 | @retval EAX Returns processor base frequency information described by the\r | |
3171 | type CPUID_PROCESSOR_FREQUENCY_EAX.\r | |
3172 | @retval EBX Returns maximum frequency information described by the type\r | |
3173 | CPUID_PROCESSOR_FREQUENCY_EBX.\r | |
3174 | @retval ECX Returns bus frequency information described by the type\r | |
3175 | CPUID_PROCESSOR_FREQUENCY_ECX.\r | |
3176 | @retval EDX Reserved.\r | |
3177 | \r | |
3178 | <b>Example usage</b>\r | |
3179 | @code\r | |
3180 | CPUID_PROCESSOR_FREQUENCY_EAX Eax;\r | |
3181 | CPUID_PROCESSOR_FREQUENCY_EBX Ebx;\r | |
3182 | CPUID_PROCESSOR_FREQUENCY_ECX Ecx;\r | |
3183 | \r | |
3184 | AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);\r | |
3185 | @endcode\r | |
3186 | **/\r | |
2f88bd3a | 3187 | #define CPUID_PROCESSOR_FREQUENCY 0x16\r |
236d5c66 RN |
3188 | \r |
3189 | /**\r | |
3190 | CPUID Processor Frequency Information EAX for CPUID leaf\r | |
3191 | #CPUID_PROCESSOR_FREQUENCY.\r | |
3192 | **/\r | |
3193 | typedef union {\r | |
3194 | ///\r | |
3195 | /// Individual bit fields\r | |
3196 | ///\r | |
3197 | struct {\r | |
3198 | ///\r | |
3199 | /// [Bits 15:0] Processor Base Frequency (in MHz).\r | |
3200 | ///\r | |
2f88bd3a MK |
3201 | UINT32 ProcessorBaseFrequency : 16;\r |
3202 | UINT32 Reserved : 16;\r | |
236d5c66 RN |
3203 | } Bits;\r |
3204 | ///\r | |
3205 | /// All bit fields as a 32-bit value\r | |
3206 | ///\r | |
2f88bd3a | 3207 | UINT32 Uint32;\r |
236d5c66 RN |
3208 | } CPUID_PROCESSOR_FREQUENCY_EAX;\r |
3209 | \r | |
3210 | /**\r | |
3211 | CPUID Processor Frequency Information EBX for CPUID leaf\r | |
3212 | #CPUID_PROCESSOR_FREQUENCY.\r | |
3213 | **/\r | |
3214 | typedef union {\r | |
3215 | ///\r | |
3216 | /// Individual bit fields\r | |
3217 | ///\r | |
3218 | struct {\r | |
3219 | ///\r | |
3220 | /// [Bits 15:0] Maximum Frequency (in MHz).\r | |
3221 | ///\r | |
2f88bd3a MK |
3222 | UINT32 MaximumFrequency : 16;\r |
3223 | UINT32 Reserved : 16;\r | |
236d5c66 RN |
3224 | } Bits;\r |
3225 | ///\r | |
3226 | /// All bit fields as a 32-bit value\r | |
3227 | ///\r | |
2f88bd3a | 3228 | UINT32 Uint32;\r |
236d5c66 RN |
3229 | } CPUID_PROCESSOR_FREQUENCY_EBX;\r |
3230 | \r | |
3231 | /**\r | |
3232 | CPUID Processor Frequency Information ECX for CPUID leaf\r | |
3233 | #CPUID_PROCESSOR_FREQUENCY.\r | |
3234 | **/\r | |
3235 | typedef union {\r | |
3236 | ///\r | |
3237 | /// Individual bit fields\r | |
3238 | ///\r | |
3239 | struct {\r | |
3240 | ///\r | |
3241 | /// [Bits 15:0] Bus (Reference) Frequency (in MHz).\r | |
3242 | ///\r | |
2f88bd3a MK |
3243 | UINT32 BusFrequency : 16;\r |
3244 | UINT32 Reserved : 16;\r | |
236d5c66 RN |
3245 | } Bits;\r |
3246 | ///\r | |
3247 | /// All bit fields as a 32-bit value\r | |
3248 | ///\r | |
2f88bd3a | 3249 | UINT32 Uint32;\r |
236d5c66 RN |
3250 | } CPUID_PROCESSOR_FREQUENCY_ECX;\r |
3251 | \r | |
236d5c66 RN |
3252 | /**\r |
3253 | CPUID SoC Vendor Information\r | |
3254 | \r | |
3255 | @param EAX CPUID_SOC_VENDOR (0x17)\r | |
3256 | @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)\r | |
3257 | CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)\r | |
3258 | CPUID_SOC_VENDOR_BRAND_STRING1 (0x02)\r | |
3259 | CPUID_SOC_VENDOR_BRAND_STRING1 (0x03)\r | |
3260 | \r | |
3261 | @note\r | |
3262 | Leaf 17H output depends on the initial value in ECX. SOC Vendor Brand String\r | |
3263 | is a UTF-8 encoded string padded with trailing bytes of 00H. The complete SOC\r | |
3264 | Vendor Brand String is constructed by concatenating in ascending order of\r | |
3265 | EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3.\r | |
3266 | \r | |
3267 | **/\r | |
2f88bd3a | 3268 | #define CPUID_SOC_VENDOR 0x17\r |
236d5c66 RN |
3269 | \r |
3270 | /**\r | |
3271 | CPUID SoC Vendor Information\r | |
3272 | \r | |
3273 | @param EAX CPUID_SOC_VENDOR (0x17)\r | |
3274 | @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)\r | |
3275 | \r | |
3276 | @retval EAX MaxSOCID_Index. Reports the maximum input value of supported\r | |
3277 | sub-leaf in leaf 17H.\r | |
3278 | @retval EBX Returns SoC Vendor information described by the type\r | |
3279 | CPUID_SOC_VENDOR_MAIN_LEAF_EBX.\r | |
3280 | @retval ECX Project ID. A unique number an SOC vendor assigns to its SOC\r | |
3281 | projects.\r | |
3282 | @retval EDX Stepping ID. A unique number within an SOC project that an SOC\r | |
3283 | vendor assigns.\r | |
3284 | \r | |
3285 | <b>Example usage</b>\r | |
3286 | @code\r | |
3287 | UINT32 Eax;\r | |
3288 | CPUID_SOC_VENDOR_MAIN_LEAF_EBX Ebx;\r | |
3289 | UINT32 Ecx;\r | |
3290 | UINT32 Edx;\r | |
3291 | \r | |
3292 | AsmCpuidEx (\r | |
3293 | CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF,\r | |
3294 | &Eax, &Ebx.Uint32, &Ecx, &Edx\r | |
3295 | );\r | |
3296 | @endcode\r | |
3297 | **/\r | |
2f88bd3a | 3298 | #define CPUID_SOC_VENDOR_MAIN_LEAF 0x00\r |
236d5c66 RN |
3299 | \r |
3300 | /**\r | |
3301 | CPUID SoC Vendor Information EBX for CPUID leaf #CPUID_SOC_VENDOR sub-leaf\r | |
3302 | #CPUID_SOC_VENDOR_MAIN_LEAF.\r | |
3303 | **/\r | |
3304 | typedef union {\r | |
3305 | ///\r | |
3306 | /// Individual bit fields\r | |
3307 | ///\r | |
3308 | struct {\r | |
3309 | ///\r | |
3310 | /// [Bits 15:0] SOC Vendor ID.\r | |
3311 | ///\r | |
2f88bd3a | 3312 | UINT32 SocVendorId : 16;\r |
236d5c66 RN |
3313 | ///\r |
3314 | /// [Bit 16] If 1, the SOC Vendor ID field is assigned via an industry\r | |
3315 | /// standard enumeration scheme. Otherwise, the SOC Vendor ID field is\r | |
3316 | /// assigned by Intel.\r | |
3317 | ///\r | |
2f88bd3a MK |
3318 | UINT32 IsVendorScheme : 1;\r |
3319 | UINT32 Reserved : 15;\r | |
236d5c66 RN |
3320 | } Bits;\r |
3321 | ///\r | |
3322 | /// All bit fields as a 32-bit value\r | |
3323 | ///\r | |
2f88bd3a | 3324 | UINT32 Uint32;\r |
236d5c66 RN |
3325 | } CPUID_SOC_VENDOR_MAIN_LEAF_EBX;\r |
3326 | \r | |
3327 | /**\r | |
3328 | CPUID SoC Vendor Information\r | |
3329 | \r | |
3330 | @param EAX CPUID_SOC_VENDOR (0x17)\r | |
3331 | @param ECX CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)\r | |
3332 | \r | |
3333 | @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type\r | |
3334 | CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r | |
3335 | @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type\r | |
3336 | CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r | |
3337 | @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type\r | |
3338 | CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r | |
3339 | @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type\r | |
3340 | CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r | |
3341 | \r | |
3342 | <b>Example usage</b>\r | |
3343 | @code\r | |
3344 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;\r | |
3345 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;\r | |
3346 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;\r | |
3347 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;\r | |
3348 | \r | |
3349 | AsmCpuidEx (\r | |
3350 | CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1,\r | |
3351 | &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r | |
3352 | );\r | |
3353 | @endcode\r | |
3354 | **/\r | |
2f88bd3a | 3355 | #define CPUID_SOC_VENDOR_BRAND_STRING1 0x01\r |
236d5c66 RN |
3356 | \r |
3357 | /**\r | |
3358 | CPUID SoC Vendor Brand String for CPUID leafs #CPUID_SOC_VENDOR_BRAND_STRING1,\r | |
3359 | #CPUID_SOC_VENDOR_BRAND_STRING2, and #CPUID_SOC_VENDOR_BRAND_STRING3.\r | |
3360 | **/\r | |
3361 | typedef union {\r | |
3362 | ///\r | |
3363 | /// 4 UTF-8 characters of Soc Vendor Brand String\r | |
3364 | ///\r | |
2f88bd3a | 3365 | CHAR8 BrandString[4];\r |
236d5c66 RN |
3366 | ///\r |
3367 | /// All fields as a 32-bit value\r | |
3368 | ///\r | |
2f88bd3a | 3369 | UINT32 Uint32;\r |
236d5c66 RN |
3370 | } CPUID_SOC_VENDOR_BRAND_STRING_DATA;\r |
3371 | \r | |
3372 | /**\r | |
3373 | CPUID SoC Vendor Information\r | |
3374 | \r | |
3375 | @param EAX CPUID_SOC_VENDOR (0x17)\r | |
3376 | @param ECX CPUID_SOC_VENDOR_BRAND_STRING2 (0x02)\r | |
3377 | \r | |
3378 | @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type\r | |
3379 | CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r | |
3380 | @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type\r | |
3381 | CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r | |
3382 | @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type\r | |
3383 | CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r | |
3384 | @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type\r | |
3385 | CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r | |
3386 | \r | |
3387 | <b>Example usage</b>\r | |
3388 | @code\r | |
3389 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;\r | |
3390 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;\r | |
3391 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;\r | |
3392 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;\r | |
3393 | \r | |
3394 | AsmCpuidEx (\r | |
3395 | CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2,\r | |
3396 | &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r | |
3397 | );\r | |
3398 | @endcode\r | |
3399 | **/\r | |
2f88bd3a | 3400 | #define CPUID_SOC_VENDOR_BRAND_STRING2 0x02\r |
236d5c66 RN |
3401 | \r |
3402 | /**\r | |
3403 | CPUID SoC Vendor Information\r | |
3404 | \r | |
3405 | @param EAX CPUID_SOC_VENDOR (0x17)\r | |
3406 | @param ECX CPUID_SOC_VENDOR_BRAND_STRING3 (0x03)\r | |
3407 | \r | |
3408 | @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type\r | |
3409 | CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r | |
3410 | @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type\r | |
3411 | CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r | |
3412 | @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type\r | |
3413 | CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r | |
3414 | @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type\r | |
3415 | CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r | |
3416 | \r | |
3417 | <b>Example usage</b>\r | |
3418 | @code\r | |
3419 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;\r | |
3420 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;\r | |
3421 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;\r | |
3422 | CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;\r | |
3423 | \r | |
3424 | AsmCpuidEx (\r | |
3425 | CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3,\r | |
3426 | &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r | |
3427 | );\r | |
3428 | @endcode\r | |
3429 | **/\r | |
2f88bd3a | 3430 | #define CPUID_SOC_VENDOR_BRAND_STRING3 0x03\r |
236d5c66 RN |
3431 | \r |
3432 | /**\r | |
3433 | CPUID Deterministic Address Translation Parameters\r | |
3434 | \r | |
3435 | @note\r | |
3436 | Each sub-leaf enumerates a different address translation structure.\r | |
3437 | If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf\r | |
3438 | index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX. A\r | |
3439 | sub-leaf index is also invalid if EDX[4:0] returns 0.\r | |
3440 | Valid sub-leaves do not need to be contiguous or in any particular order. A\r | |
3441 | valid sub-leaf may be in a higher input ECX value than an invalid sub-leaf or\r | |
3442 | than a valid sub-leaf of a higher or lower-level structure.\r | |
3443 | * Some unified TLBs will allow a single TLB entry to satisfy data read/write\r | |
3444 | and instruction fetches. Others will require separate entries (e.g., one\r | |
3445 | loaded on data read/write and another loaded on an instruction fetch).\r | |
3446 | Please see the Intel 64 and IA-32 Architectures Optimization Reference Manual\r | |
3447 | for details of a particular product.\r | |
3448 | ** Add one to the return value to get the result.\r | |
3449 | \r | |
3450 | @param EAX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (0x18)\r | |
3451 | @param ECX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF (0x00)\r | |
3452 | CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_SUB_LEAF (0x*)\r | |
3453 | \r | |
3454 | **/\r | |
2f88bd3a | 3455 | #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS 0x18\r |
236d5c66 RN |
3456 | \r |
3457 | /**\r | |
3458 | CPUID Deterministic Address Translation Parameters\r | |
3459 | \r | |
3460 | @param EAX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS (0x18)\r | |
3461 | @param ECX CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF (0x00)\r | |
3462 | \r | |
3463 | @retval EAX Reports the maximum input value of supported sub-leaf in leaf 18H.\r | |
3464 | @retval EBX Returns Deterministic Address Translation Parameters described by\r | |
3465 | the type CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX.\r | |
3466 | @retval ECX Number of Sets.\r | |
3467 | @retval EDX Returns Deterministic Address Translation Parameters described by\r | |
3468 | the type CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX.\r | |
3469 | \r | |
3470 | <b>Example usage</b>\r | |
3471 | @code\r | |
3472 | UINT32 Eax;\r | |
3473 | CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX Ebx;\r | |
3474 | UINT32 Ecx;\r | |
3475 | CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX Edx;\r | |
3476 | \r | |
3477 | AsmCpuidEx (\r | |
3478 | CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS,\r | |
3479 | CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF,\r | |
3480 | &Eax, &Ebx.Uint32, &Ecx, &Edx.Uint32\r | |
3481 | );\r | |
3482 | @endcode\r | |
3483 | **/\r | |
2f88bd3a | 3484 | #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_MAIN_LEAF 0x00\r |
236d5c66 RN |
3485 | \r |
3486 | /**\r | |
3487 | CPUID Deterministic Address Translation Parameters EBX for CPUID leafs.\r | |
3488 | **/\r | |
3489 | typedef union {\r | |
3490 | ///\r | |
3491 | /// Individual bit fields\r | |
3492 | ///\r | |
3493 | struct {\r | |
3494 | ///\r | |
3495 | /// [Bits 0] 4K page size entries supported by this structure.\r | |
3496 | ///\r | |
2f88bd3a | 3497 | UINT32 Page4K : 1;\r |
236d5c66 RN |
3498 | ///\r |
3499 | /// [Bits 1] 2MB page size entries supported by this structure.\r | |
3500 | ///\r | |
2f88bd3a | 3501 | UINT32 Page2M : 1;\r |
236d5c66 RN |
3502 | ///\r |
3503 | /// [Bits 2] 4MB page size entries supported by this structure.\r | |
3504 | ///\r | |
2f88bd3a | 3505 | UINT32 Page4M : 1;\r |
236d5c66 RN |
3506 | ///\r |
3507 | /// [Bits 3] 1 GB page size entries supported by this structure.\r | |
3508 | ///\r | |
2f88bd3a | 3509 | UINT32 Page1G : 1;\r |
236d5c66 RN |
3510 | ///\r |
3511 | /// [Bits 7:4] Reserved.\r | |
3512 | ///\r | |
2f88bd3a | 3513 | UINT32 Reserved1 : 4;\r |
236d5c66 RN |
3514 | ///\r |
3515 | /// [Bits 10:8] Partitioning (0: Soft partitioning between the logical\r | |
3516 | /// processors sharing this structure)\r | |
3517 | ///\r | |
2f88bd3a | 3518 | UINT32 Partitioning : 3;\r |
236d5c66 RN |
3519 | ///\r |
3520 | /// [Bits 15:11] Reserved.\r | |
3521 | ///\r | |
2f88bd3a | 3522 | UINT32 Reserved2 : 5;\r |
236d5c66 RN |
3523 | ///\r |
3524 | /// [Bits 31:16] W = Ways of associativity.\r | |
3525 | ///\r | |
2f88bd3a | 3526 | UINT32 Way : 16;\r |
236d5c66 RN |
3527 | } Bits;\r |
3528 | ///\r | |
3529 | /// All bit fields as a 32-bit value\r | |
3530 | ///\r | |
2f88bd3a | 3531 | UINT32 Uint32;\r |
236d5c66 RN |
3532 | } CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EBX;\r |
3533 | \r | |
3534 | /**\r | |
3535 | CPUID Deterministic Address Translation Parameters EDX for CPUID leafs.\r | |
3536 | **/\r | |
3537 | typedef union {\r | |
3538 | ///\r | |
3539 | /// Individual bit fields\r | |
3540 | ///\r | |
3541 | struct {\r | |
3542 | ///\r | |
3543 | /// [Bits 4:0] Translation cache type field.\r | |
3544 | ///\r | |
2f88bd3a | 3545 | UINT32 TranslationCacheType : 5;\r |
236d5c66 RN |
3546 | ///\r |
3547 | /// [Bits 7:5] Translation cache level (starts at 1).\r | |
3548 | ///\r | |
2f88bd3a | 3549 | UINT32 TranslationCacheLevel : 3;\r |
236d5c66 RN |
3550 | ///\r |
3551 | /// [Bits 8] Fully associative structure.\r | |
3552 | ///\r | |
2f88bd3a | 3553 | UINT32 FullyAssociative : 1;\r |
236d5c66 RN |
3554 | ///\r |
3555 | /// [Bits 13:9] Reserved.\r | |
3556 | ///\r | |
2f88bd3a | 3557 | UINT32 Reserved1 : 5;\r |
236d5c66 RN |
3558 | ///\r |
3559 | /// [Bits 25:14] Maximum number of addressable IDs for logical\r | |
3560 | /// processors sharing this translation cache.\r | |
3561 | ///\r | |
2f88bd3a | 3562 | UINT32 MaximumNum : 12;\r |
236d5c66 RN |
3563 | ///\r |
3564 | /// [Bits 31:26] Reserved.\r | |
3565 | ///\r | |
2f88bd3a | 3566 | UINT32 Reserved2 : 6;\r |
236d5c66 RN |
3567 | } Bits;\r |
3568 | ///\r | |
3569 | /// All bit fields as a 32-bit value\r | |
3570 | ///\r | |
2f88bd3a | 3571 | UINT32 Uint32;\r |
236d5c66 RN |
3572 | } CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX;\r |
3573 | \r | |
3574 | ///\r | |
3575 | /// @{ Define value for CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_EDX.TranslationCacheType\r | |
3576 | ///\r | |
3577 | #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INVALID 0x00\r | |
3578 | #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_DATA_TLB 0x01\r | |
3579 | #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_INSTRUCTION_TLB 0x02\r | |
3580 | #define CPUID_DETERMINISTIC_ADDRESS_TRANSLATION_PARAMETERS_TRANSLATION_CACHE_TYPE_UNIFIED_TLB 0x03\r | |
3581 | ///\r | |
3582 | /// @}\r | |
3583 | ///\r | |
3584 | \r | |
79f3404a JL |
3585 | /**\r |
3586 | CPUID Hybrid Information Enumeration Leaf\r | |
3587 | \r | |
3588 | @param EAX CPUID_HYBRID_INFORMATION (0x1A)\r | |
2d6fc9d3 | 3589 | @param ECX CPUID_HYBRID_INFORMATION_MAIN_LEAF (0x00).\r |
79f3404a JL |
3590 | \r |
3591 | @retval EAX Enumerates the native model ID and core type described\r | |
3592 | by the type CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX\r | |
3593 | @retval EBX Reserved.\r | |
3594 | @retval ECX Reserved.\r | |
3595 | @retval EDX Reserved.\r | |
3596 | \r | |
3597 | <b>Example usage</b>\r | |
3598 | @code\r | |
3599 | CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX Eax;\r | |
3600 | \r | |
3601 | AsmCpuidEx (\r | |
3602 | CPUID_HYBRID_INFORMATION,\r | |
2d6fc9d3 | 3603 | CPUID_HYBRID_INFORMATION_MAIN_LEAF,\r |
79f3404a JL |
3604 | &Eax, NULL, NULL, NULL\r |
3605 | );\r | |
3606 | @endcode\r | |
3607 | \r | |
3608 | **/\r | |
2f88bd3a | 3609 | #define CPUID_HYBRID_INFORMATION 0x1A\r |
79f3404a JL |
3610 | \r |
3611 | ///\r | |
2d6fc9d3 | 3612 | /// CPUID Hybrid Information Enumeration main leaf\r |
79f3404a | 3613 | ///\r |
2f88bd3a | 3614 | #define CPUID_HYBRID_INFORMATION_MAIN_LEAF 0x00\r |
79f3404a JL |
3615 | \r |
3616 | /**\r | |
3617 | CPUID Hybrid Information EAX for CPUID leaf #CPUID_HYBRID_INFORMATION,\r | |
2d6fc9d3 | 3618 | main leaf #CPUID_HYBRID_INFORMATION_MAIN_LEAF.\r |
79f3404a JL |
3619 | **/\r |
3620 | typedef union {\r | |
3621 | ///\r | |
3622 | /// Individual bit fields\r | |
3623 | ///\r | |
3624 | struct {\r | |
3625 | ///\r | |
3626 | /// [Bit 23:0] Native model ID of the core.\r | |
3627 | ///\r | |
3628 | /// The core-type and native mode ID can be used to uniquely identify\r | |
3629 | /// the microarchitecture of the core.This native model ID is not unique\r | |
3630 | /// across core types, and not related to the model ID reported in CPUID\r | |
3631 | /// leaf 01H, and does not identify the SOC.\r | |
3632 | ///\r | |
2f88bd3a | 3633 | UINT32 NativeModelId : 24;\r |
79f3404a JL |
3634 | ///\r |
3635 | /// [Bit 31:24] Core type\r | |
3636 | ///\r | |
2f88bd3a | 3637 | UINT32 CoreType : 8;\r |
79f3404a JL |
3638 | } Bits;\r |
3639 | ///\r | |
3640 | /// All bit fields as a 32-bit value\r | |
3641 | ///\r | |
2f88bd3a | 3642 | UINT32 Uint32;\r |
79f3404a JL |
3643 | } CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX;\r |
3644 | \r | |
2d6fc9d3 LY |
3645 | ///\r |
3646 | /// @{ Define value for CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX.CoreType\r | |
3647 | ///\r | |
2f88bd3a MK |
3648 | #define CPUID_CORE_TYPE_INTEL_ATOM 0x20\r |
3649 | #define CPUID_CORE_TYPE_INTEL_CORE 0x40\r | |
2d6fc9d3 LY |
3650 | ///\r |
3651 | /// @}\r | |
3652 | ///\r | |
3653 | \r | |
236d5c66 RN |
3654 | /**\r |
3655 | CPUID V2 Extended Topology Enumeration Leaf\r | |
3656 | \r | |
3657 | @note\r | |
3658 | CPUID leaf 1FH is a preferred superset to leaf 0BH. Intel recommends first checking\r | |
3659 | for the existence of Leaf 1FH and using this if available.\r | |
3660 | Most of Leaf 1FH output depends on the initial value in ECX. The EDX output of leaf\r | |
3661 | 1FH is always valid and does not vary with input value in ECX. Output value in ECX[7:0]\r | |
3662 | always equals input value in ECX[7:0]. Sub-leaf index 0 enumerates SMT level. Each\r | |
3663 | subsequent higher sub-leaf index enumerates a higher-level topological entity in\r | |
3664 | hierarchical order. For sub-leaves that return an invalid level-type of 0 in ECX[15:8];\r | |
3665 | EAX and EBX will return 0. If an input value n in ECX returns the invalid level-type of\r | |
3666 | 0 in ECX[15:8], other input values with ECX > n also return 0 in ECX[15:8].\r | |
3667 | \r | |
3668 | Software should use this field (EAX[4:0]) to enumerate processor topology of the system.\r | |
3669 | Software must not use EBX[15:0] to enumerate processor topology of the system. This value\r | |
3670 | in this field (EBX[15:0]) is only intended for display/diagnostic purposes. The actual\r | |
3671 | number of logical processors available to BIOS/OS/Applications may be different from the\r | |
3672 | value of EBX[15:0], depending on software and platform hardware configurations.\r | |
3673 | \r | |
3674 | @param EAX CPUID_V2_EXTENDED_TOPOLOGY (0x1F)\r | |
3675 | @param ECX Level number\r | |
3676 | \r | |
3677 | **/\r | |
2f88bd3a | 3678 | #define CPUID_V2_EXTENDED_TOPOLOGY 0x1F\r |
236d5c66 RN |
3679 | \r |
3680 | ///\r | |
3681 | /// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType\r | |
3682 | /// The value of the "level type" field is not related to level numbers in\r | |
3683 | /// any way, higher "level type" values do not mean higher levels.\r | |
3684 | ///\r | |
2f88bd3a MK |
3685 | #define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_MODULE 0x03\r |
3686 | #define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_TILE 0x04\r | |
3687 | #define CPUID_V2_EXTENDED_TOPOLOGY_LEVEL_TYPE_DIE 0x05\r | |
236d5c66 RN |
3688 | ///\r |
3689 | /// @}\r | |
3690 | ///\r | |
3691 | \r | |
3692 | /**\r | |
3693 | CPUID Extended Function\r | |
3694 | \r | |
3695 | @param EAX CPUID_EXTENDED_FUNCTION (0x80000000)\r | |
3696 | \r | |
3697 | @retval EAX Maximum Input Value for Extended Function CPUID Information.\r | |
3698 | @retval EBX Reserved.\r | |
3699 | @retval ECX Reserved.\r | |
3700 | @retval EDX Reserved.\r | |
3701 | \r | |
3702 | <b>Example usage</b>\r | |
3703 | @code\r | |
3704 | UINT32 Eax;\r | |
3705 | \r | |
3706 | AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);\r | |
3707 | @endcode\r | |
3708 | **/\r | |
2f88bd3a | 3709 | #define CPUID_EXTENDED_FUNCTION 0x80000000\r |
236d5c66 RN |
3710 | \r |
3711 | /**\r | |
3712 | CPUID Extended Processor Signature and Feature Bits\r | |
3713 | \r | |
3714 | @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001)\r | |
3715 | \r | |
3716 | @retval EAX CPUID_EXTENDED_CPU_SIG.\r | |
3717 | @retval EBX Reserved.\r | |
3718 | @retval ECX Extended Processor Signature and Feature Bits information\r | |
3719 | described by the type CPUID_EXTENDED_CPU_SIG_ECX.\r | |
3720 | @retval EDX Extended Processor Signature and Feature Bits information\r | |
3721 | described by the type CPUID_EXTENDED_CPU_SIG_EDX.\r | |
3722 | \r | |
3723 | <b>Example usage</b>\r | |
3724 | @code\r | |
3725 | UINT32 Eax;\r | |
3726 | CPUID_EXTENDED_CPU_SIG_ECX Ecx;\r | |
3727 | CPUID_EXTENDED_CPU_SIG_EDX Edx;\r | |
3728 | \r | |
3729 | AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32);\r | |
3730 | @endcode\r | |
3731 | **/\r | |
2f88bd3a | 3732 | #define CPUID_EXTENDED_CPU_SIG 0x80000001\r |
236d5c66 RN |
3733 | \r |
3734 | /**\r | |
3735 | CPUID Extended Processor Signature and Feature Bits ECX for CPUID leaf\r | |
3736 | #CPUID_EXTENDED_CPU_SIG.\r | |
3737 | **/\r | |
3738 | typedef union {\r | |
3739 | ///\r | |
3740 | /// Individual bit fields\r | |
3741 | ///\r | |
3742 | struct {\r | |
3743 | ///\r | |
3744 | /// [Bit 0] LAHF/SAHF available in 64-bit mode.\r | |
3745 | ///\r | |
2f88bd3a MK |
3746 | UINT32 LAHF_SAHF : 1;\r |
3747 | UINT32 Reserved1 : 4;\r | |
236d5c66 RN |
3748 | ///\r |
3749 | /// [Bit 5] LZCNT.\r | |
3750 | ///\r | |
2f88bd3a MK |
3751 | UINT32 LZCNT : 1;\r |
3752 | UINT32 Reserved2 : 2;\r | |
236d5c66 RN |
3753 | ///\r |
3754 | /// [Bit 8] PREFETCHW.\r | |
3755 | ///\r | |
2f88bd3a MK |
3756 | UINT32 PREFETCHW : 1;\r |
3757 | UINT32 Reserved3 : 23;\r | |
236d5c66 RN |
3758 | } Bits;\r |
3759 | ///\r | |
3760 | /// All bit fields as a 32-bit value\r | |
3761 | ///\r | |
2f88bd3a | 3762 | UINT32 Uint32;\r |
236d5c66 RN |
3763 | } CPUID_EXTENDED_CPU_SIG_ECX;\r |
3764 | \r | |
3765 | /**\r | |
3766 | CPUID Extended Processor Signature and Feature Bits EDX for CPUID leaf\r | |
3767 | #CPUID_EXTENDED_CPU_SIG.\r | |
3768 | **/\r | |
3769 | typedef union {\r | |
3770 | ///\r | |
3771 | /// Individual bit fields\r | |
3772 | ///\r | |
3773 | struct {\r | |
2f88bd3a | 3774 | UINT32 Reserved1 : 11;\r |
236d5c66 RN |
3775 | ///\r |
3776 | /// [Bit 11] SYSCALL/SYSRET available in 64-bit mode.\r | |
3777 | ///\r | |
2f88bd3a MK |
3778 | UINT32 SYSCALL_SYSRET : 1;\r |
3779 | UINT32 Reserved2 : 8;\r | |
236d5c66 RN |
3780 | ///\r |
3781 | /// [Bit 20] Execute Disable Bit available.\r | |
3782 | ///\r | |
2f88bd3a MK |
3783 | UINT32 NX : 1;\r |
3784 | UINT32 Reserved3 : 5;\r | |
236d5c66 RN |
3785 | ///\r |
3786 | /// [Bit 26] 1-GByte pages are available if 1.\r | |
3787 | ///\r | |
2f88bd3a | 3788 | UINT32 Page1GB : 1;\r |
236d5c66 RN |
3789 | ///\r |
3790 | /// [Bit 27] RDTSCP and IA32_TSC_AUX are available if 1.\r | |
3791 | ///\r | |
2f88bd3a MK |
3792 | UINT32 RDTSCP : 1;\r |
3793 | UINT32 Reserved4 : 1;\r | |
236d5c66 RN |
3794 | ///\r |
3795 | /// [Bit 29] Intel(R) 64 Architecture available if 1.\r | |
3796 | ///\r | |
2f88bd3a MK |
3797 | UINT32 LM : 1;\r |
3798 | UINT32 Reserved5 : 2;\r | |
236d5c66 RN |
3799 | } Bits;\r |
3800 | ///\r | |
3801 | /// All bit fields as a 32-bit value\r | |
3802 | ///\r | |
2f88bd3a | 3803 | UINT32 Uint32;\r |
236d5c66 RN |
3804 | } CPUID_EXTENDED_CPU_SIG_EDX;\r |
3805 | \r | |
236d5c66 RN |
3806 | /**\r |
3807 | CPUID Processor Brand String\r | |
3808 | \r | |
3809 | @param EAX CPUID_BRAND_STRING1 (0x80000002)\r | |
3810 | \r | |
3811 | @retval EAX Processor Brand String in type CPUID_BRAND_STRING_DATA.\r | |
3812 | @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r | |
3813 | @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r | |
3814 | @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r | |
3815 | \r | |
3816 | <b>Example usage</b>\r | |
3817 | @code\r | |
3818 | CPUID_BRAND_STRING_DATA Eax;\r | |
3819 | CPUID_BRAND_STRING_DATA Ebx;\r | |
3820 | CPUID_BRAND_STRING_DATA Ecx;\r | |
3821 | CPUID_BRAND_STRING_DATA Edx;\r | |
3822 | \r | |
3823 | AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r | |
3824 | @endcode\r | |
3825 | **/\r | |
2f88bd3a | 3826 | #define CPUID_BRAND_STRING1 0x80000002\r |
236d5c66 RN |
3827 | \r |
3828 | /**\r | |
3829 | CPUID Processor Brand String for CPUID leafs #CPUID_BRAND_STRING1,\r | |
3830 | #CPUID_BRAND_STRING2, and #CPUID_BRAND_STRING3.\r | |
3831 | **/\r | |
3832 | typedef union {\r | |
3833 | ///\r | |
3834 | /// 4 ASCII characters of Processor Brand String\r | |
3835 | ///\r | |
2f88bd3a | 3836 | CHAR8 BrandString[4];\r |
236d5c66 RN |
3837 | ///\r |
3838 | /// All fields as a 32-bit value\r | |
3839 | ///\r | |
2f88bd3a | 3840 | UINT32 Uint32;\r |
236d5c66 RN |
3841 | } CPUID_BRAND_STRING_DATA;\r |
3842 | \r | |
3843 | /**\r | |
3844 | CPUID Processor Brand String\r | |
3845 | \r | |
3846 | @param EAX CPUID_BRAND_STRING2 (0x80000003)\r | |
3847 | \r | |
3848 | @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r | |
3849 | @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r | |
3850 | @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r | |
3851 | @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r | |
3852 | \r | |
3853 | <b>Example usage</b>\r | |
3854 | @code\r | |
3855 | CPUID_BRAND_STRING_DATA Eax;\r | |
3856 | CPUID_BRAND_STRING_DATA Ebx;\r | |
3857 | CPUID_BRAND_STRING_DATA Ecx;\r | |
3858 | CPUID_BRAND_STRING_DATA Edx;\r | |
3859 | \r | |
3860 | AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r | |
3861 | @endcode\r | |
3862 | **/\r | |
2f88bd3a | 3863 | #define CPUID_BRAND_STRING2 0x80000003\r |
236d5c66 RN |
3864 | \r |
3865 | /**\r | |
3866 | CPUID Processor Brand String\r | |
3867 | \r | |
3868 | @param EAX CPUID_BRAND_STRING3 (0x80000004)\r | |
3869 | \r | |
3870 | @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r | |
3871 | @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r | |
3872 | @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r | |
3873 | @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r | |
3874 | \r | |
3875 | <b>Example usage</b>\r | |
3876 | @code\r | |
3877 | CPUID_BRAND_STRING_DATA Eax;\r | |
3878 | CPUID_BRAND_STRING_DATA Ebx;\r | |
3879 | CPUID_BRAND_STRING_DATA Ecx;\r | |
3880 | CPUID_BRAND_STRING_DATA Edx;\r | |
3881 | \r | |
3882 | AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r | |
3883 | @endcode\r | |
3884 | **/\r | |
2f88bd3a | 3885 | #define CPUID_BRAND_STRING3 0x80000004\r |
236d5c66 RN |
3886 | \r |
3887 | /**\r | |
3888 | CPUID Extended Cache information\r | |
3889 | \r | |
3890 | @param EAX CPUID_EXTENDED_CACHE_INFO (0x80000006)\r | |
3891 | \r | |
3892 | @retval EAX Reserved.\r | |
3893 | @retval EBX Reserved.\r | |
3894 | @retval ECX Extended cache information described by the type\r | |
3895 | CPUID_EXTENDED_CACHE_INFO_ECX.\r | |
3896 | @retval EDX Reserved.\r | |
3897 | \r | |
3898 | <b>Example usage</b>\r | |
3899 | @code\r | |
3900 | CPUID_EXTENDED_CACHE_INFO_ECX Ecx;\r | |
3901 | \r | |
3902 | AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL);\r | |
3903 | @endcode\r | |
3904 | **/\r | |
2f88bd3a | 3905 | #define CPUID_EXTENDED_CACHE_INFO 0x80000006\r |
236d5c66 RN |
3906 | \r |
3907 | /**\r | |
3908 | CPUID Extended Cache information ECX for CPUID leaf #CPUID_EXTENDED_CACHE_INFO.\r | |
3909 | **/\r | |
3910 | typedef union {\r | |
3911 | ///\r | |
3912 | /// Individual bit fields\r | |
3913 | ///\r | |
3914 | struct {\r | |
3915 | ///\r | |
3916 | /// [Bits 7:0] Cache line size in bytes.\r | |
3917 | ///\r | |
2f88bd3a MK |
3918 | UINT32 CacheLineSize : 8;\r |
3919 | UINT32 Reserved : 4;\r | |
236d5c66 RN |
3920 | ///\r |
3921 | /// [Bits 15:12] L2 Associativity field. Supported values are in the range\r | |
3922 | /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED to\r | |
3923 | /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL\r | |
3924 | ///\r | |
2f88bd3a | 3925 | UINT32 L2Associativity : 4;\r |
236d5c66 RN |
3926 | ///\r |
3927 | /// [Bits 31:16] Cache size in 1K units.\r | |
3928 | ///\r | |
2f88bd3a | 3929 | UINT32 CacheSize : 16;\r |
236d5c66 RN |
3930 | } Bits;\r |
3931 | ///\r | |
3932 | /// All bit fields as a 32-bit value\r | |
3933 | ///\r | |
2f88bd3a | 3934 | UINT32 Uint32;\r |
236d5c66 RN |
3935 | } CPUID_EXTENDED_CACHE_INFO_ECX;\r |
3936 | \r | |
3937 | ///\r | |
3938 | /// @{ Define value for bit field CPUID_EXTENDED_CACHE_INFO_ECX.L2Associativity\r | |
3939 | ///\r | |
3940 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED 0x00\r | |
3941 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DIRECT_MAPPED 0x01\r | |
3942 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_2_WAY 0x02\r | |
3943 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_4_WAY 0x04\r | |
3944 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_8_WAY 0x06\r | |
3945 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_16_WAY 0x08\r | |
3946 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_32_WAY 0x0A\r | |
3947 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_48_WAY 0x0B\r | |
3948 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_64_WAY 0x0C\r | |
3949 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_96_WAY 0x0D\r | |
3950 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_128_WAY 0x0E\r | |
3951 | #define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL 0x0F\r | |
3952 | ///\r | |
3953 | /// @}\r | |
3954 | ///\r | |
3955 | \r | |
3956 | /**\r | |
3957 | CPUID Extended Time Stamp Counter information\r | |
3958 | \r | |
3959 | @param EAX CPUID_EXTENDED_TIME_STAMP_COUNTER (0x80000007)\r | |
3960 | \r | |
3961 | @retval EAX Reserved.\r | |
3962 | @retval EBX Reserved.\r | |
3963 | @retval ECX Reserved.\r | |
3964 | @retval EDX Extended time stamp counter (TSC) information described by the\r | |
3965 | type CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX.\r | |
3966 | \r | |
3967 | <b>Example usage</b>\r | |
3968 | @code\r | |
3969 | CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX Edx;\r | |
3970 | \r | |
3971 | AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32);\r | |
3972 | @endcode\r | |
3973 | **/\r | |
2f88bd3a | 3974 | #define CPUID_EXTENDED_TIME_STAMP_COUNTER 0x80000007\r |
236d5c66 RN |
3975 | \r |
3976 | /**\r | |
3977 | CPUID Extended Time Stamp Counter information EDX for CPUID leaf\r | |
3978 | #CPUID_EXTENDED_TIME_STAMP_COUNTER.\r | |
3979 | **/\r | |
3980 | typedef union {\r | |
3981 | ///\r | |
3982 | /// Individual bit fields\r | |
3983 | ///\r | |
3984 | struct {\r | |
2f88bd3a | 3985 | UINT32 Reserved1 : 8;\r |
236d5c66 RN |
3986 | ///\r |
3987 | /// [Bit 8] Invariant TSC available if 1.\r | |
3988 | ///\r | |
2f88bd3a MK |
3989 | UINT32 InvariantTsc : 1;\r |
3990 | UINT32 Reserved2 : 23;\r | |
236d5c66 RN |
3991 | } Bits;\r |
3992 | ///\r | |
3993 | /// All bit fields as a 32-bit value\r | |
3994 | ///\r | |
2f88bd3a | 3995 | UINT32 Uint32;\r |
236d5c66 RN |
3996 | } CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX;\r |
3997 | \r | |
236d5c66 RN |
3998 | /**\r |
3999 | CPUID Linear Physical Address Size\r | |
4000 | \r | |
4001 | @param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)\r | |
4002 | \r | |
4003 | @retval EAX Linear/Physical Address Size described by the type\r | |
4004 | CPUID_VIR_PHY_ADDRESS_SIZE_EAX.\r | |
4005 | @retval EBX Reserved.\r | |
4006 | @retval ECX Reserved.\r | |
4007 | @retval EDX Reserved.\r | |
4008 | \r | |
4009 | <b>Example usage</b>\r | |
4010 | @code\r | |
4011 | CPUID_VIR_PHY_ADDRESS_SIZE_EAX Eax;\r | |
4012 | \r | |
4013 | AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL);\r | |
4014 | @endcode\r | |
4015 | **/\r | |
2f88bd3a | 4016 | #define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008\r |
236d5c66 RN |
4017 | \r |
4018 | /**\r | |
4019 | CPUID Linear Physical Address Size EAX for CPUID leaf\r | |
4020 | #CPUID_VIR_PHY_ADDRESS_SIZE.\r | |
4021 | **/\r | |
4022 | typedef union {\r | |
4023 | ///\r | |
4024 | /// Individual bit fields\r | |
4025 | ///\r | |
4026 | struct {\r | |
4027 | ///\r | |
4028 | /// [Bits 7:0] Number of physical address bits.\r | |
4029 | ///\r | |
4030 | /// @note\r | |
4031 | /// If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address\r | |
4032 | /// number supported should come from this field.\r | |
4033 | ///\r | |
2f88bd3a | 4034 | UINT32 PhysicalAddressBits : 8;\r |
236d5c66 RN |
4035 | ///\r |
4036 | /// [Bits 15:8] Number of linear address bits.\r | |
4037 | ///\r | |
2f88bd3a MK |
4038 | UINT32 LinearAddressBits : 8;\r |
4039 | UINT32 Reserved : 16;\r | |
236d5c66 RN |
4040 | } Bits;\r |
4041 | ///\r | |
4042 | /// All bit fields as a 32-bit value\r | |
4043 | ///\r | |
2f88bd3a | 4044 | UINT32 Uint32;\r |
236d5c66 RN |
4045 | } CPUID_VIR_PHY_ADDRESS_SIZE_EAX;\r |
4046 | \r | |
4047 | #endif\r |