[mirror_edk2.git] / MdePkg / Include / Register / Intel / LocalApic.h

/** @file\r
  IA32 Local APIC Definitions.\r
\r
  Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef __INTEL_LOCAL_APIC_H__\r
#define __INTEL_LOCAL_APIC_H__\r
\r
//\r
// Definition for Local APIC registers and related values\r
//\r
#define XAPIC_ID_OFFSET                          0x20\r
#define XAPIC_VERSION_OFFSET                     0x30\r
#define XAPIC_EOI_OFFSET                         0x0b0\r
#define XAPIC_ICR_DFR_OFFSET                     0x0e0\r
#define XAPIC_SPURIOUS_VECTOR_OFFSET             0x0f0\r
#define XAPIC_ICR_LOW_OFFSET                     0x300\r
#define XAPIC_ICR_HIGH_OFFSET                    0x310\r
#define XAPIC_LVT_TIMER_OFFSET                   0x320\r
#define XAPIC_LVT_LINT0_OFFSET                   0x350\r
#define XAPIC_LVT_LINT1_OFFSET                   0x360\r
#define XAPIC_TIMER_INIT_COUNT_OFFSET            0x380\r
#define XAPIC_TIMER_CURRENT_COUNT_OFFSET         0x390\r
#define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET  0x3E0\r
\r
#define X2APIC_MSR_BASE_ADDRESS  0x800\r
#define X2APIC_MSR_ICR_ADDRESS   0x830\r
\r
#define LOCAL_APIC_DELIVERY_MODE_FIXED            0\r
#define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY  1\r
#define LOCAL_APIC_DELIVERY_MODE_SMI              2\r
#define LOCAL_APIC_DELIVERY_MODE_NMI              4\r
#define LOCAL_APIC_DELIVERY_MODE_INIT             5\r
#define LOCAL_APIC_DELIVERY_MODE_STARTUP          6\r
#define LOCAL_APIC_DELIVERY_MODE_EXTINT           7\r
\r
#define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND        0\r
#define LOCAL_APIC_DESTINATION_SHORTHAND_SELF                1\r
#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF  2\r
#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF  3\r
\r
//\r
// Local APIC Version Register.\r
//\r
typedef union {\r
  struct {\r
    UINT32    Version                 : 8; ///< The version numbers of the local APIC.\r
    UINT32    Reserved0               : 8; ///< Reserved.\r
    UINT32    MaxLvtEntry             : 8; ///< Number of LVT entries minus 1.\r
    UINT32    EoiBroadcastSuppression : 1; ///< 1 if EOI-broadcast suppression supported.\r
    UINT32    Reserved1               : 7; ///< Reserved.\r
  } Bits;\r
  UINT32    Uint32;\r
} LOCAL_APIC_VERSION;\r
\r
//\r
// Low half of Interrupt Command Register (ICR).\r
//\r
typedef union {\r
  struct {\r
    UINT32    Vector               : 8;  ///< The vector number of the interrupt being sent.\r
    UINT32    DeliveryMode         : 3;  ///< Specifies the type of IPI to be sent.\r
    UINT32    DestinationMode      : 1;  ///< 0: physical destination mode, 1: logical destination mode.\r
    UINT32    DeliveryStatus       : 1;  ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode.\r
    UINT32    Reserved0            : 1;  ///< Reserved.\r
    UINT32    Level                : 1;  ///< 0 for the INIT level de-assert delivery mode. Otherwise 1.\r
    UINT32    TriggerMode          : 1;  ///< 0: edge, 1: level when using the INIT level de-assert delivery mode.\r
    UINT32    Reserved1            : 2;  ///< Reserved.\r
    UINT32    DestinationShorthand : 2;  ///< A shorthand notation to specify the destination of the interrupt.\r
    UINT32    Reserved2            : 12; ///< Reserved.\r
  } Bits;\r
  UINT32    Uint32;\r
} LOCAL_APIC_ICR_LOW;\r
\r
//\r
// High half of Interrupt Command Register (ICR)\r
//\r
typedef union {\r
  struct {\r
    UINT32    Reserved0   : 24; ///< Reserved.\r
    UINT32    Destination : 8;  ///< Specifies the target processor or processors in xAPIC mode.\r
  } Bits;\r
  UINT32    Uint32;         ///< Destination field expanded to 32-bit in x2APIC mode.\r
} LOCAL_APIC_ICR_HIGH;\r
\r
//\r
// Spurious-Interrupt Vector Register (SVR)\r
//\r
typedef union {\r
  struct {\r
    UINT32    SpuriousVector          : 8;  ///< Spurious Vector.\r
    UINT32    SoftwareEnable          : 1;  ///< APIC Software Enable/Disable.\r
    UINT32    FocusProcessorChecking  : 1;  ///< Focus Processor Checking.\r
    UINT32    Reserved0               : 2;  ///< Reserved.\r
    UINT32    EoiBroadcastSuppression : 1;  ///< EOI-Broadcast Suppression.\r
    UINT32    Reserved1               : 19; ///< Reserved.\r
  } Bits;\r
  UINT32    Uint32;\r
} LOCAL_APIC_SVR;\r
\r
//\r
// Divide Configuration Register (DCR)\r
//\r
typedef union {\r
  struct {\r
    UINT32    DivideValue1 : 2;  ///< Low 2 bits of the divide value.\r
    UINT32    Reserved0    : 1;  ///< Always 0.\r
    UINT32    DivideValue2 : 1;  ///< Highest 1 bit of the divide value.\r
    UINT32    Reserved1    : 28; ///< Reserved.\r
  } Bits;\r
  UINT32    Uint32;\r
} LOCAL_APIC_DCR;\r
\r
//\r
// LVT Timer Register\r
//\r
typedef union {\r
  struct {\r
    UINT32    Vector         : 8;  ///< The vector number of the interrupt being sent.\r
    UINT32    Reserved0      : 4;  ///< Reserved.\r
    UINT32    DeliveryStatus : 1;  ///< 0: Idle, 1: send pending.\r
    UINT32    Reserved1      : 3;  ///< Reserved.\r
    UINT32    Mask           : 1;  ///< 0: Not masked, 1: Masked.\r
    UINT32    TimerMode      : 1;  ///< 0: One-shot, 1: Periodic.\r
    UINT32    Reserved2      : 14; ///< Reserved.\r
  } Bits;\r
  UINT32    Uint32;\r
} LOCAL_APIC_LVT_TIMER;\r
\r
//\r
// LVT LINT0/LINT1 Register\r
//\r
typedef union {\r
  struct {\r
    UINT32    Vector           : 8;  ///< The vector number of the interrupt being sent.\r
    UINT32    DeliveryMode     : 3;  ///< Specifies the type of interrupt to be sent.\r
    UINT32    Reserved0        : 1;  ///< Reserved.\r
    UINT32    DeliveryStatus   : 1;  ///< 0: Idle, 1: send pending.\r
    UINT32    InputPinPolarity : 1;  ///< Interrupt Input Pin Polarity.\r
    UINT32    RemoteIrr        : 1;  ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.\r
    UINT32    TriggerMode      : 1;  ///< 0:edge, 1:level.\r
    UINT32    Mask             : 1;  ///< 0: Not masked, 1: Masked.\r
    UINT32    Reserved1        : 15; ///< Reserved.\r
  } Bits;\r
  UINT32    Uint32;\r
} LOCAL_APIC_LVT_LINT;\r
\r
//\r
// MSI Address Register\r
//\r
typedef union {\r
  struct {\r
    UINT32    Reserved0       : 2;  ///< Reserved\r
    UINT32    DestinationMode : 1;  ///< Specifies the Destination Mode.\r
    UINT32    RedirectionHint : 1;  ///< Specifies the Redirection Hint.\r
    UINT32    Reserved1       : 8;  ///< Reserved.\r
    UINT32    DestinationId   : 8;  ///< Specifies the Destination ID.\r
    UINT32    BaseAddress     : 12; ///< Must be 0FEEH\r
  } Bits;\r
  UINT32    Uint32;\r
} LOCAL_APIC_MSI_ADDRESS;\r
\r
//\r
// MSI Address Register\r
//\r
typedef union {\r
  struct {\r
    UINT32    Vector       : 8;  ///< Interrupt vector in range 010h..0FEH\r
    UINT32    DeliveryMode : 3;  ///< Specifies the type of interrupt to be sent.\r
    UINT32    Reserved0    : 3;  ///< Reserved.\r
    UINT32    Level        : 1;  ///< 0:Deassert, 1:Assert.  Ignored for Edge triggered interrupts.\r
    UINT32    TriggerMode  : 1;  ///< 0:Edge,     1:Level.\r
    UINT32    Reserved1    : 16; ///< Reserved.\r
    UINT32    Reserved2    : 32; ///< Reserved.\r
  } Bits;\r
  UINT64    Uint64;\r
} LOCAL_APIC_MSI_DATA;\r
\r
#endif\r
Commit	Line	Data
e057908f RN	1	/** @file\r
	2	IA32 Local APIC Definitions.\r
	3	\r
	4	Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.<BR>\r
	5	SPDX-License-Identifier: BSD-2-Clause-Patent\r
	6	\r
	7	**/\r
	8	\r
	9	#ifndef __INTEL_LOCAL_APIC_H__\r
	10	#define __INTEL_LOCAL_APIC_H__\r
	11	\r
	12	//\r
	13	// Definition for Local APIC registers and related values\r
	14	//\r
2f88bd3a MK	15	#define XAPIC_ID_OFFSET 0x20\r
	16	#define XAPIC_VERSION_OFFSET 0x30\r
	17	#define XAPIC_EOI_OFFSET 0x0b0\r
	18	#define XAPIC_ICR_DFR_OFFSET 0x0e0\r
	19	#define XAPIC_SPURIOUS_VECTOR_OFFSET 0x0f0\r
	20	#define XAPIC_ICR_LOW_OFFSET 0x300\r
	21	#define XAPIC_ICR_HIGH_OFFSET 0x310\r
	22	#define XAPIC_LVT_TIMER_OFFSET 0x320\r
	23	#define XAPIC_LVT_LINT0_OFFSET 0x350\r
	24	#define XAPIC_LVT_LINT1_OFFSET 0x360\r
	25	#define XAPIC_TIMER_INIT_COUNT_OFFSET 0x380\r
	26	#define XAPIC_TIMER_CURRENT_COUNT_OFFSET 0x390\r
	27	#define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0\r
	28	\r
	29	#define X2APIC_MSR_BASE_ADDRESS 0x800\r
	30	#define X2APIC_MSR_ICR_ADDRESS 0x830\r
	31	\r
	32	#define LOCAL_APIC_DELIVERY_MODE_FIXED 0\r
	33	#define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1\r
	34	#define LOCAL_APIC_DELIVERY_MODE_SMI 2\r
	35	#define LOCAL_APIC_DELIVERY_MODE_NMI 4\r
	36	#define LOCAL_APIC_DELIVERY_MODE_INIT 5\r
	37	#define LOCAL_APIC_DELIVERY_MODE_STARTUP 6\r
	38	#define LOCAL_APIC_DELIVERY_MODE_EXTINT 7\r
	39	\r
	40	#define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND 0\r
	41	#define LOCAL_APIC_DESTINATION_SHORTHAND_SELF 1\r
	42	#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2\r
	43	#define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3\r
e057908f RN	44	\r
	45	//\r
	46	// Local APIC Version Register.\r
	47	//\r
	48	typedef union {\r
	49	struct {\r
2f88bd3a MK	50	UINT32 Version : 8; ///< The version numbers of the local APIC.\r
	51	UINT32 Reserved0 : 8; ///< Reserved.\r
	52	UINT32 MaxLvtEntry : 8; ///< Number of LVT entries minus 1.\r
	53	UINT32 EoiBroadcastSuppression : 1; ///< 1 if EOI-broadcast suppression supported.\r
	54	UINT32 Reserved1 : 7; ///< Reserved.\r
e057908f RN	55	} Bits;\r
	56	UINT32 Uint32;\r
	57	} LOCAL_APIC_VERSION;\r
	58	\r
	59	//\r
	60	// Low half of Interrupt Command Register (ICR).\r
	61	//\r
	62	typedef union {\r
	63	struct {\r
2f88bd3a MK	64	UINT32 Vector : 8; ///< The vector number of the interrupt being sent.\r
	65	UINT32 DeliveryMode : 3; ///< Specifies the type of IPI to be sent.\r
	66	UINT32 DestinationMode : 1; ///< 0: physical destination mode, 1: logical destination mode.\r
	67	UINT32 DeliveryStatus : 1; ///< Indicates the IPI delivery status. This field is reserved in x2APIC mode.\r
	68	UINT32 Reserved0 : 1; ///< Reserved.\r
	69	UINT32 Level : 1; ///< 0 for the INIT level de-assert delivery mode. Otherwise 1.\r
	70	UINT32 TriggerMode : 1; ///< 0: edge, 1: level when using the INIT level de-assert delivery mode.\r
	71	UINT32 Reserved1 : 2; ///< Reserved.\r
	72	UINT32 DestinationShorthand : 2; ///< A shorthand notation to specify the destination of the interrupt.\r
	73	UINT32 Reserved2 : 12; ///< Reserved.\r
e057908f RN	74	} Bits;\r
	75	UINT32 Uint32;\r
	76	} LOCAL_APIC_ICR_LOW;\r
	77	\r
	78	//\r
	79	// High half of Interrupt Command Register (ICR)\r
	80	//\r
	81	typedef union {\r
	82	struct {\r
2f88bd3a MK	83	UINT32 Reserved0 : 24; ///< Reserved.\r
2f88bd3a MK	84	UINT32 Destination : 8; ///< Specifies the target processor or processors in xAPIC mode.\r
e057908f RN	85	} Bits;\r
	86	UINT32 Uint32; ///< Destination field expanded to 32-bit in x2APIC mode.\r
	87	} LOCAL_APIC_ICR_HIGH;\r
	88	\r
	89	//\r
	90	// Spurious-Interrupt Vector Register (SVR)\r
	91	//\r
	92	typedef union {\r
	93	struct {\r
2f88bd3a MK	94	UINT32 SpuriousVector : 8; ///< Spurious Vector.\r
	95	UINT32 SoftwareEnable : 1; ///< APIC Software Enable/Disable.\r
	96	UINT32 FocusProcessorChecking : 1; ///< Focus Processor Checking.\r
	97	UINT32 Reserved0 : 2; ///< Reserved.\r
	98	UINT32 EoiBroadcastSuppression : 1; ///< EOI-Broadcast Suppression.\r
	99	UINT32 Reserved1 : 19; ///< Reserved.\r
e057908f RN	100	} Bits;\r
	101	UINT32 Uint32;\r
	102	} LOCAL_APIC_SVR;\r
	103	\r
	104	//\r
	105	// Divide Configuration Register (DCR)\r
	106	//\r
	107	typedef union {\r
	108	struct {\r
2f88bd3a MK	109	UINT32 DivideValue1 : 2; ///< Low 2 bits of the divide value.\r
	110	UINT32 Reserved0 : 1; ///< Always 0.\r
	111	UINT32 DivideValue2 : 1; ///< Highest 1 bit of the divide value.\r
	112	UINT32 Reserved1 : 28; ///< Reserved.\r
e057908f RN	113	} Bits;\r
	114	UINT32 Uint32;\r
	115	} LOCAL_APIC_DCR;\r
	116	\r
	117	//\r
	118	// LVT Timer Register\r
	119	//\r
	120	typedef union {\r
	121	struct {\r
2f88bd3a MK	122	UINT32 Vector : 8; ///< The vector number of the interrupt being sent.\r
	123	UINT32 Reserved0 : 4; ///< Reserved.\r
	124	UINT32 DeliveryStatus : 1; ///< 0: Idle, 1: send pending.\r
	125	UINT32 Reserved1 : 3; ///< Reserved.\r
	126	UINT32 Mask : 1; ///< 0: Not masked, 1: Masked.\r
	127	UINT32 TimerMode : 1; ///< 0: One-shot, 1: Periodic.\r
	128	UINT32 Reserved2 : 14; ///< Reserved.\r
e057908f RN	129	} Bits;\r
	130	UINT32 Uint32;\r
	131	} LOCAL_APIC_LVT_TIMER;\r
	132	\r
	133	//\r
	134	// LVT LINT0/LINT1 Register\r
	135	//\r
	136	typedef union {\r
	137	struct {\r
2f88bd3a MK	138	UINT32 Vector : 8; ///< The vector number of the interrupt being sent.\r
	139	UINT32 DeliveryMode : 3; ///< Specifies the type of interrupt to be sent.\r
	140	UINT32 Reserved0 : 1; ///< Reserved.\r
	141	UINT32 DeliveryStatus : 1; ///< 0: Idle, 1: send pending.\r
	142	UINT32 InputPinPolarity : 1; ///< Interrupt Input Pin Polarity.\r
	143	UINT32 RemoteIrr : 1; ///< RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.\r
	144	UINT32 TriggerMode : 1; ///< 0:edge, 1:level.\r
	145	UINT32 Mask : 1; ///< 0: Not masked, 1: Masked.\r
	146	UINT32 Reserved1 : 15; ///< Reserved.\r
e057908f RN	147	} Bits;\r
	148	UINT32 Uint32;\r
	149	} LOCAL_APIC_LVT_LINT;\r
	150	\r
	151	//\r
	152	// MSI Address Register\r
	153	//\r
	154	typedef union {\r
	155	struct {\r
2f88bd3a MK	156	UINT32 Reserved0 : 2; ///< Reserved\r
	157	UINT32 DestinationMode : 1; ///< Specifies the Destination Mode.\r
	158	UINT32 RedirectionHint : 1; ///< Specifies the Redirection Hint.\r
	159	UINT32 Reserved1 : 8; ///< Reserved.\r
	160	UINT32 DestinationId : 8; ///< Specifies the Destination ID.\r
	161	UINT32 BaseAddress : 12; ///< Must be 0FEEH\r
e057908f RN	162	} Bits;\r
	163	UINT32 Uint32;\r
	164	} LOCAL_APIC_MSI_ADDRESS;\r
	165	\r
	166	//\r
	167	// MSI Address Register\r
	168	//\r
	169	typedef union {\r
	170	struct {\r
2f88bd3a MK	171	UINT32 Vector : 8; ///< Interrupt vector in range 010h..0FEH\r
	172	UINT32 DeliveryMode : 3; ///< Specifies the type of interrupt to be sent.\r
	173	UINT32 Reserved0 : 3; ///< Reserved.\r
	174	UINT32 Level : 1; ///< 0:Deassert, 1:Assert. Ignored for Edge triggered interrupts.\r
	175	UINT32 TriggerMode : 1; ///< 0:Edge, 1:Level.\r
	176	UINT32 Reserved1 : 16; ///< Reserved.\r
	177	UINT32 Reserved2 : 32; ///< Reserved.\r
e057908f RN	178	} Bits;\r
	179	UINT64 Uint64;\r
	180	} LOCAL_APIC_MSI_DATA;\r
	181	\r
	182	#endif\r