]>
Commit | Line | Data |
---|---|---|
a646000f MK |
1 | /** @file\r |
2 | MSR Definitions for the Intel(R) Atom(TM) Processor Family.\r | |
3 | \r | |
4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
7 | provided for that MSR.\r | |
8 | \r | |
e057908f | 9 | Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r |
0acd8697 | 10 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
a646000f MK |
11 | \r |
12 | @par Specification Reference:\r | |
ba1a2d11 ED |
13 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r |
14 | May 2018, Volume 4: Model-Specific-Registers (MSR)\r | |
a646000f MK |
15 | \r |
16 | **/\r | |
17 | \r | |
18 | #ifndef __ATOM_MSR_H__\r | |
19 | #define __ATOM_MSR_H__\r | |
20 | \r | |
e057908f | 21 | #include <Register/Intel/ArchitecturalMsr.h>\r |
a646000f | 22 | \r |
f4c982bf JF |
23 | /**\r |
24 | Is Intel(R) Atom(TM) Processor Family?\r | |
25 | \r | |
26 | @param DisplayFamily Display Family ID\r | |
27 | @param DisplayModel Display Model ID\r | |
28 | \r | |
29 | @retval TRUE Yes, it is.\r | |
30 | @retval FALSE No, it isn't.\r | |
31 | **/\r | |
32 | #define IS_ATOM_PROCESSOR(DisplayFamily, DisplayModel) \\r | |
33 | (DisplayFamily == 0x06 && \\r | |
34 | ( \\r | |
35 | DisplayModel == 0x1C || \\r | |
36 | DisplayModel == 0x26 || \\r | |
37 | DisplayModel == 0x27 || \\r | |
38 | DisplayModel == 0x35 || \\r | |
39 | DisplayModel == 0x36 \\r | |
40 | ) \\r | |
41 | )\r | |
42 | \r | |
a646000f MK |
43 | /**\r |
44 | Shared. Model Specific Platform ID (R).\r | |
45 | \r | |
46 | @param ECX MSR_ATOM_PLATFORM_ID (0x00000017)\r | |
47 | @param EAX Lower 32-bits of MSR value.\r | |
48 | Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.\r | |
49 | @param EDX Upper 32-bits of MSR value.\r | |
50 | Described by the type MSR_ATOM_PLATFORM_ID_REGISTER.\r | |
51 | \r | |
52 | <b>Example usage</b>\r | |
53 | @code\r | |
54 | MSR_ATOM_PLATFORM_ID_REGISTER Msr;\r | |
55 | \r | |
56 | Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PLATFORM_ID);\r | |
57 | @endcode\r | |
800a651d | 58 | @note MSR_ATOM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.\r |
a646000f | 59 | **/\r |
2f88bd3a | 60 | #define MSR_ATOM_PLATFORM_ID 0x00000017\r |
a646000f MK |
61 | \r |
62 | /**\r | |
63 | MSR information returned for MSR index #MSR_ATOM_PLATFORM_ID\r | |
64 | **/\r | |
65 | typedef union {\r | |
66 | ///\r | |
67 | /// Individual bit fields\r | |
68 | ///\r | |
69 | struct {\r | |
2f88bd3a | 70 | UINT32 Reserved1 : 8;\r |
a646000f MK |
71 | ///\r |
72 | /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.\r | |
73 | ///\r | |
2f88bd3a MK |
74 | UINT32 MaximumQualifiedRatio : 5;\r |
75 | UINT32 Reserved2 : 19;\r | |
76 | UINT32 Reserved3 : 32;\r | |
a646000f MK |
77 | } Bits;\r |
78 | ///\r | |
79 | /// All bit fields as a 32-bit value\r | |
80 | ///\r | |
2f88bd3a | 81 | UINT32 Uint32;\r |
a646000f MK |
82 | ///\r |
83 | /// All bit fields as a 64-bit value\r | |
84 | ///\r | |
2f88bd3a | 85 | UINT64 Uint64;\r |
a646000f MK |
86 | } MSR_ATOM_PLATFORM_ID_REGISTER;\r |
87 | \r | |
a646000f MK |
88 | /**\r |
89 | Shared. Processor Hard Power-On Configuration (R/W) Enables and disables\r | |
90 | processor features; (R) indicates current processor configuration.\r | |
91 | \r | |
92 | @param ECX MSR_ATOM_EBL_CR_POWERON (0x0000002A)\r | |
93 | @param EAX Lower 32-bits of MSR value.\r | |
94 | Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.\r | |
95 | @param EDX Upper 32-bits of MSR value.\r | |
96 | Described by the type MSR_ATOM_EBL_CR_POWERON_REGISTER.\r | |
97 | \r | |
98 | <b>Example usage</b>\r | |
99 | @code\r | |
100 | MSR_ATOM_EBL_CR_POWERON_REGISTER Msr;\r | |
101 | \r | |
102 | Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_EBL_CR_POWERON);\r | |
103 | AsmWriteMsr64 (MSR_ATOM_EBL_CR_POWERON, Msr.Uint64);\r | |
104 | @endcode\r | |
800a651d | 105 | @note MSR_ATOM_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r |
a646000f | 106 | **/\r |
2f88bd3a | 107 | #define MSR_ATOM_EBL_CR_POWERON 0x0000002A\r |
a646000f MK |
108 | \r |
109 | /**\r | |
110 | MSR information returned for MSR index #MSR_ATOM_EBL_CR_POWERON\r | |
111 | **/\r | |
112 | typedef union {\r | |
113 | ///\r | |
114 | /// Individual bit fields\r | |
115 | ///\r | |
116 | struct {\r | |
2f88bd3a | 117 | UINT32 Reserved1 : 1;\r |
a646000f MK |
118 | ///\r |
119 | /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r | |
120 | /// Always 0.\r | |
121 | ///\r | |
2f88bd3a | 122 | UINT32 DataErrorCheckingEnable : 1;\r |
a646000f MK |
123 | ///\r |
124 | /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r | |
125 | /// Always 0.\r | |
126 | ///\r | |
2f88bd3a | 127 | UINT32 ResponseErrorCheckingEnable : 1;\r |
a646000f MK |
128 | ///\r |
129 | /// [Bit 3] AERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.\r | |
130 | ///\r | |
2f88bd3a | 131 | UINT32 AERR_DriveEnable : 1;\r |
a646000f MK |
132 | ///\r |
133 | /// [Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 =\r | |
134 | /// Disabled Always 0.\r | |
135 | ///\r | |
2f88bd3a MK |
136 | UINT32 BERR_Enable : 1;\r |
137 | UINT32 Reserved2 : 1;\r | |
138 | UINT32 Reserved3 : 1;\r | |
a646000f MK |
139 | ///\r |
140 | /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.\r | |
141 | ///\r | |
2f88bd3a MK |
142 | UINT32 BINIT_DriverEnable : 1;\r |
143 | UINT32 Reserved4 : 1;\r | |
a646000f MK |
144 | ///\r |
145 | /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.\r | |
146 | ///\r | |
2f88bd3a | 147 | UINT32 ExecuteBIST : 1;\r |
a646000f MK |
148 | ///\r |
149 | /// [Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r | |
150 | /// Always 0.\r | |
151 | ///\r | |
2f88bd3a MK |
152 | UINT32 AERR_ObservationEnabled : 1;\r |
153 | UINT32 Reserved5 : 1;\r | |
a646000f MK |
154 | ///\r |
155 | /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r | |
156 | /// Always 0.\r | |
157 | ///\r | |
2f88bd3a MK |
158 | UINT32 BINIT_ObservationEnabled : 1;\r |
159 | UINT32 Reserved6 : 1;\r | |
a646000f MK |
160 | ///\r |
161 | /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.\r | |
162 | ///\r | |
2f88bd3a MK |
163 | UINT32 ResetVector : 1;\r |
164 | UINT32 Reserved7 : 1;\r | |
a646000f MK |
165 | ///\r |
166 | /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B.\r | |
167 | ///\r | |
2f88bd3a MK |
168 | UINT32 APICClusterID : 2;\r |
169 | UINT32 Reserved8 : 2;\r | |
a646000f MK |
170 | ///\r |
171 | /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B.\r | |
172 | ///\r | |
2f88bd3a | 173 | UINT32 SymmetricArbitrationID : 2;\r |
a646000f MK |
174 | ///\r |
175 | /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).\r | |
176 | ///\r | |
2f88bd3a MK |
177 | UINT32 IntegerBusFrequencyRatio : 5;\r |
178 | UINT32 Reserved9 : 5;\r | |
179 | UINT32 Reserved10 : 32;\r | |
a646000f MK |
180 | } Bits;\r |
181 | ///\r | |
182 | /// All bit fields as a 32-bit value\r | |
183 | ///\r | |
2f88bd3a | 184 | UINT32 Uint32;\r |
a646000f MK |
185 | ///\r |
186 | /// All bit fields as a 64-bit value\r | |
187 | ///\r | |
2f88bd3a | 188 | UINT64 Uint64;\r |
a646000f MK |
189 | } MSR_ATOM_EBL_CR_POWERON_REGISTER;\r |
190 | \r | |
a646000f | 191 | /**\r |
0f16be6d HW |
192 | Unique. Last Branch Record n From IP (R/W) One of eight pairs of last branch\r |
193 | record registers on the last branch record stack. The From_IP part of the\r | |
194 | stack contains pointers to the source instruction . See also: - Last Branch\r | |
195 | Record Stack TOS at 1C9H - Section 17.5.\r | |
a646000f MK |
196 | \r |
197 | @param ECX MSR_ATOM_LASTBRANCH_n_FROM_IP\r | |
198 | @param EAX Lower 32-bits of MSR value.\r | |
199 | @param EDX Upper 32-bits of MSR value.\r | |
200 | \r | |
201 | <b>Example usage</b>\r | |
202 | @code\r | |
203 | UINT64 Msr;\r | |
204 | \r | |
205 | Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP);\r | |
206 | AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_FROM_IP, Msr);\r | |
207 | @endcode\r | |
800a651d JF |
208 | @note MSR_ATOM_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r |
209 | MSR_ATOM_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r | |
210 | MSR_ATOM_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r | |
211 | MSR_ATOM_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r | |
212 | MSR_ATOM_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.\r | |
213 | MSR_ATOM_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.\r | |
214 | MSR_ATOM_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.\r | |
215 | MSR_ATOM_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.\r | |
a646000f MK |
216 | @{\r |
217 | **/\r | |
2f88bd3a MK |
218 | #define MSR_ATOM_LASTBRANCH_0_FROM_IP 0x00000040\r |
219 | #define MSR_ATOM_LASTBRANCH_1_FROM_IP 0x00000041\r | |
220 | #define MSR_ATOM_LASTBRANCH_2_FROM_IP 0x00000042\r | |
221 | #define MSR_ATOM_LASTBRANCH_3_FROM_IP 0x00000043\r | |
222 | #define MSR_ATOM_LASTBRANCH_4_FROM_IP 0x00000044\r | |
223 | #define MSR_ATOM_LASTBRANCH_5_FROM_IP 0x00000045\r | |
224 | #define MSR_ATOM_LASTBRANCH_6_FROM_IP 0x00000046\r | |
225 | #define MSR_ATOM_LASTBRANCH_7_FROM_IP 0x00000047\r | |
a646000f MK |
226 | /// @}\r |
227 | \r | |
a646000f | 228 | /**\r |
0f16be6d HW |
229 | Unique. Last Branch Record n To IP (R/W) One of eight pairs of last branch\r |
230 | record registers on the last branch record stack. The To_IP part of the\r | |
231 | stack contains pointers to the destination instruction.\r | |
a646000f MK |
232 | \r |
233 | @param ECX MSR_ATOM_LASTBRANCH_n_TO_IP\r | |
234 | @param EAX Lower 32-bits of MSR value.\r | |
235 | @param EDX Upper 32-bits of MSR value.\r | |
236 | \r | |
237 | <b>Example usage</b>\r | |
238 | @code\r | |
239 | UINT64 Msr;\r | |
240 | \r | |
241 | Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP);\r | |
242 | AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_0_TO_IP, Msr);\r | |
243 | @endcode\r | |
800a651d JF |
244 | @note MSR_ATOM_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r |
245 | MSR_ATOM_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r | |
246 | MSR_ATOM_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r | |
247 | MSR_ATOM_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r | |
248 | MSR_ATOM_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.\r | |
249 | MSR_ATOM_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.\r | |
250 | MSR_ATOM_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.\r | |
251 | MSR_ATOM_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.\r | |
a646000f MK |
252 | @{\r |
253 | **/\r | |
2f88bd3a MK |
254 | #define MSR_ATOM_LASTBRANCH_0_TO_IP 0x00000060\r |
255 | #define MSR_ATOM_LASTBRANCH_1_TO_IP 0x00000061\r | |
256 | #define MSR_ATOM_LASTBRANCH_2_TO_IP 0x00000062\r | |
257 | #define MSR_ATOM_LASTBRANCH_3_TO_IP 0x00000063\r | |
258 | #define MSR_ATOM_LASTBRANCH_4_TO_IP 0x00000064\r | |
259 | #define MSR_ATOM_LASTBRANCH_5_TO_IP 0x00000065\r | |
260 | #define MSR_ATOM_LASTBRANCH_6_TO_IP 0x00000066\r | |
261 | #define MSR_ATOM_LASTBRANCH_7_TO_IP 0x00000067\r | |
a646000f MK |
262 | /// @}\r |
263 | \r | |
a646000f MK |
264 | /**\r |
265 | Shared. Scalable Bus Speed(RO) This field indicates the intended scalable\r | |
266 | bus clock speed for processors based on Intel Atom microarchitecture:.\r | |
267 | \r | |
268 | @param ECX MSR_ATOM_FSB_FREQ (0x000000CD)\r | |
269 | @param EAX Lower 32-bits of MSR value.\r | |
270 | Described by the type MSR_ATOM_FSB_FREQ_REGISTER.\r | |
271 | @param EDX Upper 32-bits of MSR value.\r | |
272 | Described by the type MSR_ATOM_FSB_FREQ_REGISTER.\r | |
273 | \r | |
274 | <b>Example usage</b>\r | |
275 | @code\r | |
276 | MSR_ATOM_FSB_FREQ_REGISTER Msr;\r | |
277 | \r | |
278 | Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_FSB_FREQ);\r | |
279 | @endcode\r | |
800a651d | 280 | @note MSR_ATOM_FSB_FREQ is defined as MSR_FSB_FREQ in SDM.\r |
a646000f | 281 | **/\r |
2f88bd3a | 282 | #define MSR_ATOM_FSB_FREQ 0x000000CD\r |
a646000f MK |
283 | \r |
284 | /**\r | |
285 | MSR information returned for MSR index #MSR_ATOM_FSB_FREQ\r | |
286 | **/\r | |
287 | typedef union {\r | |
288 | ///\r | |
289 | /// Individual bit fields\r | |
290 | ///\r | |
291 | struct {\r | |
292 | ///\r | |
293 | /// [Bits 2:0] - Scalable Bus Speed\r | |
294 | ///\r | |
295 | /// Atom Processor Family\r | |
296 | /// ---------------------\r | |
297 | /// 111B: 083 MHz (FSB 333)\r | |
298 | /// 101B: 100 MHz (FSB 400)\r | |
299 | /// 001B: 133 MHz (FSB 533)\r | |
300 | /// 011B: 167 MHz (FSB 667)\r | |
301 | ///\r | |
302 | /// 133.33 MHz should be utilized if performing calculation with\r | |
303 | /// System Bus Speed when encoding is 001B.\r | |
304 | /// 166.67 MHz should be utilized if performing calculation with\r | |
305 | /// System Bus Speed when\r | |
306 | /// encoding is 011B.\r | |
307 | ///\r | |
2f88bd3a MK |
308 | UINT32 ScalableBusSpeed : 3;\r |
309 | UINT32 Reserved1 : 29;\r | |
310 | UINT32 Reserved2 : 32;\r | |
a646000f MK |
311 | } Bits;\r |
312 | ///\r | |
313 | /// All bit fields as a 32-bit value\r | |
314 | ///\r | |
2f88bd3a | 315 | UINT32 Uint32;\r |
a646000f MK |
316 | ///\r |
317 | /// All bit fields as a 64-bit value\r | |
318 | ///\r | |
2f88bd3a | 319 | UINT64 Uint64;\r |
a646000f MK |
320 | } MSR_ATOM_FSB_FREQ_REGISTER;\r |
321 | \r | |
a646000f MK |
322 | /**\r |
323 | Shared.\r | |
324 | \r | |
325 | @param ECX MSR_ATOM_BBL_CR_CTL3 (0x0000011E)\r | |
326 | @param EAX Lower 32-bits of MSR value.\r | |
327 | Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.\r | |
328 | @param EDX Upper 32-bits of MSR value.\r | |
329 | Described by the type MSR_ATOM_BBL_CR_CTL3_REGISTER.\r | |
330 | \r | |
331 | <b>Example usage</b>\r | |
332 | @code\r | |
333 | MSR_ATOM_BBL_CR_CTL3_REGISTER Msr;\r | |
334 | \r | |
335 | Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_BBL_CR_CTL3);\r | |
336 | AsmWriteMsr64 (MSR_ATOM_BBL_CR_CTL3, Msr.Uint64);\r | |
337 | @endcode\r | |
800a651d | 338 | @note MSR_ATOM_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r |
a646000f | 339 | **/\r |
2f88bd3a | 340 | #define MSR_ATOM_BBL_CR_CTL3 0x0000011E\r |
a646000f MK |
341 | \r |
342 | /**\r | |
343 | MSR information returned for MSR index #MSR_ATOM_BBL_CR_CTL3\r | |
344 | **/\r | |
345 | typedef union {\r | |
346 | ///\r | |
347 | /// Individual bit fields\r | |
348 | ///\r | |
349 | struct {\r | |
350 | ///\r | |
351 | /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r | |
352 | /// Indicates if the L2 is hardware-disabled.\r | |
353 | ///\r | |
2f88bd3a MK |
354 | UINT32 L2HardwareEnabled : 1;\r |
355 | UINT32 Reserved1 : 7;\r | |
a646000f MK |
356 | ///\r |
357 | /// [Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 =\r | |
358 | /// Disabled (default) Until this bit is set the processor will not\r | |
359 | /// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r | |
360 | ///\r | |
2f88bd3a MK |
361 | UINT32 L2Enabled : 1;\r |
362 | UINT32 Reserved2 : 14;\r | |
a646000f MK |
363 | ///\r |
364 | /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.\r | |
365 | ///\r | |
2f88bd3a MK |
366 | UINT32 L2NotPresent : 1;\r |
367 | UINT32 Reserved3 : 8;\r | |
368 | UINT32 Reserved4 : 32;\r | |
a646000f MK |
369 | } Bits;\r |
370 | ///\r | |
371 | /// All bit fields as a 32-bit value\r | |
372 | ///\r | |
2f88bd3a | 373 | UINT32 Uint32;\r |
a646000f MK |
374 | ///\r |
375 | /// All bit fields as a 64-bit value\r | |
376 | ///\r | |
2f88bd3a | 377 | UINT64 Uint64;\r |
a646000f MK |
378 | } MSR_ATOM_BBL_CR_CTL3_REGISTER;\r |
379 | \r | |
a646000f MK |
380 | /**\r |
381 | Shared.\r | |
382 | \r | |
383 | @param ECX MSR_ATOM_PERF_STATUS (0x00000198)\r | |
384 | @param EAX Lower 32-bits of MSR value.\r | |
385 | Described by the type MSR_ATOM_PERF_STATUS_REGISTER.\r | |
386 | @param EDX Upper 32-bits of MSR value.\r | |
387 | Described by the type MSR_ATOM_PERF_STATUS_REGISTER.\r | |
388 | \r | |
389 | <b>Example usage</b>\r | |
390 | @code\r | |
391 | MSR_ATOM_PERF_STATUS_REGISTER Msr;\r | |
392 | \r | |
393 | Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PERF_STATUS);\r | |
394 | AsmWriteMsr64 (MSR_ATOM_PERF_STATUS, Msr.Uint64);\r | |
395 | @endcode\r | |
800a651d | 396 | @note MSR_ATOM_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.\r |
a646000f | 397 | **/\r |
2f88bd3a | 398 | #define MSR_ATOM_PERF_STATUS 0x00000198\r |
a646000f MK |
399 | \r |
400 | /**\r | |
401 | MSR information returned for MSR index #MSR_ATOM_PERF_STATUS\r | |
402 | **/\r | |
403 | typedef union {\r | |
404 | ///\r | |
405 | /// Individual bit fields\r | |
406 | ///\r | |
407 | struct {\r | |
408 | ///\r | |
409 | /// [Bits 15:0] Current Performance State Value.\r | |
410 | ///\r | |
2f88bd3a MK |
411 | UINT32 CurrentPerformanceStateValue : 16;\r |
412 | UINT32 Reserved1 : 16;\r | |
413 | UINT32 Reserved2 : 8;\r | |
a646000f MK |
414 | ///\r |
415 | /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio\r | |
416 | /// configured for the processor.\r | |
417 | ///\r | |
2f88bd3a MK |
418 | UINT32 MaximumBusRatio : 5;\r |
419 | UINT32 Reserved3 : 19;\r | |
a646000f MK |
420 | } Bits;\r |
421 | ///\r | |
422 | /// All bit fields as a 64-bit value\r | |
423 | ///\r | |
2f88bd3a | 424 | UINT64 Uint64;\r |
a646000f MK |
425 | } MSR_ATOM_PERF_STATUS_REGISTER;\r |
426 | \r | |
a646000f MK |
427 | /**\r |
428 | Shared.\r | |
429 | \r | |
430 | @param ECX MSR_ATOM_THERM2_CTL (0x0000019D)\r | |
431 | @param EAX Lower 32-bits of MSR value.\r | |
432 | Described by the type MSR_ATOM_THERM2_CTL_REGISTER.\r | |
433 | @param EDX Upper 32-bits of MSR value.\r | |
434 | Described by the type MSR_ATOM_THERM2_CTL_REGISTER.\r | |
435 | \r | |
436 | <b>Example usage</b>\r | |
437 | @code\r | |
438 | MSR_ATOM_THERM2_CTL_REGISTER Msr;\r | |
439 | \r | |
440 | Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_THERM2_CTL);\r | |
441 | AsmWriteMsr64 (MSR_ATOM_THERM2_CTL, Msr.Uint64);\r | |
442 | @endcode\r | |
800a651d | 443 | @note MSR_ATOM_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r |
a646000f | 444 | **/\r |
2f88bd3a | 445 | #define MSR_ATOM_THERM2_CTL 0x0000019D\r |
a646000f MK |
446 | \r |
447 | /**\r | |
448 | MSR information returned for MSR index #MSR_ATOM_THERM2_CTL\r | |
449 | **/\r | |
450 | typedef union {\r | |
451 | ///\r | |
452 | /// Individual bit fields\r | |
453 | ///\r | |
454 | struct {\r | |
2f88bd3a | 455 | UINT32 Reserved1 : 16;\r |
a646000f MK |
456 | ///\r |
457 | /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =\r | |
458 | /// Thermal Monitor 1 (thermally-initiated on-die modulation of the\r | |
459 | /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated\r | |
460 | /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is\r | |
461 | /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.\r | |
462 | ///\r | |
2f88bd3a MK |
463 | UINT32 TM_SELECT : 1;\r |
464 | UINT32 Reserved2 : 15;\r | |
465 | UINT32 Reserved3 : 32;\r | |
a646000f MK |
466 | } Bits;\r |
467 | ///\r | |
468 | /// All bit fields as a 32-bit value\r | |
469 | ///\r | |
2f88bd3a | 470 | UINT32 Uint32;\r |
a646000f MK |
471 | ///\r |
472 | /// All bit fields as a 64-bit value\r | |
473 | ///\r | |
2f88bd3a | 474 | UINT64 Uint64;\r |
a646000f MK |
475 | } MSR_ATOM_THERM2_CTL_REGISTER;\r |
476 | \r | |
a646000f MK |
477 | /**\r |
478 | Unique. Enable Misc. Processor Features (R/W) Allows a variety of processor\r | |
479 | functions to be enabled and disabled.\r | |
480 | \r | |
481 | @param ECX MSR_ATOM_IA32_MISC_ENABLE (0x000001A0)\r | |
482 | @param EAX Lower 32-bits of MSR value.\r | |
483 | Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.\r | |
484 | @param EDX Upper 32-bits of MSR value.\r | |
485 | Described by the type MSR_ATOM_IA32_MISC_ENABLE_REGISTER.\r | |
486 | \r | |
487 | <b>Example usage</b>\r | |
488 | @code\r | |
489 | MSR_ATOM_IA32_MISC_ENABLE_REGISTER Msr;\r | |
490 | \r | |
491 | Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_IA32_MISC_ENABLE);\r | |
492 | AsmWriteMsr64 (MSR_ATOM_IA32_MISC_ENABLE, Msr.Uint64);\r | |
493 | @endcode\r | |
800a651d | 494 | @note MSR_ATOM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r |
a646000f | 495 | **/\r |
2f88bd3a | 496 | #define MSR_ATOM_IA32_MISC_ENABLE 0x000001A0\r |
a646000f MK |
497 | \r |
498 | /**\r | |
499 | MSR information returned for MSR index #MSR_ATOM_IA32_MISC_ENABLE\r | |
500 | **/\r | |
501 | typedef union {\r | |
502 | ///\r | |
503 | /// Individual bit fields\r | |
504 | ///\r | |
505 | struct {\r | |
506 | ///\r | |
ba1a2d11 | 507 | /// [Bit 0] Fast-Strings Enable See Table 2-2.\r |
a646000f | 508 | ///\r |
2f88bd3a MK |
509 | UINT32 FastStrings : 1;\r |
510 | UINT32 Reserved1 : 2;\r | |
a646000f MK |
511 | ///\r |
512 | /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See\r | |
ba1a2d11 | 513 | /// Table 2-2. Default value is 0.\r |
a646000f | 514 | ///\r |
2f88bd3a MK |
515 | UINT32 AutomaticThermalControlCircuit : 1;\r |
516 | UINT32 Reserved2 : 3;\r | |
a646000f | 517 | ///\r |
ba1a2d11 | 518 | /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.\r |
a646000f | 519 | ///\r |
2f88bd3a MK |
520 | UINT32 PerformanceMonitoring : 1;\r |
521 | UINT32 Reserved3 : 1;\r | |
522 | UINT32 Reserved4 : 1;\r | |
a646000f MK |
523 | ///\r |
524 | /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by\r | |
525 | /// the processor to indicate a pending break event within the processor 0\r | |
526 | /// = Indicates compatible FERR# signaling behavior This bit must be set\r | |
527 | /// to 1 to support XAPIC interrupt model usage.\r | |
528 | ///\r | |
2f88bd3a | 529 | UINT32 FERR : 1;\r |
a646000f | 530 | ///\r |
ba1a2d11 | 531 | /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.\r |
a646000f | 532 | ///\r |
2f88bd3a | 533 | UINT32 BTS : 1;\r |
a646000f | 534 | ///\r |
0f16be6d | 535 | /// [Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See\r |
ba1a2d11 | 536 | /// Table 2-2.\r |
a646000f | 537 | ///\r |
2f88bd3a | 538 | UINT32 PEBS : 1;\r |
a646000f MK |
539 | ///\r |
540 | /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the\r | |
541 | /// thermal sensor indicates that the die temperature is at the\r | |
542 | /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.\r | |
543 | /// TM2 will reduce the bus to core ratio and voltage according to the\r | |
544 | /// value last written to MSR_THERM2_CTL bits 15:0.\r | |
545 | /// When this bit is clear (0, default), the processor does not change\r | |
546 | /// the VID signals or the bus to core ratio when the processor enters a\r | |
547 | /// thermally managed state. The BIOS must enable this feature if the\r | |
548 | /// TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is\r | |
549 | /// not set, this feature is not supported and BIOS must not alter the\r | |
550 | /// contents of the TM2 bit location. The processor is operating out of\r | |
551 | /// specification if both this bit and the TM1 bit are set to 0.\r | |
552 | ///\r | |
2f88bd3a MK |
553 | UINT32 TM2 : 1;\r |
554 | UINT32 Reserved5 : 2;\r | |
a646000f MK |
555 | ///\r |
556 | /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See\r | |
ba1a2d11 | 557 | /// Table 2-2.\r |
a646000f | 558 | ///\r |
2f88bd3a MK |
559 | UINT32 EIST : 1;\r |
560 | UINT32 Reserved6 : 1;\r | |
a646000f | 561 | ///\r |
ba1a2d11 | 562 | /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.\r |
a646000f | 563 | ///\r |
2f88bd3a MK |
564 | UINT32 MONITOR : 1;\r |
565 | UINT32 Reserved7 : 1;\r | |
a646000f MK |
566 | ///\r |
567 | /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock\r | |
568 | /// (R/WO) When set, this bit causes the following bits to become\r | |
569 | /// read-only: - Enhanced Intel SpeedStep Technology Select Lock (this\r | |
570 | /// bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must\r | |
571 | /// be set before an Enhanced Intel SpeedStep Technology transition is\r | |
572 | /// requested. This bit is cleared on reset.\r | |
573 | ///\r | |
2f88bd3a MK |
574 | UINT32 EISTLock : 1;\r |
575 | UINT32 Reserved8 : 1;\r | |
a646000f | 576 | ///\r |
ba1a2d11 | 577 | /// [Bit 22] Unique. Limit CPUID Maxval (R/W) See Table 2-2.\r |
a646000f | 578 | ///\r |
2f88bd3a | 579 | UINT32 LimitCpuidMaxval : 1;\r |
a646000f | 580 | ///\r |
ba1a2d11 | 581 | /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.\r |
a646000f | 582 | ///\r |
2f88bd3a MK |
583 | UINT32 xTPR_Message_Disable : 1;\r |
584 | UINT32 Reserved9 : 8;\r | |
585 | UINT32 Reserved10 : 2;\r | |
a646000f | 586 | ///\r |
ba1a2d11 | 587 | /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.\r |
a646000f | 588 | ///\r |
2f88bd3a MK |
589 | UINT32 XD : 1;\r |
590 | UINT32 Reserved11 : 29;\r | |
a646000f MK |
591 | } Bits;\r |
592 | ///\r | |
593 | /// All bit fields as a 64-bit value\r | |
594 | ///\r | |
2f88bd3a | 595 | UINT64 Uint64;\r |
a646000f MK |
596 | } MSR_ATOM_IA32_MISC_ENABLE_REGISTER;\r |
597 | \r | |
a646000f MK |
598 | /**\r |
599 | Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-2)\r | |
600 | that points to the MSR containing the most recent branch record. See\r | |
601 | MSR_LASTBRANCH_0_FROM_IP (at 40H).\r | |
602 | \r | |
603 | @param ECX MSR_ATOM_LASTBRANCH_TOS (0x000001C9)\r | |
604 | @param EAX Lower 32-bits of MSR value.\r | |
605 | @param EDX Upper 32-bits of MSR value.\r | |
606 | \r | |
607 | <b>Example usage</b>\r | |
608 | @code\r | |
609 | UINT64 Msr;\r | |
610 | \r | |
611 | Msr = AsmReadMsr64 (MSR_ATOM_LASTBRANCH_TOS);\r | |
612 | AsmWriteMsr64 (MSR_ATOM_LASTBRANCH_TOS, Msr);\r | |
613 | @endcode\r | |
800a651d | 614 | @note MSR_ATOM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r |
a646000f | 615 | **/\r |
2f88bd3a | 616 | #define MSR_ATOM_LASTBRANCH_TOS 0x000001C9\r |
a646000f MK |
617 | \r |
618 | /**\r | |
619 | Unique. Last Exception Record From Linear IP (R) Contains a pointer to the\r | |
620 | last branch instruction that the processor executed prior to the last\r | |
621 | exception that was generated or the last interrupt that was handled.\r | |
622 | \r | |
623 | @param ECX MSR_ATOM_LER_FROM_LIP (0x000001DD)\r | |
624 | @param EAX Lower 32-bits of MSR value.\r | |
625 | @param EDX Upper 32-bits of MSR value.\r | |
626 | \r | |
627 | <b>Example usage</b>\r | |
628 | @code\r | |
629 | UINT64 Msr;\r | |
630 | \r | |
631 | Msr = AsmReadMsr64 (MSR_ATOM_LER_FROM_LIP);\r | |
632 | @endcode\r | |
800a651d | 633 | @note MSR_ATOM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r |
a646000f | 634 | **/\r |
2f88bd3a | 635 | #define MSR_ATOM_LER_FROM_LIP 0x000001DD\r |
a646000f MK |
636 | \r |
637 | /**\r | |
638 | Unique. Last Exception Record To Linear IP (R) This area contains a pointer\r | |
639 | to the target of the last branch instruction that the processor executed\r | |
640 | prior to the last exception that was generated or the last interrupt that\r | |
641 | was handled.\r | |
642 | \r | |
643 | @param ECX MSR_ATOM_LER_TO_LIP (0x000001DE)\r | |
644 | @param EAX Lower 32-bits of MSR value.\r | |
645 | @param EDX Upper 32-bits of MSR value.\r | |
646 | \r | |
647 | <b>Example usage</b>\r | |
648 | @code\r | |
649 | UINT64 Msr;\r | |
650 | \r | |
651 | Msr = AsmReadMsr64 (MSR_ATOM_LER_TO_LIP);\r | |
652 | @endcode\r | |
800a651d | 653 | @note MSR_ATOM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r |
a646000f | 654 | **/\r |
2f88bd3a | 655 | #define MSR_ATOM_LER_TO_LIP 0x000001DE\r |
a646000f MK |
656 | \r |
657 | /**\r | |
ba1a2d11 | 658 | Unique. See Table 2-2. See Section 18.6.2.4, "Processor Event Based Sampling\r |
a646000f MK |
659 | (PEBS).".\r |
660 | \r | |
661 | @param ECX MSR_ATOM_PEBS_ENABLE (0x000003F1)\r | |
662 | @param EAX Lower 32-bits of MSR value.\r | |
663 | Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.\r | |
664 | @param EDX Upper 32-bits of MSR value.\r | |
665 | Described by the type MSR_ATOM_PEBS_ENABLE_REGISTER.\r | |
666 | \r | |
667 | <b>Example usage</b>\r | |
668 | @code\r | |
669 | MSR_ATOM_PEBS_ENABLE_REGISTER Msr;\r | |
670 | \r | |
671 | Msr.Uint64 = AsmReadMsr64 (MSR_ATOM_PEBS_ENABLE);\r | |
672 | AsmWriteMsr64 (MSR_ATOM_PEBS_ENABLE, Msr.Uint64);\r | |
673 | @endcode\r | |
800a651d | 674 | @note MSR_ATOM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r |
a646000f | 675 | **/\r |
2f88bd3a | 676 | #define MSR_ATOM_PEBS_ENABLE 0x000003F1\r |
a646000f MK |
677 | \r |
678 | /**\r | |
679 | MSR information returned for MSR index #MSR_ATOM_PEBS_ENABLE\r | |
680 | **/\r | |
681 | typedef union {\r | |
682 | ///\r | |
683 | /// Individual bit fields\r | |
684 | ///\r | |
685 | struct {\r | |
686 | ///\r | |
687 | /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r | |
688 | ///\r | |
2f88bd3a MK |
689 | UINT32 Enable : 1;\r |
690 | UINT32 Reserved1 : 31;\r | |
691 | UINT32 Reserved2 : 32;\r | |
a646000f MK |
692 | } Bits;\r |
693 | ///\r | |
694 | /// All bit fields as a 32-bit value\r | |
695 | ///\r | |
2f88bd3a | 696 | UINT32 Uint32;\r |
a646000f MK |
697 | ///\r |
698 | /// All bit fields as a 64-bit value\r | |
699 | ///\r | |
2f88bd3a | 700 | UINT64 Uint64;\r |
a646000f MK |
701 | } MSR_ATOM_PEBS_ENABLE_REGISTER;\r |
702 | \r | |
a646000f MK |
703 | /**\r |
704 | Package. Package C2 Residency Note: C-state values are processor specific\r | |
705 | C-state code names, unrelated to MWAIT extension C-state parameters or ACPI\r | |
706 | C-States. Package. Package C2 Residency Counter. (R/O) Time that this\r | |
707 | package is in processor-specific C2 states since last reset. Counts at 1 Mhz\r | |
708 | frequency.\r | |
709 | \r | |
710 | @param ECX MSR_ATOM_PKG_C2_RESIDENCY (0x000003F8)\r | |
711 | @param EAX Lower 32-bits of MSR value.\r | |
712 | @param EDX Upper 32-bits of MSR value.\r | |
713 | \r | |
714 | <b>Example usage</b>\r | |
715 | @code\r | |
716 | UINT64 Msr;\r | |
717 | \r | |
718 | Msr = AsmReadMsr64 (MSR_ATOM_PKG_C2_RESIDENCY);\r | |
719 | AsmWriteMsr64 (MSR_ATOM_PKG_C2_RESIDENCY, Msr);\r | |
720 | @endcode\r | |
800a651d | 721 | @note MSR_ATOM_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.\r |
a646000f | 722 | **/\r |
2f88bd3a | 723 | #define MSR_ATOM_PKG_C2_RESIDENCY 0x000003F8\r |
a646000f MK |
724 | \r |
725 | /**\r | |
726 | Package. Package C4 Residency Note: C-state values are processor specific\r | |
727 | C-state code names, unrelated to MWAIT extension C-state parameters or ACPI\r | |
728 | C-States. Package. Package C4 Residency Counter. (R/O) Time that this\r | |
729 | package is in processor-specific C4 states since last reset. Counts at 1 Mhz\r | |
730 | frequency.\r | |
731 | \r | |
732 | @param ECX MSR_ATOM_PKG_C4_RESIDENCY (0x000003F9)\r | |
733 | @param EAX Lower 32-bits of MSR value.\r | |
734 | @param EDX Upper 32-bits of MSR value.\r | |
735 | \r | |
736 | <b>Example usage</b>\r | |
737 | @code\r | |
738 | UINT64 Msr;\r | |
739 | \r | |
740 | Msr = AsmReadMsr64 (MSR_ATOM_PKG_C4_RESIDENCY);\r | |
741 | AsmWriteMsr64 (MSR_ATOM_PKG_C4_RESIDENCY, Msr);\r | |
742 | @endcode\r | |
800a651d | 743 | @note MSR_ATOM_PKG_C4_RESIDENCY is defined as MSR_PKG_C4_RESIDENCY in SDM.\r |
a646000f | 744 | **/\r |
2f88bd3a | 745 | #define MSR_ATOM_PKG_C4_RESIDENCY 0x000003F9\r |
a646000f MK |
746 | \r |
747 | /**\r | |
748 | Package. Package C6 Residency Note: C-state values are processor specific\r | |
749 | C-state code names, unrelated to MWAIT extension C-state parameters or ACPI\r | |
750 | C-States. Package. Package C6 Residency Counter. (R/O) Time that this\r | |
751 | package is in processor-specific C6 states since last reset. Counts at 1 Mhz\r | |
752 | frequency.\r | |
753 | \r | |
754 | @param ECX MSR_ATOM_PKG_C6_RESIDENCY (0x000003FA)\r | |
755 | @param EAX Lower 32-bits of MSR value.\r | |
756 | @param EDX Upper 32-bits of MSR value.\r | |
757 | \r | |
758 | <b>Example usage</b>\r | |
759 | @code\r | |
760 | UINT64 Msr;\r | |
761 | \r | |
762 | Msr = AsmReadMsr64 (MSR_ATOM_PKG_C6_RESIDENCY);\r | |
763 | AsmWriteMsr64 (MSR_ATOM_PKG_C6_RESIDENCY, Msr);\r | |
764 | @endcode\r | |
800a651d | 765 | @note MSR_ATOM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r |
a646000f | 766 | **/\r |
2f88bd3a | 767 | #define MSR_ATOM_PKG_C6_RESIDENCY 0x000003FA\r |
a646000f MK |
768 | \r |
769 | #endif\r |