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/** @file\r
  MSR Definitions for Intel processors based on the Nehalem microarchitecture.\r
\r
  Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
  are provided for MSRs that contain one or more bit fields.  If the MSR value\r
  returned is a single 32-bit or 64-bit value, then a data structure is not\r
  provided for that MSR.\r
\r
  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
  @par Specification Reference:\r
  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
  May 2018, Volume 4: Model-Specific-Registers (MSR)\r
\r
**/\r
\r
#ifndef __NEHALEM_MSR_H__\r
#define __NEHALEM_MSR_H__\r
\r
#include <Register/Intel/ArchitecturalMsr.h>\r
\r
/**\r
  Is Intel processors based on the Nehalem microarchitecture?\r
\r
  @param   DisplayFamily  Display Family ID\r
  @param   DisplayModel   Display Model ID\r
\r
  @retval  TRUE   Yes, it is.\r
  @retval  FALSE  No, it isn't.\r
**/\r
#define IS_NEHALEM_PROCESSOR(DisplayFamily, DisplayModel) \\r
  (DisplayFamily == 0x06 && \\r
   (                        \\r
    DisplayModel == 0x1A || \\r
    DisplayModel == 0x1E || \\r
    DisplayModel == 0x1F || \\r
    DisplayModel == 0x2E    \\r
    )                       \\r
   )\r
\r
/**\r
  Package. Model Specific Platform ID (R).\r
\r
  @param  ECX  MSR_NEHALEM_PLATFORM_ID (0x00000017)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_PLATFORM_ID_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_NEHALEM_PLATFORM_ID_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_ID);\r
  @endcode\r
  @note MSR_NEHALEM_PLATFORM_ID is defined as MSR_PLATFORM_ID in SDM.\r
**/\r
#define MSR_NEHALEM_PLATFORM_ID  0x00000017\r
\r
/**\r
  MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_ID\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    UINT32    Reserved1  : 32;\r
    UINT32    Reserved2  : 18;\r
    ///\r
    /// [Bits 52:50] See Table 2-2.\r
    ///\r
    UINT32    PlatformId : 3;\r
    UINT32    Reserved3  : 11;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64    Uint64;\r
} MSR_NEHALEM_PLATFORM_ID_REGISTER;\r
\r
/**\r
  Thread. SMI Counter (R/O).\r
\r
  @param  ECX  MSR_NEHALEM_SMI_COUNT (0x00000034)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_SMI_COUNT_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_NEHALEM_SMI_COUNT_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_SMI_COUNT);\r
  @endcode\r
  @note MSR_NEHALEM_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.\r
**/\r
#define MSR_NEHALEM_SMI_COUNT  0x00000034\r
\r
/**\r
  MSR information returned for MSR index #MSR_NEHALEM_SMI_COUNT\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 31:0] SMI Count (R/O)  Running count of SMI events since last\r
    /// RESET.\r
    ///\r
    UINT32    SMICount : 32;\r
    UINT32    Reserved : 32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64    Uint64;\r
} MSR_NEHALEM_SMI_COUNT_REGISTER;\r
\r
/**\r
  Package. see http://biosbits.org.\r
\r
  @param  ECX  MSR_NEHALEM_PLATFORM_INFO (0x000000CE)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_PLATFORM_INFO_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_NEHALEM_PLATFORM_INFO_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PLATFORM_INFO);\r
  AsmWriteMsr64 (MSR_NEHALEM_PLATFORM_INFO, Msr.Uint64);\r
  @endcode\r
  @note MSR_NEHALEM_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
**/\r
#define MSR_NEHALEM_PLATFORM_INFO  0x000000CE\r
\r
/**\r
  MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_INFO\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    UINT32    Reserved1              : 8;\r
    ///\r
    /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O)  The is the ratio\r
    /// of the frequency that invariant TSC runs at. The invariant TSC\r
    /// frequency can be computed by multiplying this ratio by 133.33 MHz.\r
    ///\r
    UINT32    MaximumNonTurboRatio   : 8;\r
    UINT32    Reserved2              : 12;\r
    ///\r
    /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O)  When\r
    /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r
    /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r
    /// Turbo mode is disabled.\r
    ///\r
    UINT32    RatioLimit             : 1;\r
    ///\r
    /// [Bit 29] Package. Programmable TDC-TDP Limit for Turbo Mode (R/O)\r
    /// When set to 1, indicates that TDC/TDP Limits for Turbo mode are\r
    /// programmable, and when set to 0, indicates TDC and TDP Limits for\r
    /// Turbo mode are not programmable.\r
    ///\r
    UINT32    TDC_TDPLimit           : 1;\r
    UINT32    Reserved3              : 2;\r
    UINT32    Reserved4              : 8;\r
    ///\r
    /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O)  The is the\r
    /// minimum ratio (maximum efficiency) that the processor can operates, in\r
    /// units of 133.33MHz.\r
    ///\r
    UINT32    MaximumEfficiencyRatio : 8;\r
    UINT32    Reserved5              : 16;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64    Uint64;\r
} MSR_NEHALEM_PLATFORM_INFO_REGISTER;\r
\r
/**\r
  Core. C-State Configuration Control (R/W)  Note: C-state values are\r
  processor specific C-state code names, unrelated to MWAIT extension C-state\r
  parameters or ACPI CStates. See http://biosbits.org.\r
\r
  @param  ECX  MSR_NEHALEM_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL);\r
  AsmWriteMsr64 (MSR_NEHALEM_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
  @endcode\r
  @note MSR_NEHALEM_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
**/\r
#define MSR_NEHALEM_PKG_CST_CONFIG_CONTROL  0x000000E2\r
\r
/**\r
  MSR information returned for MSR index #MSR_NEHALEM_PKG_CST_CONFIG_CONTROL\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 2:0] Package C-State Limit (R/W)  Specifies the lowest\r
    /// processor-specific C-state code name (consuming the least power). for\r
    /// the package. The default is set as factory-configured package C-state\r
    /// limit. The following C-state code name encodings are supported: 000b:\r
    /// C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b)\r
    /// 010b: C3 011b: C6 100b: C7 101b and 110b: Reserved 111: No package\r
    /// C-state limit. Note: This field cannot be used to limit package\r
    /// C-state to C3.\r
    ///\r
    UINT32    Limit              : 3;\r
    UINT32    Reserved1          : 7;\r
    ///\r
    /// [Bit 10] I/O MWAIT Redirection Enable (R/W)  When set, will map\r
    /// IO_read instructions sent to IO register specified by\r
    /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r
    ///\r
    UINT32    IO_MWAIT           : 1;\r
    UINT32    Reserved2          : 4;\r
    ///\r
    /// [Bit 15] CFG Lock (R/WO)  When set, lock bits 15:0 of this register\r
    /// until next reset.\r
    ///\r
    UINT32    CFGLock            : 1;\r
    UINT32    Reserved3          : 8;\r
    ///\r
    /// [Bit 24] Interrupt filtering enable (R/W)  When set, processor cores\r
    /// in a deep C-State will wake only when the event message is destined\r
    /// for that core. When 0, all processor cores in a deep C-State will wake\r
    /// for an event message.\r
    ///\r
    UINT32    InterruptFiltering : 1;\r
    ///\r
    /// [Bit 25] C3 state auto demotion enable (R/W)  When set, the processor\r
    /// will conditionally demote C6/C7 requests to C3 based on uncore\r
    /// auto-demote information.\r
    ///\r
    UINT32    C3AutoDemotion     : 1;\r
    ///\r
    /// [Bit 26] C1 state auto demotion enable (R/W)  When set, the processor\r
    /// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r
    /// auto-demote information.\r
    ///\r
    UINT32    C1AutoDemotion     : 1;\r
    ///\r
    /// [Bit 27] Enable C3 Undemotion (R/W).\r
    ///\r
    UINT32    C3Undemotion       : 1;\r
    ///\r
    /// [Bit 28] Enable C1 Undemotion (R/W).\r
    ///\r
    UINT32    C1Undemotion       : 1;\r
    ///\r
    /// [Bit 29] Package C State Demotion Enable (R/W).\r
    ///\r
    UINT32    CStateDemotion     : 1;\r
    ///\r
    /// [Bit 30] Package C State UnDemotion Enable (R/W).\r
    ///\r
    UINT32    CStateUndemotion   : 1;\r
    UINT32    Reserved4          : 1;\r
    UINT32    Reserved5          : 32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64    Uint64;\r
} MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER;\r
\r
/**\r
  Core. Power Management IO Redirection in C-state (R/W) See\r
  http://biosbits.org.\r
\r
  @param  ECX  MSR_NEHALEM_PMG_IO_CAPTURE_BASE (0x000000E4)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE);\r
  AsmWriteMsr64 (MSR_NEHALEM_PMG_IO_CAPTURE_BASE, Msr.Uint64);\r
  @endcode\r
  @note MSR_NEHALEM_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.\r
**/\r
#define MSR_NEHALEM_PMG_IO_CAPTURE_BASE  0x000000E4\r
\r
/**\r
  MSR information returned for MSR index #MSR_NEHALEM_PMG_IO_CAPTURE_BASE\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 15:0] LVL_2 Base Address (R/W)  Specifies the base address\r
    /// visible to software for IO redirection. If IO MWAIT Redirection is\r
    /// enabled, reads to this address will be consumed by the power\r
    /// management logic and decoded to MWAIT instructions. When IO port\r
    /// address redirection is enabled, this is the IO port address reported\r
    /// to the OS/software.\r
    ///\r
    UINT32    Lvl2Base    : 16;\r
    ///\r
    /// [Bits 18:16] C-state Range (R/W)  Specifies the encoding value of the\r
    /// maximum C-State code name to be included when IO read to MWAIT\r
    /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3\r
    /// is the max C-State to include 001b - C6 is the max C-State to include\r
    /// 010b - C7 is the max C-State to include.\r
    ///\r
    UINT32    CStateRange : 3;\r
    UINT32    Reserved1   : 13;\r
    UINT32    Reserved2   : 32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64    Uint64;\r
} MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER;\r
\r
/**\r
  Enable Misc. Processor Features (R/W)  Allows a variety of processor\r
  functions to be enabled and disabled.\r
\r
  @param  ECX  MSR_NEHALEM_IA32_MISC_ENABLE (0x000001A0)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE);\r
  AsmWriteMsr64 (MSR_NEHALEM_IA32_MISC_ENABLE, Msr.Uint64);\r
  @endcode\r
  @note MSR_NEHALEM_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
**/\r
#define MSR_NEHALEM_IA32_MISC_ENABLE  0x000001A0\r
\r
/**\r
  MSR information returned for MSR index #MSR_NEHALEM_IA32_MISC_ENABLE\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Thread. Fast-Strings Enable See Table 2-2.\r
    ///\r
    UINT32    FastStrings                    : 1;\r
    UINT32    Reserved1                      : 2;\r
    ///\r
    /// [Bit 3] Thread. Automatic Thermal Control Circuit Enable (R/W) See\r
    /// Table 2-2. Default value is 1.\r
    ///\r
    UINT32    AutomaticThermalControlCircuit : 1;\r
    UINT32    Reserved2                      : 3;\r
    ///\r
    /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2.\r
    ///\r
    UINT32    PerformanceMonitoring          : 1;\r
    UINT32    Reserved3                      : 3;\r
    ///\r
    /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2.\r
    ///\r
    UINT32    BTS                            : 1;\r
    ///\r
    /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See\r
    /// Table 2-2.\r
    ///\r
    UINT32    PEBS                           : 1;\r
    UINT32    Reserved4                      : 3;\r
    ///\r
    /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
    /// Table 2-2.\r
    ///\r
    UINT32    EIST                           : 1;\r
    UINT32    Reserved5                      : 1;\r
    ///\r
    /// [Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 2-2.\r
    ///\r
    UINT32    MONITOR                        : 1;\r
    UINT32    Reserved6                      : 3;\r
    ///\r
    /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2.\r
    ///\r
    UINT32    LimitCpuidMaxval               : 1;\r
    ///\r
    /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2.\r
    ///\r
    UINT32    xTPR_Message_Disable           : 1;\r
    UINT32    Reserved7                      : 8;\r
    UINT32    Reserved8                      : 2;\r
    ///\r
    /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2.\r
    ///\r
    UINT32    XD                             : 1;\r
    UINT32    Reserved9                      : 3;\r
    ///\r
    /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors\r
    /// that support Intel Turbo Boost Technology, the turbo mode feature is\r
    /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:\r
    /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:\r
    /// EAX[1] reports the processor's support of turbo mode is enabled. Note:\r
    /// the power-on default value is used by BIOS to detect hardware support\r
    /// of turbo mode. If power-on default value is 1, turbo mode is available\r
    /// in the processor. If power-on default value is 0, turbo mode is not\r
    /// available.\r
    ///\r
    UINT32    TurboModeDisable : 1;\r
    UINT32    Reserved10       : 25;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64    Uint64;\r
} MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER;\r
\r
/**\r
  Thread.\r
\r
  @param  ECX  MSR_NEHALEM_TEMPERATURE_TARGET (0x000001A2)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET);\r
  AsmWriteMsr64 (MSR_NEHALEM_TEMPERATURE_TARGET, Msr.Uint64);\r
  @endcode\r
  @note MSR_NEHALEM_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
**/\r
#define MSR_NEHALEM_TEMPERATURE_TARGET  0x000001A2\r
\r
/**\r
  MSR information returned for MSR index #MSR_NEHALEM_TEMPERATURE_TARGET\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    UINT32    Reserved1         : 16;\r
    ///\r
    /// [Bits 23:16] Temperature Target (R)  The minimum temperature at which\r
    /// PROCHOT# will be asserted. The value is degree C.\r
    ///\r
    UINT32    TemperatureTarget : 8;\r
    UINT32    Reserved2         : 8;\r
    UINT32    Reserved3         : 32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64    Uint64;\r
} MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER;\r
\r
/**\r
  Miscellaneous Feature Control (R/W).\r
\r
  @param  ECX  MSR_NEHALEM_MISC_FEATURE_CONTROL (0x000001A4)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL);\r
  AsmWriteMsr64 (MSR_NEHALEM_MISC_FEATURE_CONTROL, Msr.Uint64);\r
  @endcode\r
  @note MSR_NEHALEM_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r
**/\r
#define MSR_NEHALEM_MISC_FEATURE_CONTROL  0x000001A4\r
\r
/**\r
  MSR information returned for MSR index #MSR_NEHALEM_MISC_FEATURE_CONTROL\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W)  If 1, disables the\r
    /// L2 hardware prefetcher, which fetches additional lines of code or data\r
    /// into the L2 cache.\r
    ///\r
    UINT32    L2HardwarePrefetcherDisable          : 1;\r
    ///\r
    /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W)  If 1,\r
    /// disables the adjacent cache line prefetcher, which fetches the cache\r
    /// line that comprises a cache line pair (128 bytes).\r
    ///\r
    UINT32    L2AdjacentCacheLinePrefetcherDisable : 1;\r
    ///\r
    /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W)  If 1, disables\r
    /// the L1 data cache prefetcher, which fetches the next cache line into\r
    /// L1 data cache.\r
    ///\r
    UINT32    DCUHardwarePrefetcherDisable         : 1;\r
    ///\r
    /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W)  If 1, disables the L1\r
    /// data cache IP prefetcher, which uses sequential load history (based on\r
    /// instruction Pointer of previous loads) to determine whether to\r
    /// prefetch additional lines.\r
    ///\r
    UINT32    DCUIPPrefetcherDisable               : 1;\r
    UINT32    Reserved1                            : 28;\r
    UINT32    Reserved2                            : 32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64    Uint64;\r
} MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER;\r
\r
/**\r
  Thread. Offcore Response Event Select Register (R/W).\r
\r
  @param  ECX  MSR_NEHALEM_OFFCORE_RSP_0 (0x000001A6)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_OFFCORE_RSP_0);\r
  AsmWriteMsr64 (MSR_NEHALEM_OFFCORE_RSP_0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.\r
**/\r
#define MSR_NEHALEM_OFFCORE_RSP_0  0x000001A6\r
\r
/**\r
  See http://biosbits.org.\r
\r
  @param  ECX  MSR_NEHALEM_MISC_PWR_MGMT (0x000001AA)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_MISC_PWR_MGMT_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_NEHALEM_MISC_PWR_MGMT_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_MISC_PWR_MGMT);\r
  AsmWriteMsr64 (MSR_NEHALEM_MISC_PWR_MGMT, Msr.Uint64);\r
  @endcode\r
  @note MSR_NEHALEM_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.\r
**/\r
#define MSR_NEHALEM_MISC_PWR_MGMT  0x000001AA\r
\r
/**\r
  MSR information returned for MSR index #MSR_NEHALEM_MISC_PWR_MGMT\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Package. EIST Hardware Coordination Disable (R/W) When 0,\r
    /// enables hardware coordination of Enhanced Intel Speedstep Technology\r
    /// request from processor cores; When 1, disables hardware coordination\r
    /// of Enhanced Intel Speedstep Technology requests.\r
    ///\r
    UINT32    EISTHardwareCoordinationDisable : 1;\r
    ///\r
    /// [Bit 1] Thread. Energy/Performance Bias Enable (R/W)  This bit makes\r
    /// the IA32_ENERGY_PERF_BIAS register (MSR 1B0h) visible to software with\r
    /// Ring 0 privileges. This bit's status (1 or 0) is also reflected by\r
    /// CPUID.(EAX=06h):ECX[3].\r
    ///\r
    UINT32    EnergyPerformanceBiasEnable     : 1;\r
    UINT32    Reserved1                       : 30;\r
    UINT32    Reserved2                       : 32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64    Uint64;\r
} MSR_NEHALEM_MISC_PWR_MGMT_REGISTER;\r
\r
/**\r
  See http://biosbits.org.\r
\r
  @param  ECX  MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT (0x000001AC)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT);\r
  AsmWriteMsr64 (MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT, Msr.Uint64);\r
  @endcode\r
  @note MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT is defined as MSR_TURBO_POWER_CURRENT_LIMIT in SDM.\r
**/\r
#define MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT  0x000001AC\r
\r
/**\r
  MSR information returned for MSR index #MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 14:0] Package. TDP Limit (R/W)  TDP limit in 1/8 Watt\r
    /// granularity.\r
    ///\r
    UINT32    TDPLimit               : 15;\r
    ///\r
    /// [Bit 15] Package. TDP Limit Override Enable (R/W)  A value = 0\r
    /// indicates override is not active, and a value = 1 indicates active.\r
    ///\r
    UINT32    TDPLimitOverrideEnable : 1;\r
    ///\r
    /// [Bits 30:16] Package. TDC Limit (R/W)  TDC limit in 1/8 Amp\r
    /// granularity.\r
    ///\r
    UINT32    TDCLimit               : 15;\r
    ///\r
    /// [Bit 31] Package. TDC Limit Override Enable (R/W)  A value = 0\r
    /// indicates override is not active, and a value = 1 indicates active.\r
    ///\r
    UINT32    TDCLimitOverrideEnable : 1;\r
    UINT32    Reserved               : 32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64    Uint64;\r
} MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER;\r
\r
/**\r
  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
  RW if MSR_PLATFORM_INFO.[28] = 1.\r
\r
  @param  ECX  MSR_NEHALEM_TURBO_RATIO_LIMIT (0x000001AD)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_TURBO_RATIO_LIMIT);\r
  @endcode\r
  @note MSR_NEHALEM_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
#define MSR_NEHALEM_TURBO_RATIO_LIMIT  0x000001AD\r
\r
/**\r
  MSR information returned for MSR index #MSR_NEHALEM_TURBO_RATIO_LIMIT\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
    /// limit of 1 core active.\r
    ///\r
    UINT32    Maximum1C : 8;\r
    ///\r
    /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
    /// limit of 2 core active.\r
    ///\r
    UINT32    Maximum2C : 8;\r
    ///\r
    /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
    /// limit of 3 core active.\r
    ///\r
    UINT32    Maximum3C : 8;\r
    ///\r
    /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
    /// limit of 4 core active.\r
    ///\r
    UINT32    Maximum4C : 8;\r
    UINT32    Reserved  : 32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64    Uint64;\r
} MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER;\r
\r
/**\r
  Core. Last Branch Record Filtering Select Register (R/W) See Section 17.9.2,\r
  "Filtering of Last Branch Records.".\r
\r
  @param  ECX  MSR_NEHALEM_LBR_SELECT (0x000001C8)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_LBR_SELECT_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_NEHALEM_LBR_SELECT_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_LBR_SELECT);\r
  AsmWriteMsr64 (MSR_NEHALEM_LBR_SELECT, Msr.Uint64);\r
  @endcode\r
  @note MSR_NEHALEM_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r
**/\r
#define MSR_NEHALEM_LBR_SELECT  0x000001C8\r
\r
/**\r
  MSR information returned for MSR index #MSR_NEHALEM_LBR_SELECT\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] CPL_EQ_0.\r
    ///\r
    UINT32    CPL_EQ_0      : 1;\r
    ///\r
    /// [Bit 1] CPL_NEQ_0.\r
    ///\r
    UINT32    CPL_NEQ_0     : 1;\r
    ///\r
    /// [Bit 2] JCC.\r
    ///\r
    UINT32    JCC           : 1;\r
    ///\r
    /// [Bit 3] NEAR_REL_CALL.\r
    ///\r
    UINT32    NEAR_REL_CALL : 1;\r
    ///\r
    /// [Bit 4] NEAR_IND_CALL.\r
    ///\r
    UINT32    NEAR_IND_CALL : 1;\r
    ///\r
    /// [Bit 5] NEAR_RET.\r
    ///\r
    UINT32    NEAR_RET      : 1;\r
    ///\r
    /// [Bit 6] NEAR_IND_JMP.\r
    ///\r
    UINT32    NEAR_IND_JMP  : 1;\r
    ///\r
    /// [Bit 7] NEAR_REL_JMP.\r
    ///\r
    UINT32    NEAR_REL_JMP  : 1;\r
    ///\r
    /// [Bit 8] FAR_BRANCH.\r
    ///\r
    UINT32    FAR_BRANCH    : 1;\r
    UINT32    Reserved1     : 23;\r
    UINT32    Reserved2     : 32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64    Uint64;\r
} MSR_NEHALEM_LBR_SELECT_REGISTER;\r
\r
/**\r
  Thread. Last Branch Record Stack TOS (R/W)  Contains an index (bits 0-3)\r
  that points to the MSR containing the most recent branch record. See\r
  MSR_LASTBRANCH_0_FROM_IP (at 680H).\r
\r
  @param  ECX  MSR_NEHALEM_LASTBRANCH_TOS (0x000001C9)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_TOS);\r
  AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_TOS, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
**/\r
#define MSR_NEHALEM_LASTBRANCH_TOS  0x000001C9\r
\r
/**\r
  Thread. Last Exception Record From Linear IP (R)  Contains a pointer to the\r
  last branch instruction that the processor executed prior to the last\r
  exception that was generated or the last interrupt that was handled.\r
\r
  @param  ECX  MSR_NEHALEM_LER_FROM_LIP (0x000001DD)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_LER_FROM_LIP);\r
  @endcode\r
  @note MSR_NEHALEM_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
**/\r
#define MSR_NEHALEM_LER_FROM_LIP  0x000001DD\r
\r
/**\r
  Thread. Last Exception Record To Linear IP (R)  This area contains a pointer\r
  to the target of the last branch instruction that the processor executed\r
  prior to the last exception that was generated or the last interrupt that\r
  was handled.\r
\r
  @param  ECX  MSR_NEHALEM_LER_TO_LIP (0x000001DE)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_LER_TO_LIP);\r
  @endcode\r
  @note MSR_NEHALEM_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
**/\r
#define MSR_NEHALEM_LER_TO_LIP  0x000001DE\r
\r
/**\r
  Core. Power Control Register. See http://biosbits.org.\r
\r
  @param  ECX  MSR_NEHALEM_POWER_CTL (0x000001FC)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_POWER_CTL_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_NEHALEM_POWER_CTL_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_POWER_CTL);\r
  AsmWriteMsr64 (MSR_NEHALEM_POWER_CTL, Msr.Uint64);\r
  @endcode\r
  @note MSR_NEHALEM_POWER_CTL is defined as MSR_POWER_CTL in SDM.\r
**/\r
#define MSR_NEHALEM_POWER_CTL  0x000001FC\r
\r
/**\r
  MSR information returned for MSR index #MSR_NEHALEM_POWER_CTL\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    UINT32    Reserved1 : 1;\r
    ///\r
    /// [Bit 1] Package. C1E Enable (R/W)  When set to '1', will enable the\r
    /// CPU to switch to the Minimum Enhanced Intel SpeedStep Technology\r
    /// operating point when all execution cores enter MWAIT (C1).\r
    ///\r
    UINT32    C1EEnable : 1;\r
    UINT32    Reserved2 : 30;\r
    UINT32    Reserved3 : 32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64    Uint64;\r
} MSR_NEHALEM_POWER_CTL_REGISTER;\r
\r
/**\r
  Thread. (RO).\r
\r
  @param  ECX  MSR_NEHALEM_PERF_GLOBAL_STATUS (0x0000038E)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_STATUS);\r
  @endcode\r
  @note MSR_NEHALEM_PERF_GLOBAL_STATUS is defined as MSR_PERF_GLOBAL_STATUS in SDM.\r
**/\r
#define MSR_NEHALEM_PERF_GLOBAL_STATUS  0x0000038E\r
\r
/**\r
  MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_STATUS\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    UINT32    Reserved1  : 32;\r
    UINT32    Reserved2  : 29;\r
    ///\r
    /// [Bit 61] UNC_Ovf Uncore overflowed if 1.\r
    ///\r
    UINT32    Ovf_Uncore : 1;\r
    UINT32    Reserved3  : 2;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64    Uint64;\r
} MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER;\r
\r
/**\r
  Thread. (R/W).\r
\r
  @param  ECX  MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL (0x00000390)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);\r
  @endcode\r
  @note MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL is defined as MSR_PERF_GLOBAL_OVF_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL  0x00000390\r
\r
/**\r
  MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    UINT32    Reserved1  : 32;\r
    UINT32    Reserved2  : 29;\r
    ///\r
    /// [Bit 61] CLR_UNC_Ovf Set 1 to clear UNC_Ovf.\r
    ///\r
    UINT32    Ovf_Uncore : 1;\r
    UINT32    Reserved3  : 2;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64    Uint64;\r
} MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER;\r
\r
/**\r
  Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".\r
\r
  @param  ECX  MSR_NEHALEM_PEBS_ENABLE (0x000003F1)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_PEBS_ENABLE_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_NEHALEM_PEBS_ENABLE_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_ENABLE);\r
  AsmWriteMsr64 (MSR_NEHALEM_PEBS_ENABLE, Msr.Uint64);\r
  @endcode\r
  @note MSR_NEHALEM_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r
**/\r
#define MSR_NEHALEM_PEBS_ENABLE  0x000003F1\r
\r
/**\r
  MSR information returned for MSR index #MSR_NEHALEM_PEBS_ENABLE\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
    ///\r
    UINT32    PEBS_EN_PMC0 : 1;\r
    ///\r
    /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).\r
    ///\r
    UINT32    PEBS_EN_PMC1 : 1;\r
    ///\r
    /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).\r
    ///\r
    UINT32    PEBS_EN_PMC2 : 1;\r
    ///\r
    /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).\r
    ///\r
    UINT32    PEBS_EN_PMC3 : 1;\r
    UINT32    Reserved1    : 28;\r
    ///\r
    /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).\r
    ///\r
    UINT32    LL_EN_PMC0   : 1;\r
    ///\r
    /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).\r
    ///\r
    UINT32    LL_EN_PMC1   : 1;\r
    ///\r
    /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).\r
    ///\r
    UINT32    LL_EN_PMC2   : 1;\r
    ///\r
    /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).\r
    ///\r
    UINT32    LL_EN_PMC3   : 1;\r
    UINT32    Reserved2    : 28;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64    Uint64;\r
} MSR_NEHALEM_PEBS_ENABLE_REGISTER;\r
\r
/**\r
  Thread. See Section 18.3.1.1.2, "Load Latency Performance Monitoring\r
  Facility.".\r
\r
  @param  ECX  MSR_NEHALEM_PEBS_LD_LAT (0x000003F6)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_PEBS_LD_LAT_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_NEHALEM_PEBS_LD_LAT_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_PEBS_LD_LAT);\r
  AsmWriteMsr64 (MSR_NEHALEM_PEBS_LD_LAT, Msr.Uint64);\r
  @endcode\r
  @note MSR_NEHALEM_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM.\r
**/\r
#define MSR_NEHALEM_PEBS_LD_LAT  0x000003F6\r
\r
/**\r
  MSR information returned for MSR index #MSR_NEHALEM_PEBS_LD_LAT\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 15:0] Minimum threshold latency value of tagged load operation\r
    /// that will be counted. (R/W).\r
    ///\r
    UINT32    MinimumThreshold : 16;\r
    UINT32    Reserved1        : 16;\r
    UINT32    Reserved2        : 32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64    Uint64;\r
} MSR_NEHALEM_PEBS_LD_LAT_REGISTER;\r
\r
/**\r
  Package. Note: C-state values are processor specific C-state code names,\r
  unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3\r
  Residency Counter. (R/O) Value since last reset that this package is in\r
  processor-specific C3 states. Count at the same frequency as the TSC.\r
\r
  @param  ECX  MSR_NEHALEM_PKG_C3_RESIDENCY (0x000003F8)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY);\r
  AsmWriteMsr64 (MSR_NEHALEM_PKG_C3_RESIDENCY, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.\r
**/\r
#define MSR_NEHALEM_PKG_C3_RESIDENCY  0x000003F8\r
\r
/**\r
  Package. Note: C-state values are processor specific C-state code names,\r
  unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6\r
  Residency Counter. (R/O) Value since last reset that this package is in\r
  processor-specific C6 states. Count at the same frequency as the TSC.\r
\r
  @param  ECX  MSR_NEHALEM_PKG_C6_RESIDENCY (0x000003F9)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY);\r
  AsmWriteMsr64 (MSR_NEHALEM_PKG_C6_RESIDENCY, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r
**/\r
#define MSR_NEHALEM_PKG_C6_RESIDENCY  0x000003F9\r
\r
/**\r
  Package. Note: C-state values are processor specific C-state code names,\r
  unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7\r
  Residency Counter. (R/O) Value since last reset that this package is in\r
  processor-specific C7 states. Count at the same frequency as the TSC.\r
\r
  @param  ECX  MSR_NEHALEM_PKG_C7_RESIDENCY (0x000003FA)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY);\r
  AsmWriteMsr64 (MSR_NEHALEM_PKG_C7_RESIDENCY, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.\r
**/\r
#define MSR_NEHALEM_PKG_C7_RESIDENCY  0x000003FA\r
\r
/**\r
  Core. Note: C-state values are processor specific C-state code names,\r
  unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3\r
  Residency Counter. (R/O) Value since last reset that this core is in\r
  processor-specific C3 states. Count at the same frequency as the TSC.\r
\r
  @param  ECX  MSR_NEHALEM_CORE_C3_RESIDENCY (0x000003FC)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY);\r
  AsmWriteMsr64 (MSR_NEHALEM_CORE_C3_RESIDENCY, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.\r
**/\r
#define MSR_NEHALEM_CORE_C3_RESIDENCY  0x000003FC\r
\r
/**\r
  Core. Note: C-state values are processor specific C-state code names,\r
  unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6\r
  Residency Counter. (R/O) Value since last reset that this core is in\r
  processor-specific C6 states. Count at the same frequency as the TSC.\r
\r
  @param  ECX  MSR_NEHALEM_CORE_C6_RESIDENCY (0x000003FD)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY);\r
  AsmWriteMsr64 (MSR_NEHALEM_CORE_C6_RESIDENCY, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.\r
**/\r
#define MSR_NEHALEM_CORE_C6_RESIDENCY  0x000003FD\r
\r
/**\r
  Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last\r
  branch record registers on the last branch record stack. The From_IP part of\r
  the stack contains pointers to the source instruction. See also: -  Last\r
  Branch Record Stack TOS at 1C9H -  Section 17.7.1 and record format in\r
  Section 17.4.8.1.\r
\r
  @param  ECX  MSR_NEHALEM_LASTBRANCH_n_FROM_IP\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP);\r
  AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_FROM_IP, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_LASTBRANCH_0_FROM_IP  is defined as MSR_LASTBRANCH_0_FROM_IP  in SDM.\r
        MSR_NEHALEM_LASTBRANCH_1_FROM_IP  is defined as MSR_LASTBRANCH_1_FROM_IP  in SDM.\r
        MSR_NEHALEM_LASTBRANCH_2_FROM_IP  is defined as MSR_LASTBRANCH_2_FROM_IP  in SDM.\r
        MSR_NEHALEM_LASTBRANCH_3_FROM_IP  is defined as MSR_LASTBRANCH_3_FROM_IP  in SDM.\r
        MSR_NEHALEM_LASTBRANCH_4_FROM_IP  is defined as MSR_LASTBRANCH_4_FROM_IP  in SDM.\r
        MSR_NEHALEM_LASTBRANCH_5_FROM_IP  is defined as MSR_LASTBRANCH_5_FROM_IP  in SDM.\r
        MSR_NEHALEM_LASTBRANCH_6_FROM_IP  is defined as MSR_LASTBRANCH_6_FROM_IP  in SDM.\r
        MSR_NEHALEM_LASTBRANCH_7_FROM_IP  is defined as MSR_LASTBRANCH_7_FROM_IP  in SDM.\r
        MSR_NEHALEM_LASTBRANCH_8_FROM_IP  is defined as MSR_LASTBRANCH_8_FROM_IP  in SDM.\r
        MSR_NEHALEM_LASTBRANCH_9_FROM_IP  is defined as MSR_LASTBRANCH_9_FROM_IP  in SDM.\r
        MSR_NEHALEM_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.\r
        MSR_NEHALEM_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.\r
        MSR_NEHALEM_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.\r
        MSR_NEHALEM_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.\r
        MSR_NEHALEM_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.\r
        MSR_NEHALEM_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.\r
  @{\r
**/\r
#define MSR_NEHALEM_LASTBRANCH_0_FROM_IP   0x00000680\r
#define MSR_NEHALEM_LASTBRANCH_1_FROM_IP   0x00000681\r
#define MSR_NEHALEM_LASTBRANCH_2_FROM_IP   0x00000682\r
#define MSR_NEHALEM_LASTBRANCH_3_FROM_IP   0x00000683\r
#define MSR_NEHALEM_LASTBRANCH_4_FROM_IP   0x00000684\r
#define MSR_NEHALEM_LASTBRANCH_5_FROM_IP   0x00000685\r
#define MSR_NEHALEM_LASTBRANCH_6_FROM_IP   0x00000686\r
#define MSR_NEHALEM_LASTBRANCH_7_FROM_IP   0x00000687\r
#define MSR_NEHALEM_LASTBRANCH_8_FROM_IP   0x00000688\r
#define MSR_NEHALEM_LASTBRANCH_9_FROM_IP   0x00000689\r
#define MSR_NEHALEM_LASTBRANCH_10_FROM_IP  0x0000068A\r
#define MSR_NEHALEM_LASTBRANCH_11_FROM_IP  0x0000068B\r
#define MSR_NEHALEM_LASTBRANCH_12_FROM_IP  0x0000068C\r
#define MSR_NEHALEM_LASTBRANCH_13_FROM_IP  0x0000068D\r
#define MSR_NEHALEM_LASTBRANCH_14_FROM_IP  0x0000068E\r
#define MSR_NEHALEM_LASTBRANCH_15_FROM_IP  0x0000068F\r
/// @}\r
\r
/**\r
  Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch\r
  record registers on the last branch record stack. This part of the stack\r
  contains pointers to the destination instruction.\r
\r
  @param  ECX  MSR_NEHALEM_LASTBRANCH_n_TO_IP\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP);\r
  AsmWriteMsr64 (MSR_NEHALEM_LASTBRANCH_0_TO_IP, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_LASTBRANCH_0_TO_IP  is defined as MSR_LASTBRANCH_0_TO_IP  in SDM.\r
        MSR_NEHALEM_LASTBRANCH_1_TO_IP  is defined as MSR_LASTBRANCH_1_TO_IP  in SDM.\r
        MSR_NEHALEM_LASTBRANCH_2_TO_IP  is defined as MSR_LASTBRANCH_2_TO_IP  in SDM.\r
        MSR_NEHALEM_LASTBRANCH_3_TO_IP  is defined as MSR_LASTBRANCH_3_TO_IP  in SDM.\r
        MSR_NEHALEM_LASTBRANCH_4_TO_IP  is defined as MSR_LASTBRANCH_4_TO_IP  in SDM.\r
        MSR_NEHALEM_LASTBRANCH_5_TO_IP  is defined as MSR_LASTBRANCH_5_TO_IP  in SDM.\r
        MSR_NEHALEM_LASTBRANCH_6_TO_IP  is defined as MSR_LASTBRANCH_6_TO_IP  in SDM.\r
        MSR_NEHALEM_LASTBRANCH_7_TO_IP  is defined as MSR_LASTBRANCH_7_TO_IP  in SDM.\r
        MSR_NEHALEM_LASTBRANCH_8_TO_IP  is defined as MSR_LASTBRANCH_8_TO_IP  in SDM.\r
        MSR_NEHALEM_LASTBRANCH_9_TO_IP  is defined as MSR_LASTBRANCH_9_TO_IP  in SDM.\r
        MSR_NEHALEM_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.\r
        MSR_NEHALEM_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.\r
        MSR_NEHALEM_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.\r
        MSR_NEHALEM_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.\r
        MSR_NEHALEM_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.\r
        MSR_NEHALEM_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.\r
  @{\r
**/\r
#define MSR_NEHALEM_LASTBRANCH_0_TO_IP   0x000006C0\r
#define MSR_NEHALEM_LASTBRANCH_1_TO_IP   0x000006C1\r
#define MSR_NEHALEM_LASTBRANCH_2_TO_IP   0x000006C2\r
#define MSR_NEHALEM_LASTBRANCH_3_TO_IP   0x000006C3\r
#define MSR_NEHALEM_LASTBRANCH_4_TO_IP   0x000006C4\r
#define MSR_NEHALEM_LASTBRANCH_5_TO_IP   0x000006C5\r
#define MSR_NEHALEM_LASTBRANCH_6_TO_IP   0x000006C6\r
#define MSR_NEHALEM_LASTBRANCH_7_TO_IP   0x000006C7\r
#define MSR_NEHALEM_LASTBRANCH_8_TO_IP   0x000006C8\r
#define MSR_NEHALEM_LASTBRANCH_9_TO_IP   0x000006C9\r
#define MSR_NEHALEM_LASTBRANCH_10_TO_IP  0x000006CA\r
#define MSR_NEHALEM_LASTBRANCH_11_TO_IP  0x000006CB\r
#define MSR_NEHALEM_LASTBRANCH_12_TO_IP  0x000006CC\r
#define MSR_NEHALEM_LASTBRANCH_13_TO_IP  0x000006CD\r
#define MSR_NEHALEM_LASTBRANCH_14_TO_IP  0x000006CE\r
#define MSR_NEHALEM_LASTBRANCH_15_TO_IP  0x000006CF\r
/// @}\r
\r
/**\r
  Package.\r
\r
  @param  ECX  MSR_NEHALEM_GQ_SNOOP_MESF (0x00000301)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF);\r
  AsmWriteMsr64 (MSR_NEHALEM_GQ_SNOOP_MESF, Msr.Uint64);\r
  @endcode\r
  @note MSR_NEHALEM_GQ_SNOOP_MESF is defined as MSR_GQ_SNOOP_MESF in SDM.\r
**/\r
#define MSR_NEHALEM_GQ_SNOOP_MESF  0x00000301\r
\r
/**\r
  MSR information returned for MSR index #MSR_NEHALEM_GQ_SNOOP_MESF\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] From M to S (R/W).\r
    ///\r
    UINT32    FromMtoS  : 1;\r
    ///\r
    /// [Bit 1] From E to S (R/W).\r
    ///\r
    UINT32    FromEtoS  : 1;\r
    ///\r
    /// [Bit 2] From S to S (R/W).\r
    ///\r
    UINT32    FromStoS  : 1;\r
    ///\r
    /// [Bit 3] From F to S (R/W).\r
    ///\r
    UINT32    FromFtoS  : 1;\r
    ///\r
    /// [Bit 4] From M to I (R/W).\r
    ///\r
    UINT32    FromMtoI  : 1;\r
    ///\r
    /// [Bit 5] From E to I (R/W).\r
    ///\r
    UINT32    FromEtoI  : 1;\r
    ///\r
    /// [Bit 6] From S to I (R/W).\r
    ///\r
    UINT32    FromStoI  : 1;\r
    ///\r
    /// [Bit 7] From F to I (R/W).\r
    ///\r
    UINT32    FromFtoI  : 1;\r
    UINT32    Reserved1 : 24;\r
    UINT32    Reserved2 : 32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64    Uint64;\r
} MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER;\r
\r
/**\r
  Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management\r
  Facility.".\r
\r
  @param  ECX  MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL (0x00000391)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_CTRL  0x00000391\r
\r
/**\r
  Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management\r
  Facility.".\r
\r
  @param  ECX  MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS (0x00000392)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS);\r
  AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS is defined as MSR_UNCORE_PERF_GLOBAL_STATUS in SDM.\r
**/\r
#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_STATUS  0x00000392\r
\r
/**\r
  Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management\r
  Facility.".\r
\r
  @param  ECX  MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL (0x00000393)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL is defined as MSR_UNCORE_PERF_GLOBAL_OVF_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_UNCORE_PERF_GLOBAL_OVF_CTRL  0x00000393\r
\r
/**\r
  Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management\r
  Facility.".\r
\r
  @param  ECX  MSR_NEHALEM_UNCORE_FIXED_CTR0 (0x00000394)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0);\r
  AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_UNCORE_FIXED_CTR0 is defined as MSR_UNCORE_FIXED_CTR0 in SDM.\r
**/\r
#define MSR_NEHALEM_UNCORE_FIXED_CTR0  0x00000394\r
\r
/**\r
  Package. See Section 18.3.1.2.1, "Uncore Performance Monitoring Management\r
  Facility.".\r
\r
  @param  ECX  MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL (0x00000395)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL is defined as MSR_UNCORE_FIXED_CTR_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_UNCORE_FIXED_CTR_CTRL  0x00000395\r
\r
/**\r
  Package. See Section 18.3.1.2.3, "Uncore Address/Opcode Match MSR.".\r
\r
  @param  ECX  MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH (0x00000396)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH);\r
  AsmWriteMsr64 (MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH is defined as MSR_UNCORE_ADDR_OPCODE_MATCH in SDM.\r
**/\r
#define MSR_NEHALEM_UNCORE_ADDR_OPCODE_MATCH  0x00000396\r
\r
/**\r
  Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration\r
  Facility.".\r
\r
  @param  ECX  MSR_NEHALEM_UNCORE_PMCi\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PMC0);\r
  AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PMC0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_UNCORE_PMC0 is defined as MSR_UNCORE_PMC0 in SDM.\r
        MSR_NEHALEM_UNCORE_PMC1 is defined as MSR_UNCORE_PMC1 in SDM.\r
        MSR_NEHALEM_UNCORE_PMC2 is defined as MSR_UNCORE_PMC2 in SDM.\r
        MSR_NEHALEM_UNCORE_PMC3 is defined as MSR_UNCORE_PMC3 in SDM.\r
        MSR_NEHALEM_UNCORE_PMC4 is defined as MSR_UNCORE_PMC4 in SDM.\r
        MSR_NEHALEM_UNCORE_PMC5 is defined as MSR_UNCORE_PMC5 in SDM.\r
        MSR_NEHALEM_UNCORE_PMC6 is defined as MSR_UNCORE_PMC6 in SDM.\r
        MSR_NEHALEM_UNCORE_PMC7 is defined as MSR_UNCORE_PMC7 in SDM.\r
  @{\r
**/\r
#define MSR_NEHALEM_UNCORE_PMC0  0x000003B0\r
#define MSR_NEHALEM_UNCORE_PMC1  0x000003B1\r
#define MSR_NEHALEM_UNCORE_PMC2  0x000003B2\r
#define MSR_NEHALEM_UNCORE_PMC3  0x000003B3\r
#define MSR_NEHALEM_UNCORE_PMC4  0x000003B4\r
#define MSR_NEHALEM_UNCORE_PMC5  0x000003B5\r
#define MSR_NEHALEM_UNCORE_PMC6  0x000003B6\r
#define MSR_NEHALEM_UNCORE_PMC7  0x000003B7\r
/// @}\r
\r
/**\r
  Package. See Section 18.3.1.2.2, "Uncore Performance Event Configuration\r
  Facility.".\r
\r
  @param  ECX  MSR_NEHALEM_UNCORE_PERFEVTSELi\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0);\r
  AsmWriteMsr64 (MSR_NEHALEM_UNCORE_PERFEVTSEL0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_UNCORE_PERFEVTSEL0 is defined as MSR_UNCORE_PERFEVTSEL0 in SDM.\r
        MSR_NEHALEM_UNCORE_PERFEVTSEL1 is defined as MSR_UNCORE_PERFEVTSEL1 in SDM.\r
        MSR_NEHALEM_UNCORE_PERFEVTSEL2 is defined as MSR_UNCORE_PERFEVTSEL2 in SDM.\r
        MSR_NEHALEM_UNCORE_PERFEVTSEL3 is defined as MSR_UNCORE_PERFEVTSEL3 in SDM.\r
        MSR_NEHALEM_UNCORE_PERFEVTSEL4 is defined as MSR_UNCORE_PERFEVTSEL4 in SDM.\r
        MSR_NEHALEM_UNCORE_PERFEVTSEL5 is defined as MSR_UNCORE_PERFEVTSEL5 in SDM.\r
        MSR_NEHALEM_UNCORE_PERFEVTSEL6 is defined as MSR_UNCORE_PERFEVTSEL6 in SDM.\r
        MSR_NEHALEM_UNCORE_PERFEVTSEL7 is defined as MSR_UNCORE_PERFEVTSEL7 in SDM.\r
  @{\r
**/\r
#define MSR_NEHALEM_UNCORE_PERFEVTSEL0  0x000003C0\r
#define MSR_NEHALEM_UNCORE_PERFEVTSEL1  0x000003C1\r
#define MSR_NEHALEM_UNCORE_PERFEVTSEL2  0x000003C2\r
#define MSR_NEHALEM_UNCORE_PERFEVTSEL3  0x000003C3\r
#define MSR_NEHALEM_UNCORE_PERFEVTSEL4  0x000003C4\r
#define MSR_NEHALEM_UNCORE_PERFEVTSEL5  0x000003C5\r
#define MSR_NEHALEM_UNCORE_PERFEVTSEL6  0x000003C6\r
#define MSR_NEHALEM_UNCORE_PERFEVTSEL7  0x000003C7\r
/// @}\r
\r
/**\r
  Package. Uncore W-box perfmon fixed counter.\r
\r
  @param  ECX  MSR_NEHALEM_W_PMON_FIXED_CTR (0x00000394)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR);\r
  AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_W_PMON_FIXED_CTR is defined as MSR_W_PMON_FIXED_CTR in SDM.\r
**/\r
#define MSR_NEHALEM_W_PMON_FIXED_CTR  0x00000394\r
\r
/**\r
  Package. Uncore U-box perfmon fixed counter control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_W_PMON_FIXED_CTR_CTL (0x00000395)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL);\r
  AsmWriteMsr64 (MSR_NEHALEM_W_PMON_FIXED_CTR_CTL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_W_PMON_FIXED_CTR_CTL is defined as MSR_W_PMON_FIXED_CTR_CTL in SDM.\r
**/\r
#define MSR_NEHALEM_W_PMON_FIXED_CTR_CTL  0x00000395\r
\r
/**\r
  Package. Uncore U-box perfmon global control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_U_PMON_GLOBAL_CTRL (0x00000C00)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_U_PMON_GLOBAL_CTRL is defined as MSR_U_PMON_GLOBAL_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_U_PMON_GLOBAL_CTRL  0x00000C00\r
\r
/**\r
  Package. Uncore U-box perfmon global status MSR.\r
\r
  @param  ECX  MSR_NEHALEM_U_PMON_GLOBAL_STATUS (0x00000C01)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS);\r
  AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_STATUS, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_U_PMON_GLOBAL_STATUS is defined as MSR_U_PMON_GLOBAL_STATUS in SDM.\r
**/\r
#define MSR_NEHALEM_U_PMON_GLOBAL_STATUS  0x00000C01\r
\r
/**\r
  Package. Uncore U-box perfmon global overflow control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL (0x00000C02)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL is defined as MSR_U_PMON_GLOBAL_OVF_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_U_PMON_GLOBAL_OVF_CTRL  0x00000C02\r
\r
/**\r
  Package. Uncore U-box perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_U_PMON_EVNT_SEL (0x00000C10)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL);\r
  AsmWriteMsr64 (MSR_NEHALEM_U_PMON_EVNT_SEL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_U_PMON_EVNT_SEL is defined as MSR_U_PMON_EVNT_SEL in SDM.\r
**/\r
#define MSR_NEHALEM_U_PMON_EVNT_SEL  0x00000C10\r
\r
/**\r
  Package. Uncore U-box perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_U_PMON_CTR (0x00000C11)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_U_PMON_CTR);\r
  AsmWriteMsr64 (MSR_NEHALEM_U_PMON_CTR, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_U_PMON_CTR is defined as MSR_U_PMON_CTR in SDM.\r
**/\r
#define MSR_NEHALEM_U_PMON_CTR  0x00000C11\r
\r
/**\r
  Package. Uncore B-box 0 perfmon local box control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_B0_PMON_BOX_CTRL (0x00000C20)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_B0_PMON_BOX_CTRL is defined as MSR_B0_PMON_BOX_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_B0_PMON_BOX_CTRL  0x00000C20\r
\r
/**\r
  Package. Uncore B-box 0 perfmon local box status MSR.\r
\r
  @param  ECX  MSR_NEHALEM_B0_PMON_BOX_STATUS (0x00000C21)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS);\r
  AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_STATUS, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_B0_PMON_BOX_STATUS is defined as MSR_B0_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_NEHALEM_B0_PMON_BOX_STATUS  0x00000C21\r
\r
/**\r
  Package. Uncore B-box 0 perfmon local box overflow control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL (0x00000C22)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL is defined as MSR_B0_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_B0_PMON_BOX_OVF_CTRL  0x00000C22\r
\r
/**\r
  Package. Uncore B-box 0 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_B0_PMON_EVNT_SEL0 (0x00000C30)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0);\r
  AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_B0_PMON_EVNT_SEL0 is defined as MSR_B0_PMON_EVNT_SEL0 in SDM.\r
**/\r
#define MSR_NEHALEM_B0_PMON_EVNT_SEL0  0x00000C30\r
\r
/**\r
  Package. Uncore B-box 0 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_B0_PMON_CTR0 (0x00000C31)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR0);\r
  AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_B0_PMON_CTR0 is defined as MSR_B0_PMON_CTR0 in SDM.\r
**/\r
#define MSR_NEHALEM_B0_PMON_CTR0  0x00000C31\r
\r
/**\r
  Package. Uncore B-box 0 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_B0_PMON_EVNT_SEL1 (0x00000C32)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1);\r
  AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_B0_PMON_EVNT_SEL1 is defined as MSR_B0_PMON_EVNT_SEL1 in SDM.\r
**/\r
#define MSR_NEHALEM_B0_PMON_EVNT_SEL1  0x00000C32\r
\r
/**\r
  Package. Uncore B-box 0 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_B0_PMON_CTR1 (0x00000C33)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR1);\r
  AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_B0_PMON_CTR1 is defined as MSR_B0_PMON_CTR1 in SDM.\r
**/\r
#define MSR_NEHALEM_B0_PMON_CTR1  0x00000C33\r
\r
/**\r
  Package. Uncore B-box 0 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_B0_PMON_EVNT_SEL2 (0x00000C34)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2);\r
  AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_B0_PMON_EVNT_SEL2 is defined as MSR_B0_PMON_EVNT_SEL2 in SDM.\r
**/\r
#define MSR_NEHALEM_B0_PMON_EVNT_SEL2  0x00000C34\r
\r
/**\r
  Package. Uncore B-box 0 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_B0_PMON_CTR2 (0x00000C35)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR2);\r
  AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_B0_PMON_CTR2 is defined as MSR_B0_PMON_CTR2 in SDM.\r
**/\r
#define MSR_NEHALEM_B0_PMON_CTR2  0x00000C35\r
\r
/**\r
  Package. Uncore B-box 0 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_B0_PMON_EVNT_SEL3 (0x00000C36)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3);\r
  AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_EVNT_SEL3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_B0_PMON_EVNT_SEL3 is defined as MSR_B0_PMON_EVNT_SEL3 in SDM.\r
**/\r
#define MSR_NEHALEM_B0_PMON_EVNT_SEL3  0x00000C36\r
\r
/**\r
  Package. Uncore B-box 0 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_B0_PMON_CTR3 (0x00000C37)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_CTR3);\r
  AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_CTR3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_B0_PMON_CTR3 is defined as MSR_B0_PMON_CTR3 in SDM.\r
**/\r
#define MSR_NEHALEM_B0_PMON_CTR3  0x00000C37\r
\r
/**\r
  Package. Uncore S-box 0 perfmon local box control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_S0_PMON_BOX_CTRL (0x00000C40)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_S0_PMON_BOX_CTRL is defined as MSR_S0_PMON_BOX_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_S0_PMON_BOX_CTRL  0x00000C40\r
\r
/**\r
  Package. Uncore S-box 0 perfmon local box status MSR.\r
\r
  @param  ECX  MSR_NEHALEM_S0_PMON_BOX_STATUS (0x00000C41)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS);\r
  AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_STATUS, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_S0_PMON_BOX_STATUS is defined as MSR_S0_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_NEHALEM_S0_PMON_BOX_STATUS  0x00000C41\r
\r
/**\r
  Package. Uncore S-box 0 perfmon local box overflow control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL (0x00000C42)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL is defined as MSR_S0_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_S0_PMON_BOX_OVF_CTRL  0x00000C42\r
\r
/**\r
  Package. Uncore S-box 0 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_S0_PMON_EVNT_SEL0 (0x00000C50)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0);\r
  AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_S0_PMON_EVNT_SEL0 is defined as MSR_S0_PMON_EVNT_SEL0 in SDM.\r
**/\r
#define MSR_NEHALEM_S0_PMON_EVNT_SEL0  0x00000C50\r
\r
/**\r
  Package. Uncore S-box 0 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_S0_PMON_CTR0 (0x00000C51)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR0);\r
  AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_S0_PMON_CTR0 is defined as MSR_S0_PMON_CTR0 in SDM.\r
**/\r
#define MSR_NEHALEM_S0_PMON_CTR0  0x00000C51\r
\r
/**\r
  Package. Uncore S-box 0 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_S0_PMON_EVNT_SEL1 (0x00000C52)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1);\r
  AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_S0_PMON_EVNT_SEL1 is defined as MSR_S0_PMON_EVNT_SEL1 in SDM.\r
**/\r
#define MSR_NEHALEM_S0_PMON_EVNT_SEL1  0x00000C52\r
\r
/**\r
  Package. Uncore S-box 0 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_S0_PMON_CTR1 (0x00000C53)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR1);\r
  AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_S0_PMON_CTR1 is defined as MSR_S0_PMON_CTR1 in SDM.\r
**/\r
#define MSR_NEHALEM_S0_PMON_CTR1  0x00000C53\r
\r
/**\r
  Package. Uncore S-box 0 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_S0_PMON_EVNT_SEL2 (0x00000C54)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2);\r
  AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_S0_PMON_EVNT_SEL2 is defined as MSR_S0_PMON_EVNT_SEL2 in SDM.\r
**/\r
#define MSR_NEHALEM_S0_PMON_EVNT_SEL2  0x00000C54\r
\r
/**\r
  Package. Uncore S-box 0 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_S0_PMON_CTR2 (0x00000C55)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR2);\r
  AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_S0_PMON_CTR2 is defined as MSR_S0_PMON_CTR2 in SDM.\r
**/\r
#define MSR_NEHALEM_S0_PMON_CTR2  0x00000C55\r
\r
/**\r
  Package. Uncore S-box 0 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_S0_PMON_EVNT_SEL3 (0x00000C56)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3);\r
  AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_EVNT_SEL3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_S0_PMON_EVNT_SEL3 is defined as MSR_S0_PMON_EVNT_SEL3 in SDM.\r
**/\r
#define MSR_NEHALEM_S0_PMON_EVNT_SEL3  0x00000C56\r
\r
/**\r
  Package. Uncore S-box 0 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_S0_PMON_CTR3 (0x00000C57)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_CTR3);\r
  AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_CTR3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_S0_PMON_CTR3 is defined as MSR_S0_PMON_CTR3 in SDM.\r
**/\r
#define MSR_NEHALEM_S0_PMON_CTR3  0x00000C57\r
\r
/**\r
  Package. Uncore B-box 1 perfmon local box control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_B1_PMON_BOX_CTRL (0x00000C60)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_B1_PMON_BOX_CTRL is defined as MSR_B1_PMON_BOX_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_B1_PMON_BOX_CTRL  0x00000C60\r
\r
/**\r
  Package. Uncore B-box 1 perfmon local box status MSR.\r
\r
  @param  ECX  MSR_NEHALEM_B1_PMON_BOX_STATUS (0x00000C61)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS);\r
  AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_STATUS, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_B1_PMON_BOX_STATUS is defined as MSR_B1_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_NEHALEM_B1_PMON_BOX_STATUS  0x00000C61\r
\r
/**\r
  Package. Uncore B-box 1 perfmon local box overflow control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL (0x00000C62)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL is defined as MSR_B1_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_B1_PMON_BOX_OVF_CTRL  0x00000C62\r
\r
/**\r
  Package. Uncore B-box 1 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_B1_PMON_EVNT_SEL0 (0x00000C70)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0);\r
  AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_B1_PMON_EVNT_SEL0 is defined as MSR_B1_PMON_EVNT_SEL0 in SDM.\r
**/\r
#define MSR_NEHALEM_B1_PMON_EVNT_SEL0  0x00000C70\r
\r
/**\r
  Package. Uncore B-box 1 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_B1_PMON_CTR0 (0x00000C71)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR0);\r
  AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_B1_PMON_CTR0 is defined as MSR_B1_PMON_CTR0 in SDM.\r
**/\r
#define MSR_NEHALEM_B1_PMON_CTR0  0x00000C71\r
\r
/**\r
  Package. Uncore B-box 1 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_B1_PMON_EVNT_SEL1 (0x00000C72)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1);\r
  AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_B1_PMON_EVNT_SEL1 is defined as MSR_B1_PMON_EVNT_SEL1 in SDM.\r
**/\r
#define MSR_NEHALEM_B1_PMON_EVNT_SEL1  0x00000C72\r
\r
/**\r
  Package. Uncore B-box 1 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_B1_PMON_CTR1 (0x00000C73)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR1);\r
  AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_B1_PMON_CTR1 is defined as MSR_B1_PMON_CTR1 in SDM.\r
**/\r
#define MSR_NEHALEM_B1_PMON_CTR1  0x00000C73\r
\r
/**\r
  Package. Uncore B-box 1 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_B1_PMON_EVNT_SEL2 (0x00000C74)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2);\r
  AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_B1_PMON_EVNT_SEL2 is defined as MSR_B1_PMON_EVNT_SEL2 in SDM.\r
**/\r
#define MSR_NEHALEM_B1_PMON_EVNT_SEL2  0x00000C74\r
\r
/**\r
  Package. Uncore B-box 1 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_B1_PMON_CTR2 (0x00000C75)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR2);\r
  AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_B1_PMON_CTR2 is defined as MSR_B1_PMON_CTR2 in SDM.\r
**/\r
#define MSR_NEHALEM_B1_PMON_CTR2  0x00000C75\r
\r
/**\r
  Package. Uncore B-box 1vperfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_B1_PMON_EVNT_SEL3 (0x00000C76)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3);\r
  AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_EVNT_SEL3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_B1_PMON_EVNT_SEL3 is defined as MSR_B1_PMON_EVNT_SEL3 in SDM.\r
**/\r
#define MSR_NEHALEM_B1_PMON_EVNT_SEL3  0x00000C76\r
\r
/**\r
  Package. Uncore B-box 1 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_B1_PMON_CTR3 (0x00000C77)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_CTR3);\r
  AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_CTR3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_B1_PMON_CTR3 is defined as MSR_B1_PMON_CTR3 in SDM.\r
**/\r
#define MSR_NEHALEM_B1_PMON_CTR3  0x00000C77\r
\r
/**\r
  Package. Uncore W-box perfmon local box control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_W_PMON_BOX_CTRL (0x00000C80)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_W_PMON_BOX_CTRL is defined as MSR_W_PMON_BOX_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_W_PMON_BOX_CTRL  0x00000C80\r
\r
/**\r
  Package. Uncore W-box perfmon local box status MSR.\r
\r
  @param  ECX  MSR_NEHALEM_W_PMON_BOX_STATUS (0x00000C81)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS);\r
  AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_STATUS, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_W_PMON_BOX_STATUS is defined as MSR_W_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_NEHALEM_W_PMON_BOX_STATUS  0x00000C81\r
\r
/**\r
  Package. Uncore W-box perfmon local box overflow control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_W_PMON_BOX_OVF_CTRL (0x00000C82)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_W_PMON_BOX_OVF_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_W_PMON_BOX_OVF_CTRL is defined as MSR_W_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_W_PMON_BOX_OVF_CTRL  0x00000C82\r
\r
/**\r
  Package. Uncore W-box perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_W_PMON_EVNT_SEL0 (0x00000C90)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0);\r
  AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_W_PMON_EVNT_SEL0 is defined as MSR_W_PMON_EVNT_SEL0 in SDM.\r
**/\r
#define MSR_NEHALEM_W_PMON_EVNT_SEL0  0x00000C90\r
\r
/**\r
  Package. Uncore W-box perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_W_PMON_CTR0 (0x00000C91)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR0);\r
  AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_W_PMON_CTR0 is defined as MSR_W_PMON_CTR0 in SDM.\r
**/\r
#define MSR_NEHALEM_W_PMON_CTR0  0x00000C91\r
\r
/**\r
  Package. Uncore W-box perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_W_PMON_EVNT_SEL1 (0x00000C92)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1);\r
  AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_W_PMON_EVNT_SEL1 is defined as MSR_W_PMON_EVNT_SEL1 in SDM.\r
**/\r
#define MSR_NEHALEM_W_PMON_EVNT_SEL1  0x00000C92\r
\r
/**\r
  Package. Uncore W-box perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_W_PMON_CTR1 (0x00000C93)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR1);\r
  AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_W_PMON_CTR1 is defined as MSR_W_PMON_CTR1 in SDM.\r
**/\r
#define MSR_NEHALEM_W_PMON_CTR1  0x00000C93\r
\r
/**\r
  Package. Uncore W-box perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_W_PMON_EVNT_SEL2 (0x00000C94)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2);\r
  AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_W_PMON_EVNT_SEL2 is defined as MSR_W_PMON_EVNT_SEL2 in SDM.\r
**/\r
#define MSR_NEHALEM_W_PMON_EVNT_SEL2  0x00000C94\r
\r
/**\r
  Package. Uncore W-box perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_W_PMON_CTR2 (0x00000C95)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR2);\r
  AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_W_PMON_CTR2 is defined as MSR_W_PMON_CTR2 in SDM.\r
**/\r
#define MSR_NEHALEM_W_PMON_CTR2  0x00000C95\r
\r
/**\r
  Package. Uncore W-box perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_W_PMON_EVNT_SEL3 (0x00000C96)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3);\r
  AsmWriteMsr64 (MSR_NEHALEM_W_PMON_EVNT_SEL3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_W_PMON_EVNT_SEL3 is defined as MSR_W_PMON_EVNT_SEL3 in SDM.\r
**/\r
#define MSR_NEHALEM_W_PMON_EVNT_SEL3  0x00000C96\r
\r
/**\r
  Package. Uncore W-box perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_W_PMON_CTR3 (0x00000C97)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_W_PMON_CTR3);\r
  AsmWriteMsr64 (MSR_NEHALEM_W_PMON_CTR3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_W_PMON_CTR3 is defined as MSR_W_PMON_CTR3 in SDM.\r
**/\r
#define MSR_NEHALEM_W_PMON_CTR3  0x00000C97\r
\r
/**\r
  Package. Uncore M-box 0 perfmon local box control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M0_PMON_BOX_CTRL (0x00000CA0)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M0_PMON_BOX_CTRL is defined as MSR_M0_PMON_BOX_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_M0_PMON_BOX_CTRL  0x00000CA0\r
\r
/**\r
  Package. Uncore M-box 0 perfmon local box status MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M0_PMON_BOX_STATUS (0x00000CA1)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS);\r
  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_STATUS, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M0_PMON_BOX_STATUS is defined as MSR_M0_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_NEHALEM_M0_PMON_BOX_STATUS  0x00000CA1\r
\r
/**\r
  Package. Uncore M-box 0 perfmon local box overflow control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL (0x00000CA2)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL is defined as MSR_M0_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_M0_PMON_BOX_OVF_CTRL  0x00000CA2\r
\r
/**\r
  Package. Uncore M-box 0 perfmon time stamp unit select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M0_PMON_TIMESTAMP (0x00000CA4)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP);\r
  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_TIMESTAMP, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M0_PMON_TIMESTAMP is defined as MSR_M0_PMON_TIMESTAMP in SDM.\r
**/\r
#define MSR_NEHALEM_M0_PMON_TIMESTAMP  0x00000CA4\r
\r
/**\r
  Package. Uncore M-box 0 perfmon DSP unit select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M0_PMON_DSP (0x00000CA5)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_DSP);\r
  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_DSP, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M0_PMON_DSP is defined as MSR_M0_PMON_DSP in SDM.\r
**/\r
#define MSR_NEHALEM_M0_PMON_DSP  0x00000CA5\r
\r
/**\r
  Package. Uncore M-box 0 perfmon ISS unit select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M0_PMON_ISS (0x00000CA6)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ISS);\r
  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ISS, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M0_PMON_ISS is defined as MSR_M0_PMON_ISS in SDM.\r
**/\r
#define MSR_NEHALEM_M0_PMON_ISS  0x00000CA6\r
\r
/**\r
  Package. Uncore M-box 0 perfmon MAP unit select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M0_PMON_MAP (0x00000CA7)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MAP);\r
  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MAP, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M0_PMON_MAP is defined as MSR_M0_PMON_MAP in SDM.\r
**/\r
#define MSR_NEHALEM_M0_PMON_MAP  0x00000CA7\r
\r
/**\r
  Package. Uncore M-box 0 perfmon MIC THR select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M0_PMON_MSC_THR (0x00000CA8)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR);\r
  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MSC_THR, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M0_PMON_MSC_THR is defined as MSR_M0_PMON_MSC_THR in SDM.\r
**/\r
#define MSR_NEHALEM_M0_PMON_MSC_THR  0x00000CA8\r
\r
/**\r
  Package. Uncore M-box 0 perfmon PGT unit select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M0_PMON_PGT (0x00000CA9)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PGT);\r
  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PGT, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M0_PMON_PGT is defined as MSR_M0_PMON_PGT in SDM.\r
**/\r
#define MSR_NEHALEM_M0_PMON_PGT  0x00000CA9\r
\r
/**\r
  Package. Uncore M-box 0 perfmon PLD unit select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M0_PMON_PLD (0x00000CAA)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_PLD);\r
  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_PLD, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M0_PMON_PLD is defined as MSR_M0_PMON_PLD in SDM.\r
**/\r
#define MSR_NEHALEM_M0_PMON_PLD  0x00000CAA\r
\r
/**\r
  Package. Uncore M-box 0 perfmon ZDP unit select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M0_PMON_ZDP (0x00000CAB)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ZDP);\r
  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ZDP, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M0_PMON_ZDP is defined as MSR_M0_PMON_ZDP in SDM.\r
**/\r
#define MSR_NEHALEM_M0_PMON_ZDP  0x00000CAB\r
\r
/**\r
  Package. Uncore M-box 0 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M0_PMON_EVNT_SEL0 (0x00000CB0)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0);\r
  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M0_PMON_EVNT_SEL0 is defined as MSR_M0_PMON_EVNT_SEL0 in SDM.\r
**/\r
#define MSR_NEHALEM_M0_PMON_EVNT_SEL0  0x00000CB0\r
\r
/**\r
  Package. Uncore M-box 0 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M0_PMON_CTR0 (0x00000CB1)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR0);\r
  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M0_PMON_CTR0 is defined as MSR_M0_PMON_CTR0 in SDM.\r
**/\r
#define MSR_NEHALEM_M0_PMON_CTR0  0x00000CB1\r
\r
/**\r
  Package. Uncore M-box 0 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M0_PMON_EVNT_SEL1 (0x00000CB2)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1);\r
  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M0_PMON_EVNT_SEL1 is defined as MSR_M0_PMON_EVNT_SEL1 in SDM.\r
**/\r
#define MSR_NEHALEM_M0_PMON_EVNT_SEL1  0x00000CB2\r
\r
/**\r
  Package. Uncore M-box 0 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M0_PMON_CTR1 (0x00000CB3)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR1);\r
  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M0_PMON_CTR1 is defined as MSR_M0_PMON_CTR1 in SDM.\r
**/\r
#define MSR_NEHALEM_M0_PMON_CTR1  0x00000CB3\r
\r
/**\r
  Package. Uncore M-box 0 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M0_PMON_EVNT_SEL2 (0x00000CB4)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2);\r
  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M0_PMON_EVNT_SEL2 is defined as MSR_M0_PMON_EVNT_SEL2 in SDM.\r
**/\r
#define MSR_NEHALEM_M0_PMON_EVNT_SEL2  0x00000CB4\r
\r
/**\r
  Package. Uncore M-box 0 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M0_PMON_CTR2 (0x00000CB5)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR2);\r
  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M0_PMON_CTR2 is defined as MSR_M0_PMON_CTR2 in SDM.\r
**/\r
#define MSR_NEHALEM_M0_PMON_CTR2  0x00000CB5\r
\r
/**\r
  Package. Uncore M-box 0 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M0_PMON_EVNT_SEL3 (0x00000CB6)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3);\r
  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M0_PMON_EVNT_SEL3 is defined as MSR_M0_PMON_EVNT_SEL3 in SDM.\r
**/\r
#define MSR_NEHALEM_M0_PMON_EVNT_SEL3  0x00000CB6\r
\r
/**\r
  Package. Uncore M-box 0 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M0_PMON_CTR3 (0x00000CB7)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR3);\r
  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M0_PMON_CTR3 is defined as MSR_M0_PMON_CTR3 in SDM.\r
**/\r
#define MSR_NEHALEM_M0_PMON_CTR3  0x00000CB7\r
\r
/**\r
  Package. Uncore M-box 0 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M0_PMON_EVNT_SEL4 (0x00000CB8)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4);\r
  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL4, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M0_PMON_EVNT_SEL4 is defined as MSR_M0_PMON_EVNT_SEL4 in SDM.\r
**/\r
#define MSR_NEHALEM_M0_PMON_EVNT_SEL4  0x00000CB8\r
\r
/**\r
  Package. Uncore M-box 0 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M0_PMON_CTR4 (0x00000CB9)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR4);\r
  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR4, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M0_PMON_CTR4 is defined as MSR_M0_PMON_CTR4 in SDM.\r
**/\r
#define MSR_NEHALEM_M0_PMON_CTR4  0x00000CB9\r
\r
/**\r
  Package. Uncore M-box 0 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M0_PMON_EVNT_SEL5 (0x00000CBA)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5);\r
  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_EVNT_SEL5, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M0_PMON_EVNT_SEL5 is defined as MSR_M0_PMON_EVNT_SEL5 in SDM.\r
**/\r
#define MSR_NEHALEM_M0_PMON_EVNT_SEL5  0x00000CBA\r
\r
/**\r
  Package. Uncore M-box 0 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M0_PMON_CTR5 (0x00000CBB)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_CTR5);\r
  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_CTR5, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M0_PMON_CTR5 is defined as MSR_M0_PMON_CTR5 in SDM.\r
**/\r
#define MSR_NEHALEM_M0_PMON_CTR5  0x00000CBB\r
\r
/**\r
  Package. Uncore S-box 1 perfmon local box control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_S1_PMON_BOX_CTRL (0x00000CC0)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_S1_PMON_BOX_CTRL is defined as MSR_S1_PMON_BOX_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_S1_PMON_BOX_CTRL  0x00000CC0\r
\r
/**\r
  Package. Uncore S-box 1 perfmon local box status MSR.\r
\r
  @param  ECX  MSR_NEHALEM_S1_PMON_BOX_STATUS (0x00000CC1)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS);\r
  AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_STATUS, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_S1_PMON_BOX_STATUS is defined as MSR_S1_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_NEHALEM_S1_PMON_BOX_STATUS  0x00000CC1\r
\r
/**\r
  Package. Uncore S-box 1 perfmon local box overflow control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL (0x00000CC2)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL is defined as MSR_S1_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_S1_PMON_BOX_OVF_CTRL  0x00000CC2\r
\r
/**\r
  Package. Uncore S-box 1 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_S1_PMON_EVNT_SEL0 (0x00000CD0)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0);\r
  AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_S1_PMON_EVNT_SEL0 is defined as MSR_S1_PMON_EVNT_SEL0 in SDM.\r
**/\r
#define MSR_NEHALEM_S1_PMON_EVNT_SEL0  0x00000CD0\r
\r
/**\r
  Package. Uncore S-box 1 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_S1_PMON_CTR0 (0x00000CD1)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR0);\r
  AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_S1_PMON_CTR0 is defined as MSR_S1_PMON_CTR0 in SDM.\r
**/\r
#define MSR_NEHALEM_S1_PMON_CTR0  0x00000CD1\r
\r
/**\r
  Package. Uncore S-box 1 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_S1_PMON_EVNT_SEL1 (0x00000CD2)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1);\r
  AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_S1_PMON_EVNT_SEL1 is defined as MSR_S1_PMON_EVNT_SEL1 in SDM.\r
**/\r
#define MSR_NEHALEM_S1_PMON_EVNT_SEL1  0x00000CD2\r
\r
/**\r
  Package. Uncore S-box 1 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_S1_PMON_CTR1 (0x00000CD3)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR1);\r
  AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_S1_PMON_CTR1 is defined as MSR_S1_PMON_CTR1 in SDM.\r
**/\r
#define MSR_NEHALEM_S1_PMON_CTR1  0x00000CD3\r
\r
/**\r
  Package. Uncore S-box 1 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_S1_PMON_EVNT_SEL2 (0x00000CD4)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2);\r
  AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_S1_PMON_EVNT_SEL2 is defined as MSR_S1_PMON_EVNT_SEL2 in SDM.\r
**/\r
#define MSR_NEHALEM_S1_PMON_EVNT_SEL2  0x00000CD4\r
\r
/**\r
  Package. Uncore S-box 1 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_S1_PMON_CTR2 (0x00000CD5)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR2);\r
  AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_S1_PMON_CTR2 is defined as MSR_S1_PMON_CTR2 in SDM.\r
**/\r
#define MSR_NEHALEM_S1_PMON_CTR2  0x00000CD5\r
\r
/**\r
  Package. Uncore S-box 1 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_S1_PMON_EVNT_SEL3 (0x00000CD6)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3);\r
  AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_EVNT_SEL3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_S1_PMON_EVNT_SEL3 is defined as MSR_S1_PMON_EVNT_SEL3 in SDM.\r
**/\r
#define MSR_NEHALEM_S1_PMON_EVNT_SEL3  0x00000CD6\r
\r
/**\r
  Package. Uncore S-box 1 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_S1_PMON_CTR3 (0x00000CD7)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_CTR3);\r
  AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_CTR3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_S1_PMON_CTR3 is defined as MSR_S1_PMON_CTR3 in SDM.\r
**/\r
#define MSR_NEHALEM_S1_PMON_CTR3  0x00000CD7\r
\r
/**\r
  Package. Uncore M-box 1 perfmon local box control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M1_PMON_BOX_CTRL (0x00000CE0)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M1_PMON_BOX_CTRL is defined as MSR_M1_PMON_BOX_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_M1_PMON_BOX_CTRL  0x00000CE0\r
\r
/**\r
  Package. Uncore M-box 1 perfmon local box status MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M1_PMON_BOX_STATUS (0x00000CE1)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS);\r
  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_STATUS, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M1_PMON_BOX_STATUS is defined as MSR_M1_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_NEHALEM_M1_PMON_BOX_STATUS  0x00000CE1\r
\r
/**\r
  Package. Uncore M-box 1 perfmon local box overflow control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL (0x00000CE2)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL is defined as MSR_M1_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_M1_PMON_BOX_OVF_CTRL  0x00000CE2\r
\r
/**\r
  Package. Uncore M-box 1 perfmon time stamp unit select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M1_PMON_TIMESTAMP (0x00000CE4)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP);\r
  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_TIMESTAMP, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M1_PMON_TIMESTAMP is defined as MSR_M1_PMON_TIMESTAMP in SDM.\r
**/\r
#define MSR_NEHALEM_M1_PMON_TIMESTAMP  0x00000CE4\r
\r
/**\r
  Package. Uncore M-box 1 perfmon DSP unit select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M1_PMON_DSP (0x00000CE5)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_DSP);\r
  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_DSP, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M1_PMON_DSP is defined as MSR_M1_PMON_DSP in SDM.\r
**/\r
#define MSR_NEHALEM_M1_PMON_DSP  0x00000CE5\r
\r
/**\r
  Package. Uncore M-box 1 perfmon ISS unit select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M1_PMON_ISS (0x00000CE6)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ISS);\r
  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ISS, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M1_PMON_ISS is defined as MSR_M1_PMON_ISS in SDM.\r
**/\r
#define MSR_NEHALEM_M1_PMON_ISS  0x00000CE6\r
\r
/**\r
  Package. Uncore M-box 1 perfmon MAP unit select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M1_PMON_MAP (0x00000CE7)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MAP);\r
  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MAP, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M1_PMON_MAP is defined as MSR_M1_PMON_MAP in SDM.\r
**/\r
#define MSR_NEHALEM_M1_PMON_MAP  0x00000CE7\r
\r
/**\r
  Package. Uncore M-box 1 perfmon MIC THR select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M1_PMON_MSC_THR (0x00000CE8)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR);\r
  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MSC_THR, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M1_PMON_MSC_THR is defined as MSR_M1_PMON_MSC_THR in SDM.\r
**/\r
#define MSR_NEHALEM_M1_PMON_MSC_THR  0x00000CE8\r
\r
/**\r
  Package. Uncore M-box 1 perfmon PGT unit select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M1_PMON_PGT (0x00000CE9)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PGT);\r
  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PGT, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M1_PMON_PGT is defined as MSR_M1_PMON_PGT in SDM.\r
**/\r
#define MSR_NEHALEM_M1_PMON_PGT  0x00000CE9\r
\r
/**\r
  Package. Uncore M-box 1 perfmon PLD unit select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M1_PMON_PLD (0x00000CEA)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_PLD);\r
  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_PLD, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M1_PMON_PLD is defined as MSR_M1_PMON_PLD in SDM.\r
**/\r
#define MSR_NEHALEM_M1_PMON_PLD  0x00000CEA\r
\r
/**\r
  Package. Uncore M-box 1 perfmon ZDP unit select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M1_PMON_ZDP (0x00000CEB)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ZDP);\r
  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ZDP, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M1_PMON_ZDP is defined as MSR_M1_PMON_ZDP in SDM.\r
**/\r
#define MSR_NEHALEM_M1_PMON_ZDP  0x00000CEB\r
\r
/**\r
  Package. Uncore M-box 1 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M1_PMON_EVNT_SEL0 (0x00000CF0)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0);\r
  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M1_PMON_EVNT_SEL0 is defined as MSR_M1_PMON_EVNT_SEL0 in SDM.\r
**/\r
#define MSR_NEHALEM_M1_PMON_EVNT_SEL0  0x00000CF0\r
\r
/**\r
  Package. Uncore M-box 1 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M1_PMON_CTR0 (0x00000CF1)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR0);\r
  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M1_PMON_CTR0 is defined as MSR_M1_PMON_CTR0 in SDM.\r
**/\r
#define MSR_NEHALEM_M1_PMON_CTR0  0x00000CF1\r
\r
/**\r
  Package. Uncore M-box 1 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M1_PMON_EVNT_SEL1 (0x00000CF2)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1);\r
  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M1_PMON_EVNT_SEL1 is defined as MSR_M1_PMON_EVNT_SEL1 in SDM.\r
**/\r
#define MSR_NEHALEM_M1_PMON_EVNT_SEL1  0x00000CF2\r
\r
/**\r
  Package. Uncore M-box 1 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M1_PMON_CTR1 (0x00000CF3)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR1);\r
  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M1_PMON_CTR1 is defined as MSR_M1_PMON_CTR1 in SDM.\r
**/\r
#define MSR_NEHALEM_M1_PMON_CTR1  0x00000CF3\r
\r
/**\r
  Package. Uncore M-box 1 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M1_PMON_EVNT_SEL2 (0x00000CF4)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2);\r
  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M1_PMON_EVNT_SEL2 is defined as MSR_M1_PMON_EVNT_SEL2 in SDM.\r
**/\r
#define MSR_NEHALEM_M1_PMON_EVNT_SEL2  0x00000CF4\r
\r
/**\r
  Package. Uncore M-box 1 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M1_PMON_CTR2 (0x00000CF5)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR2);\r
  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M1_PMON_CTR2 is defined as MSR_M1_PMON_CTR2 in SDM.\r
**/\r
#define MSR_NEHALEM_M1_PMON_CTR2  0x00000CF5\r
\r
/**\r
  Package. Uncore M-box 1 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M1_PMON_EVNT_SEL3 (0x00000CF6)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3);\r
  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M1_PMON_EVNT_SEL3 is defined as MSR_M1_PMON_EVNT_SEL3 in SDM.\r
**/\r
#define MSR_NEHALEM_M1_PMON_EVNT_SEL3  0x00000CF6\r
\r
/**\r
  Package. Uncore M-box 1 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M1_PMON_CTR3 (0x00000CF7)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR3);\r
  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M1_PMON_CTR3 is defined as MSR_M1_PMON_CTR3 in SDM.\r
**/\r
#define MSR_NEHALEM_M1_PMON_CTR3  0x00000CF7\r
\r
/**\r
  Package. Uncore M-box 1 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M1_PMON_EVNT_SEL4 (0x00000CF8)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4);\r
  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL4, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M1_PMON_EVNT_SEL4 is defined as MSR_M1_PMON_EVNT_SEL4 in SDM.\r
**/\r
#define MSR_NEHALEM_M1_PMON_EVNT_SEL4  0x00000CF8\r
\r
/**\r
  Package. Uncore M-box 1 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M1_PMON_CTR4 (0x00000CF9)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR4);\r
  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR4, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M1_PMON_CTR4 is defined as MSR_M1_PMON_CTR4 in SDM.\r
**/\r
#define MSR_NEHALEM_M1_PMON_CTR4  0x00000CF9\r
\r
/**\r
  Package. Uncore M-box 1 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M1_PMON_EVNT_SEL5 (0x00000CFA)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5);\r
  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_EVNT_SEL5, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M1_PMON_EVNT_SEL5 is defined as MSR_M1_PMON_EVNT_SEL5 in SDM.\r
**/\r
#define MSR_NEHALEM_M1_PMON_EVNT_SEL5  0x00000CFA\r
\r
/**\r
  Package. Uncore M-box 1 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M1_PMON_CTR5 (0x00000CFB)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_CTR5);\r
  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_CTR5, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M1_PMON_CTR5 is defined as MSR_M1_PMON_CTR5 in SDM.\r
**/\r
#define MSR_NEHALEM_M1_PMON_CTR5  0x00000CFB\r
\r
/**\r
  Package. Uncore C-box 0 perfmon local box control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C0_PMON_BOX_CTRL (0x00000D00)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C0_PMON_BOX_CTRL is defined as MSR_C0_PMON_BOX_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_C0_PMON_BOX_CTRL  0x00000D00\r
\r
/**\r
  Package. Uncore C-box 0 perfmon local box status MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C0_PMON_BOX_STATUS (0x00000D01)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS);\r
  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_STATUS, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C0_PMON_BOX_STATUS is defined as MSR_C0_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_NEHALEM_C0_PMON_BOX_STATUS  0x00000D01\r
\r
/**\r
  Package. Uncore C-box 0 perfmon local box overflow control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL (0x00000D02)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL is defined as MSR_C0_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_C0_PMON_BOX_OVF_CTRL  0x00000D02\r
\r
/**\r
  Package. Uncore C-box 0 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C0_PMON_EVNT_SEL0 (0x00000D10)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0);\r
  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C0_PMON_EVNT_SEL0 is defined as MSR_C0_PMON_EVNT_SEL0 in SDM.\r
**/\r
#define MSR_NEHALEM_C0_PMON_EVNT_SEL0  0x00000D10\r
\r
/**\r
  Package. Uncore C-box 0 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C0_PMON_CTR0 (0x00000D11)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR0);\r
  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.\r
**/\r
#define MSR_NEHALEM_C0_PMON_CTR0  0x00000D11\r
\r
/**\r
  Package. Uncore C-box 0 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C0_PMON_EVNT_SEL1 (0x00000D12)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1);\r
  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C0_PMON_EVNT_SEL1 is defined as MSR_C0_PMON_EVNT_SEL1 in SDM.\r
**/\r
#define MSR_NEHALEM_C0_PMON_EVNT_SEL1  0x00000D12\r
\r
/**\r
  Package. Uncore C-box 0 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C0_PMON_CTR1 (0x00000D13)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR1);\r
  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.\r
**/\r
#define MSR_NEHALEM_C0_PMON_CTR1  0x00000D13\r
\r
/**\r
  Package. Uncore C-box 0 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C0_PMON_EVNT_SEL2 (0x00000D14)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2);\r
  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C0_PMON_EVNT_SEL2 is defined as MSR_C0_PMON_EVNT_SEL2 in SDM.\r
**/\r
#define MSR_NEHALEM_C0_PMON_EVNT_SEL2  0x00000D14\r
\r
/**\r
  Package. Uncore C-box 0 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C0_PMON_CTR2 (0x00000D15)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR2);\r
  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.\r
**/\r
#define MSR_NEHALEM_C0_PMON_CTR2  0x00000D15\r
\r
/**\r
  Package. Uncore C-box 0 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C0_PMON_EVNT_SEL3 (0x00000D16)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3);\r
  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C0_PMON_EVNT_SEL3 is defined as MSR_C0_PMON_EVNT_SEL3 in SDM.\r
**/\r
#define MSR_NEHALEM_C0_PMON_EVNT_SEL3  0x00000D16\r
\r
/**\r
  Package. Uncore C-box 0 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C0_PMON_CTR3 (0x00000D17)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR3);\r
  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.\r
**/\r
#define MSR_NEHALEM_C0_PMON_CTR3  0x00000D17\r
\r
/**\r
  Package. Uncore C-box 0 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C0_PMON_EVNT_SEL4 (0x00000D18)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4);\r
  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL4, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C0_PMON_EVNT_SEL4 is defined as MSR_C0_PMON_EVNT_SEL4 in SDM.\r
**/\r
#define MSR_NEHALEM_C0_PMON_EVNT_SEL4  0x00000D18\r
\r
/**\r
  Package. Uncore C-box 0 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C0_PMON_CTR4 (0x00000D19)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR4);\r
  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR4, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C0_PMON_CTR4 is defined as MSR_C0_PMON_CTR4 in SDM.\r
**/\r
#define MSR_NEHALEM_C0_PMON_CTR4  0x00000D19\r
\r
/**\r
  Package. Uncore C-box 0 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C0_PMON_EVNT_SEL5 (0x00000D1A)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5);\r
  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_EVNT_SEL5, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C0_PMON_EVNT_SEL5 is defined as MSR_C0_PMON_EVNT_SEL5 in SDM.\r
**/\r
#define MSR_NEHALEM_C0_PMON_EVNT_SEL5  0x00000D1A\r
\r
/**\r
  Package. Uncore C-box 0 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C0_PMON_CTR5 (0x00000D1B)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C0_PMON_CTR5);\r
  AsmWriteMsr64 (MSR_NEHALEM_C0_PMON_CTR5, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C0_PMON_CTR5 is defined as MSR_C0_PMON_CTR5 in SDM.\r
**/\r
#define MSR_NEHALEM_C0_PMON_CTR5  0x00000D1B\r
\r
/**\r
  Package. Uncore C-box 4 perfmon local box control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C4_PMON_BOX_CTRL (0x00000D20)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C4_PMON_BOX_CTRL is defined as MSR_C4_PMON_BOX_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_C4_PMON_BOX_CTRL  0x00000D20\r
\r
/**\r
  Package. Uncore C-box 4 perfmon local box status MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C4_PMON_BOX_STATUS (0x00000D21)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS);\r
  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_STATUS, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C4_PMON_BOX_STATUS is defined as MSR_C4_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_NEHALEM_C4_PMON_BOX_STATUS  0x00000D21\r
\r
/**\r
  Package. Uncore C-box 4 perfmon local box overflow control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL (0x00000D22)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL is defined as MSR_C4_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_C4_PMON_BOX_OVF_CTRL  0x00000D22\r
\r
/**\r
  Package. Uncore C-box 4 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C4_PMON_EVNT_SEL0 (0x00000D30)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0);\r
  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C4_PMON_EVNT_SEL0 is defined as MSR_C4_PMON_EVNT_SEL0 in SDM.\r
**/\r
#define MSR_NEHALEM_C4_PMON_EVNT_SEL0  0x00000D30\r
\r
/**\r
  Package. Uncore C-box 4 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C4_PMON_CTR0 (0x00000D31)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR0);\r
  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.\r
**/\r
#define MSR_NEHALEM_C4_PMON_CTR0  0x00000D31\r
\r
/**\r
  Package. Uncore C-box 4 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C4_PMON_EVNT_SEL1 (0x00000D32)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1);\r
  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C4_PMON_EVNT_SEL1 is defined as MSR_C4_PMON_EVNT_SEL1 in SDM.\r
**/\r
#define MSR_NEHALEM_C4_PMON_EVNT_SEL1  0x00000D32\r
\r
/**\r
  Package. Uncore C-box 4 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C4_PMON_CTR1 (0x00000D33)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR1);\r
  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.\r
**/\r
#define MSR_NEHALEM_C4_PMON_CTR1  0x00000D33\r
\r
/**\r
  Package. Uncore C-box 4 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C4_PMON_EVNT_SEL2 (0x00000D34)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2);\r
  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C4_PMON_EVNT_SEL2 is defined as MSR_C4_PMON_EVNT_SEL2 in SDM.\r
**/\r
#define MSR_NEHALEM_C4_PMON_EVNT_SEL2  0x00000D34\r
\r
/**\r
  Package. Uncore C-box 4 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C4_PMON_CTR2 (0x00000D35)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR2);\r
  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.\r
**/\r
#define MSR_NEHALEM_C4_PMON_CTR2  0x00000D35\r
\r
/**\r
  Package. Uncore C-box 4 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C4_PMON_EVNT_SEL3 (0x00000D36)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3);\r
  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C4_PMON_EVNT_SEL3 is defined as MSR_C4_PMON_EVNT_SEL3 in SDM.\r
**/\r
#define MSR_NEHALEM_C4_PMON_EVNT_SEL3  0x00000D36\r
\r
/**\r
  Package. Uncore C-box 4 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C4_PMON_CTR3 (0x00000D37)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR3);\r
  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.\r
**/\r
#define MSR_NEHALEM_C4_PMON_CTR3  0x00000D37\r
\r
/**\r
  Package. Uncore C-box 4 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C4_PMON_EVNT_SEL4 (0x00000D38)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4);\r
  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL4, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C4_PMON_EVNT_SEL4 is defined as MSR_C4_PMON_EVNT_SEL4 in SDM.\r
**/\r
#define MSR_NEHALEM_C4_PMON_EVNT_SEL4  0x00000D38\r
\r
/**\r
  Package. Uncore C-box 4 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C4_PMON_CTR4 (0x00000D39)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR4);\r
  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR4, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C4_PMON_CTR4 is defined as MSR_C4_PMON_CTR4 in SDM.\r
**/\r
#define MSR_NEHALEM_C4_PMON_CTR4  0x00000D39\r
\r
/**\r
  Package. Uncore C-box 4 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C4_PMON_EVNT_SEL5 (0x00000D3A)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5);\r
  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_EVNT_SEL5, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C4_PMON_EVNT_SEL5 is defined as MSR_C4_PMON_EVNT_SEL5 in SDM.\r
**/\r
#define MSR_NEHALEM_C4_PMON_EVNT_SEL5  0x00000D3A\r
\r
/**\r
  Package. Uncore C-box 4 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C4_PMON_CTR5 (0x00000D3B)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C4_PMON_CTR5);\r
  AsmWriteMsr64 (MSR_NEHALEM_C4_PMON_CTR5, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C4_PMON_CTR5 is defined as MSR_C4_PMON_CTR5 in SDM.\r
**/\r
#define MSR_NEHALEM_C4_PMON_CTR5  0x00000D3B\r
\r
/**\r
  Package. Uncore C-box 2 perfmon local box control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C2_PMON_BOX_CTRL (0x00000D40)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C2_PMON_BOX_CTRL is defined as MSR_C2_PMON_BOX_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_C2_PMON_BOX_CTRL  0x00000D40\r
\r
/**\r
  Package. Uncore C-box 2 perfmon local box status MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C2_PMON_BOX_STATUS (0x00000D41)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS);\r
  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_STATUS, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C2_PMON_BOX_STATUS is defined as MSR_C2_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_NEHALEM_C2_PMON_BOX_STATUS  0x00000D41\r
\r
/**\r
  Package. Uncore C-box 2 perfmon local box overflow control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL (0x00000D42)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL is defined as MSR_C2_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_C2_PMON_BOX_OVF_CTRL  0x00000D42\r
\r
/**\r
  Package. Uncore C-box 2 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C2_PMON_EVNT_SEL0 (0x00000D50)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0);\r
  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C2_PMON_EVNT_SEL0 is defined as MSR_C2_PMON_EVNT_SEL0 in SDM.\r
**/\r
#define MSR_NEHALEM_C2_PMON_EVNT_SEL0  0x00000D50\r
\r
/**\r
  Package. Uncore C-box 2 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C2_PMON_CTR0 (0x00000D51)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR0);\r
  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.\r
**/\r
#define MSR_NEHALEM_C2_PMON_CTR0  0x00000D51\r
\r
/**\r
  Package. Uncore C-box 2 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C2_PMON_EVNT_SEL1 (0x00000D52)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1);\r
  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C2_PMON_EVNT_SEL1 is defined as MSR_C2_PMON_EVNT_SEL1 in SDM.\r
**/\r
#define MSR_NEHALEM_C2_PMON_EVNT_SEL1  0x00000D52\r
\r
/**\r
  Package. Uncore C-box 2 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C2_PMON_CTR1 (0x00000D53)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR1);\r
  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.\r
**/\r
#define MSR_NEHALEM_C2_PMON_CTR1  0x00000D53\r
\r
/**\r
  Package. Uncore C-box 2 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C2_PMON_EVNT_SEL2 (0x00000D54)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2);\r
  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C2_PMON_EVNT_SEL2 is defined as MSR_C2_PMON_EVNT_SEL2 in SDM.\r
**/\r
#define MSR_NEHALEM_C2_PMON_EVNT_SEL2  0x00000D54\r
\r
/**\r
  Package. Uncore C-box 2 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C2_PMON_CTR2 (0x00000D55)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR2);\r
  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.\r
**/\r
#define MSR_NEHALEM_C2_PMON_CTR2  0x00000D55\r
\r
/**\r
  Package. Uncore C-box 2 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C2_PMON_EVNT_SEL3 (0x00000D56)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3);\r
  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C2_PMON_EVNT_SEL3 is defined as MSR_C2_PMON_EVNT_SEL3 in SDM.\r
**/\r
#define MSR_NEHALEM_C2_PMON_EVNT_SEL3  0x00000D56\r
\r
/**\r
  Package. Uncore C-box 2 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C2_PMON_CTR3 (0x00000D57)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR3);\r
  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.\r
**/\r
#define MSR_NEHALEM_C2_PMON_CTR3  0x00000D57\r
\r
/**\r
  Package. Uncore C-box 2 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C2_PMON_EVNT_SEL4 (0x00000D58)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4);\r
  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL4, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C2_PMON_EVNT_SEL4 is defined as MSR_C2_PMON_EVNT_SEL4 in SDM.\r
**/\r
#define MSR_NEHALEM_C2_PMON_EVNT_SEL4  0x00000D58\r
\r
/**\r
  Package. Uncore C-box 2 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C2_PMON_CTR4 (0x00000D59)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR4);\r
  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR4, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C2_PMON_CTR4 is defined as MSR_C2_PMON_CTR4 in SDM.\r
**/\r
#define MSR_NEHALEM_C2_PMON_CTR4  0x00000D59\r
\r
/**\r
  Package. Uncore C-box 2 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C2_PMON_EVNT_SEL5 (0x00000D5A)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5);\r
  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_EVNT_SEL5, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C2_PMON_EVNT_SEL5 is defined as MSR_C2_PMON_EVNT_SEL5 in SDM.\r
**/\r
#define MSR_NEHALEM_C2_PMON_EVNT_SEL5  0x00000D5A\r
\r
/**\r
  Package. Uncore C-box 2 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C2_PMON_CTR5 (0x00000D5B)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C2_PMON_CTR5);\r
  AsmWriteMsr64 (MSR_NEHALEM_C2_PMON_CTR5, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C2_PMON_CTR5 is defined as MSR_C2_PMON_CTR5 in SDM.\r
**/\r
#define MSR_NEHALEM_C2_PMON_CTR5  0x00000D5B\r
\r
/**\r
  Package. Uncore C-box 6 perfmon local box control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C6_PMON_BOX_CTRL (0x00000D60)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C6_PMON_BOX_CTRL is defined as MSR_C6_PMON_BOX_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_C6_PMON_BOX_CTRL  0x00000D60\r
\r
/**\r
  Package. Uncore C-box 6 perfmon local box status MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C6_PMON_BOX_STATUS (0x00000D61)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS);\r
  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_STATUS, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C6_PMON_BOX_STATUS is defined as MSR_C6_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_NEHALEM_C6_PMON_BOX_STATUS  0x00000D61\r
\r
/**\r
  Package. Uncore C-box 6 perfmon local box overflow control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL (0x00000D62)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL is defined as MSR_C6_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_C6_PMON_BOX_OVF_CTRL  0x00000D62\r
\r
/**\r
  Package. Uncore C-box 6 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C6_PMON_EVNT_SEL0 (0x00000D70)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0);\r
  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C6_PMON_EVNT_SEL0 is defined as MSR_C6_PMON_EVNT_SEL0 in SDM.\r
**/\r
#define MSR_NEHALEM_C6_PMON_EVNT_SEL0  0x00000D70\r
\r
/**\r
  Package. Uncore C-box 6 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C6_PMON_CTR0 (0x00000D71)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR0);\r
  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.\r
**/\r
#define MSR_NEHALEM_C6_PMON_CTR0  0x00000D71\r
\r
/**\r
  Package. Uncore C-box 6 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C6_PMON_EVNT_SEL1 (0x00000D72)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1);\r
  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C6_PMON_EVNT_SEL1 is defined as MSR_C6_PMON_EVNT_SEL1 in SDM.\r
**/\r
#define MSR_NEHALEM_C6_PMON_EVNT_SEL1  0x00000D72\r
\r
/**\r
  Package. Uncore C-box 6 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C6_PMON_CTR1 (0x00000D73)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR1);\r
  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.\r
**/\r
#define MSR_NEHALEM_C6_PMON_CTR1  0x00000D73\r
\r
/**\r
  Package. Uncore C-box 6 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C6_PMON_EVNT_SEL2 (0x00000D74)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2);\r
  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C6_PMON_EVNT_SEL2 is defined as MSR_C6_PMON_EVNT_SEL2 in SDM.\r
**/\r
#define MSR_NEHALEM_C6_PMON_EVNT_SEL2  0x00000D74\r
\r
/**\r
  Package. Uncore C-box 6 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C6_PMON_CTR2 (0x00000D75)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR2);\r
  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.\r
**/\r
#define MSR_NEHALEM_C6_PMON_CTR2  0x00000D75\r
\r
/**\r
  Package. Uncore C-box 6 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C6_PMON_EVNT_SEL3 (0x00000D76)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3);\r
  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C6_PMON_EVNT_SEL3 is defined as MSR_C6_PMON_EVNT_SEL3 in SDM.\r
**/\r
#define MSR_NEHALEM_C6_PMON_EVNT_SEL3  0x00000D76\r
\r
/**\r
  Package. Uncore C-box 6 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C6_PMON_CTR3 (0x00000D77)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR3);\r
  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.\r
**/\r
#define MSR_NEHALEM_C6_PMON_CTR3  0x00000D77\r
\r
/**\r
  Package. Uncore C-box 6 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C6_PMON_EVNT_SEL4 (0x00000D78)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4);\r
  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL4, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C6_PMON_EVNT_SEL4 is defined as MSR_C6_PMON_EVNT_SEL4 in SDM.\r
**/\r
#define MSR_NEHALEM_C6_PMON_EVNT_SEL4  0x00000D78\r
\r
/**\r
  Package. Uncore C-box 6 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C6_PMON_CTR4 (0x00000D79)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR4);\r
  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR4, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C6_PMON_CTR4 is defined as MSR_C6_PMON_CTR4 in SDM.\r
**/\r
#define MSR_NEHALEM_C6_PMON_CTR4  0x00000D79\r
\r
/**\r
  Package. Uncore C-box 6 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C6_PMON_EVNT_SEL5 (0x00000D7A)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5);\r
  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_EVNT_SEL5, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C6_PMON_EVNT_SEL5 is defined as MSR_C6_PMON_EVNT_SEL5 in SDM.\r
**/\r
#define MSR_NEHALEM_C6_PMON_EVNT_SEL5  0x00000D7A\r
\r
/**\r
  Package. Uncore C-box 6 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C6_PMON_CTR5 (0x00000D7B)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C6_PMON_CTR5);\r
  AsmWriteMsr64 (MSR_NEHALEM_C6_PMON_CTR5, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C6_PMON_CTR5 is defined as MSR_C6_PMON_CTR5 in SDM.\r
**/\r
#define MSR_NEHALEM_C6_PMON_CTR5  0x00000D7B\r
\r
/**\r
  Package. Uncore C-box 1 perfmon local box control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C1_PMON_BOX_CTRL (0x00000D80)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C1_PMON_BOX_CTRL is defined as MSR_C1_PMON_BOX_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_C1_PMON_BOX_CTRL  0x00000D80\r
\r
/**\r
  Package. Uncore C-box 1 perfmon local box status MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C1_PMON_BOX_STATUS (0x00000D81)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS);\r
  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_STATUS, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C1_PMON_BOX_STATUS is defined as MSR_C1_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_NEHALEM_C1_PMON_BOX_STATUS  0x00000D81\r
\r
/**\r
  Package. Uncore C-box 1 perfmon local box overflow control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL (0x00000D82)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL is defined as MSR_C1_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_C1_PMON_BOX_OVF_CTRL  0x00000D82\r
\r
/**\r
  Package. Uncore C-box 1 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C1_PMON_EVNT_SEL0 (0x00000D90)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0);\r
  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C1_PMON_EVNT_SEL0 is defined as MSR_C1_PMON_EVNT_SEL0 in SDM.\r
**/\r
#define MSR_NEHALEM_C1_PMON_EVNT_SEL0  0x00000D90\r
\r
/**\r
  Package. Uncore C-box 1 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C1_PMON_CTR0 (0x00000D91)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR0);\r
  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.\r
**/\r
#define MSR_NEHALEM_C1_PMON_CTR0  0x00000D91\r
\r
/**\r
  Package. Uncore C-box 1 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C1_PMON_EVNT_SEL1 (0x00000D92)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1);\r
  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C1_PMON_EVNT_SEL1 is defined as MSR_C1_PMON_EVNT_SEL1 in SDM.\r
**/\r
#define MSR_NEHALEM_C1_PMON_EVNT_SEL1  0x00000D92\r
\r
/**\r
  Package. Uncore C-box 1 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C1_PMON_CTR1 (0x00000D93)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR1);\r
  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.\r
**/\r
#define MSR_NEHALEM_C1_PMON_CTR1  0x00000D93\r
\r
/**\r
  Package. Uncore C-box 1 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C1_PMON_EVNT_SEL2 (0x00000D94)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2);\r
  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C1_PMON_EVNT_SEL2 is defined as MSR_C1_PMON_EVNT_SEL2 in SDM.\r
**/\r
#define MSR_NEHALEM_C1_PMON_EVNT_SEL2  0x00000D94\r
\r
/**\r
  Package. Uncore C-box 1 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C1_PMON_CTR2 (0x00000D95)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR2);\r
  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.\r
**/\r
#define MSR_NEHALEM_C1_PMON_CTR2  0x00000D95\r
\r
/**\r
  Package. Uncore C-box 1 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C1_PMON_EVNT_SEL3 (0x00000D96)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3);\r
  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C1_PMON_EVNT_SEL3 is defined as MSR_C1_PMON_EVNT_SEL3 in SDM.\r
**/\r
#define MSR_NEHALEM_C1_PMON_EVNT_SEL3  0x00000D96\r
\r
/**\r
  Package. Uncore C-box 1 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C1_PMON_CTR3 (0x00000D97)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR3);\r
  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.\r
**/\r
#define MSR_NEHALEM_C1_PMON_CTR3  0x00000D97\r
\r
/**\r
  Package. Uncore C-box 1 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C1_PMON_EVNT_SEL4 (0x00000D98)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4);\r
  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL4, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C1_PMON_EVNT_SEL4 is defined as MSR_C1_PMON_EVNT_SEL4 in SDM.\r
**/\r
#define MSR_NEHALEM_C1_PMON_EVNT_SEL4  0x00000D98\r
\r
/**\r
  Package. Uncore C-box 1 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C1_PMON_CTR4 (0x00000D99)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR4);\r
  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR4, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C1_PMON_CTR4 is defined as MSR_C1_PMON_CTR4 in SDM.\r
**/\r
#define MSR_NEHALEM_C1_PMON_CTR4  0x00000D99\r
\r
/**\r
  Package. Uncore C-box 1 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C1_PMON_EVNT_SEL5 (0x00000D9A)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5);\r
  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_EVNT_SEL5, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C1_PMON_EVNT_SEL5 is defined as MSR_C1_PMON_EVNT_SEL5 in SDM.\r
**/\r
#define MSR_NEHALEM_C1_PMON_EVNT_SEL5  0x00000D9A\r
\r
/**\r
  Package. Uncore C-box 1 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C1_PMON_CTR5 (0x00000D9B)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C1_PMON_CTR5);\r
  AsmWriteMsr64 (MSR_NEHALEM_C1_PMON_CTR5, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C1_PMON_CTR5 is defined as MSR_C1_PMON_CTR5 in SDM.\r
**/\r
#define MSR_NEHALEM_C1_PMON_CTR5  0x00000D9B\r
\r
/**\r
  Package. Uncore C-box 5 perfmon local box control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C5_PMON_BOX_CTRL (0x00000DA0)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C5_PMON_BOX_CTRL is defined as MSR_C5_PMON_BOX_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_C5_PMON_BOX_CTRL  0x00000DA0\r
\r
/**\r
  Package. Uncore C-box 5 perfmon local box status MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C5_PMON_BOX_STATUS (0x00000DA1)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS);\r
  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_STATUS, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C5_PMON_BOX_STATUS is defined as MSR_C5_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_NEHALEM_C5_PMON_BOX_STATUS  0x00000DA1\r
\r
/**\r
  Package. Uncore C-box 5 perfmon local box overflow control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL (0x00000DA2)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL is defined as MSR_C5_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_C5_PMON_BOX_OVF_CTRL  0x00000DA2\r
\r
/**\r
  Package. Uncore C-box 5 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C5_PMON_EVNT_SEL0 (0x00000DB0)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0);\r
  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C5_PMON_EVNT_SEL0 is defined as MSR_C5_PMON_EVNT_SEL0 in SDM.\r
**/\r
#define MSR_NEHALEM_C5_PMON_EVNT_SEL0  0x00000DB0\r
\r
/**\r
  Package. Uncore C-box 5 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C5_PMON_CTR0 (0x00000DB1)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR0);\r
  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.\r
**/\r
#define MSR_NEHALEM_C5_PMON_CTR0  0x00000DB1\r
\r
/**\r
  Package. Uncore C-box 5 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C5_PMON_EVNT_SEL1 (0x00000DB2)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1);\r
  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C5_PMON_EVNT_SEL1 is defined as MSR_C5_PMON_EVNT_SEL1 in SDM.\r
**/\r
#define MSR_NEHALEM_C5_PMON_EVNT_SEL1  0x00000DB2\r
\r
/**\r
  Package. Uncore C-box 5 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C5_PMON_CTR1 (0x00000DB3)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR1);\r
  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.\r
**/\r
#define MSR_NEHALEM_C5_PMON_CTR1  0x00000DB3\r
\r
/**\r
  Package. Uncore C-box 5 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C5_PMON_EVNT_SEL2 (0x00000DB4)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2);\r
  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C5_PMON_EVNT_SEL2 is defined as MSR_C5_PMON_EVNT_SEL2 in SDM.\r
**/\r
#define MSR_NEHALEM_C5_PMON_EVNT_SEL2  0x00000DB4\r
\r
/**\r
  Package. Uncore C-box 5 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C5_PMON_CTR2 (0x00000DB5)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR2);\r
  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.\r
**/\r
#define MSR_NEHALEM_C5_PMON_CTR2  0x00000DB5\r
\r
/**\r
  Package. Uncore C-box 5 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C5_PMON_EVNT_SEL3 (0x00000DB6)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3);\r
  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C5_PMON_EVNT_SEL3 is defined as MSR_C5_PMON_EVNT_SEL3 in SDM.\r
**/\r
#define MSR_NEHALEM_C5_PMON_EVNT_SEL3  0x00000DB6\r
\r
/**\r
  Package. Uncore C-box 5 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C5_PMON_CTR3 (0x00000DB7)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR3);\r
  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.\r
**/\r
#define MSR_NEHALEM_C5_PMON_CTR3  0x00000DB7\r
\r
/**\r
  Package. Uncore C-box 5 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C5_PMON_EVNT_SEL4 (0x00000DB8)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4);\r
  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL4, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C5_PMON_EVNT_SEL4 is defined as MSR_C5_PMON_EVNT_SEL4 in SDM.\r
**/\r
#define MSR_NEHALEM_C5_PMON_EVNT_SEL4  0x00000DB8\r
\r
/**\r
  Package. Uncore C-box 5 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C5_PMON_CTR4 (0x00000DB9)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR4);\r
  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR4, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C5_PMON_CTR4 is defined as MSR_C5_PMON_CTR4 in SDM.\r
**/\r
#define MSR_NEHALEM_C5_PMON_CTR4  0x00000DB9\r
\r
/**\r
  Package. Uncore C-box 5 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C5_PMON_EVNT_SEL5 (0x00000DBA)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5);\r
  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_EVNT_SEL5, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C5_PMON_EVNT_SEL5 is defined as MSR_C5_PMON_EVNT_SEL5 in SDM.\r
**/\r
#define MSR_NEHALEM_C5_PMON_EVNT_SEL5  0x00000DBA\r
\r
/**\r
  Package. Uncore C-box 5 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C5_PMON_CTR5 (0x00000DBB)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C5_PMON_CTR5);\r
  AsmWriteMsr64 (MSR_NEHALEM_C5_PMON_CTR5, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C5_PMON_CTR5 is defined as MSR_C5_PMON_CTR5 in SDM.\r
**/\r
#define MSR_NEHALEM_C5_PMON_CTR5  0x00000DBB\r
\r
/**\r
  Package. Uncore C-box 3 perfmon local box control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C3_PMON_BOX_CTRL (0x00000DC0)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C3_PMON_BOX_CTRL is defined as MSR_C3_PMON_BOX_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_C3_PMON_BOX_CTRL  0x00000DC0\r
\r
/**\r
  Package. Uncore C-box 3 perfmon local box status MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C3_PMON_BOX_STATUS (0x00000DC1)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS);\r
  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_STATUS, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C3_PMON_BOX_STATUS is defined as MSR_C3_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_NEHALEM_C3_PMON_BOX_STATUS  0x00000DC1\r
\r
/**\r
  Package. Uncore C-box 3 perfmon local box overflow control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL (0x00000DC2)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL is defined as MSR_C3_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_C3_PMON_BOX_OVF_CTRL  0x00000DC2\r
\r
/**\r
  Package. Uncore C-box 3 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C3_PMON_EVNT_SEL0 (0x00000DD0)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0);\r
  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C3_PMON_EVNT_SEL0 is defined as MSR_C3_PMON_EVNT_SEL0 in SDM.\r
**/\r
#define MSR_NEHALEM_C3_PMON_EVNT_SEL0  0x00000DD0\r
\r
/**\r
  Package. Uncore C-box 3 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C3_PMON_CTR0 (0x00000DD1)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR0);\r
  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.\r
**/\r
#define MSR_NEHALEM_C3_PMON_CTR0  0x00000DD1\r
\r
/**\r
  Package. Uncore C-box 3 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C3_PMON_EVNT_SEL1 (0x00000DD2)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1);\r
  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C3_PMON_EVNT_SEL1 is defined as MSR_C3_PMON_EVNT_SEL1 in SDM.\r
**/\r
#define MSR_NEHALEM_C3_PMON_EVNT_SEL1  0x00000DD2\r
\r
/**\r
  Package. Uncore C-box 3 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C3_PMON_CTR1 (0x00000DD3)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR1);\r
  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.\r
**/\r
#define MSR_NEHALEM_C3_PMON_CTR1  0x00000DD3\r
\r
/**\r
  Package. Uncore C-box 3 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C3_PMON_EVNT_SEL2 (0x00000DD4)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2);\r
  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C3_PMON_EVNT_SEL2 is defined as MSR_C3_PMON_EVNT_SEL2 in SDM.\r
**/\r
#define MSR_NEHALEM_C3_PMON_EVNT_SEL2  0x00000DD4\r
\r
/**\r
  Package. Uncore C-box 3 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C3_PMON_CTR2 (0x00000DD5)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR2);\r
  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.\r
**/\r
#define MSR_NEHALEM_C3_PMON_CTR2  0x00000DD5\r
\r
/**\r
  Package. Uncore C-box 3 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C3_PMON_EVNT_SEL3 (0x00000DD6)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3);\r
  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C3_PMON_EVNT_SEL3 is defined as MSR_C3_PMON_EVNT_SEL3 in SDM.\r
**/\r
#define MSR_NEHALEM_C3_PMON_EVNT_SEL3  0x00000DD6\r
\r
/**\r
  Package. Uncore C-box 3 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C3_PMON_CTR3 (0x00000DD7)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR3);\r
  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.\r
**/\r
#define MSR_NEHALEM_C3_PMON_CTR3  0x00000DD7\r
\r
/**\r
  Package. Uncore C-box 3 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C3_PMON_EVNT_SEL4 (0x00000DD8)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4);\r
  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL4, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C3_PMON_EVNT_SEL4 is defined as MSR_C3_PMON_EVNT_SEL4 in SDM.\r
**/\r
#define MSR_NEHALEM_C3_PMON_EVNT_SEL4  0x00000DD8\r
\r
/**\r
  Package. Uncore C-box 3 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C3_PMON_CTR4 (0x00000DD9)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR4);\r
  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR4, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C3_PMON_CTR4 is defined as MSR_C3_PMON_CTR4 in SDM.\r
**/\r
#define MSR_NEHALEM_C3_PMON_CTR4  0x00000DD9\r
\r
/**\r
  Package. Uncore C-box 3 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C3_PMON_EVNT_SEL5 (0x00000DDA)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5);\r
  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_EVNT_SEL5, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C3_PMON_EVNT_SEL5 is defined as MSR_C3_PMON_EVNT_SEL5 in SDM.\r
**/\r
#define MSR_NEHALEM_C3_PMON_EVNT_SEL5  0x00000DDA\r
\r
/**\r
  Package. Uncore C-box 3 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C3_PMON_CTR5 (0x00000DDB)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C3_PMON_CTR5);\r
  AsmWriteMsr64 (MSR_NEHALEM_C3_PMON_CTR5, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C3_PMON_CTR5 is defined as MSR_C3_PMON_CTR5 in SDM.\r
**/\r
#define MSR_NEHALEM_C3_PMON_CTR5  0x00000DDB\r
\r
/**\r
  Package. Uncore C-box 7 perfmon local box control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C7_PMON_BOX_CTRL (0x00000DE0)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C7_PMON_BOX_CTRL is defined as MSR_C7_PMON_BOX_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_C7_PMON_BOX_CTRL  0x00000DE0\r
\r
/**\r
  Package. Uncore C-box 7 perfmon local box status MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C7_PMON_BOX_STATUS (0x00000DE1)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS);\r
  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_STATUS, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C7_PMON_BOX_STATUS is defined as MSR_C7_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_NEHALEM_C7_PMON_BOX_STATUS  0x00000DE1\r
\r
/**\r
  Package. Uncore C-box 7 perfmon local box overflow control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL (0x00000DE2)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL is defined as MSR_C7_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_C7_PMON_BOX_OVF_CTRL  0x00000DE2\r
\r
/**\r
  Package. Uncore C-box 7 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C7_PMON_EVNT_SEL0 (0x00000DF0)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0);\r
  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C7_PMON_EVNT_SEL0 is defined as MSR_C7_PMON_EVNT_SEL0 in SDM.\r
**/\r
#define MSR_NEHALEM_C7_PMON_EVNT_SEL0  0x00000DF0\r
\r
/**\r
  Package. Uncore C-box 7 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C7_PMON_CTR0 (0x00000DF1)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR0);\r
  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.\r
**/\r
#define MSR_NEHALEM_C7_PMON_CTR0  0x00000DF1\r
\r
/**\r
  Package. Uncore C-box 7 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C7_PMON_EVNT_SEL1 (0x00000DF2)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1);\r
  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C7_PMON_EVNT_SEL1 is defined as MSR_C7_PMON_EVNT_SEL1 in SDM.\r
**/\r
#define MSR_NEHALEM_C7_PMON_EVNT_SEL1  0x00000DF2\r
\r
/**\r
  Package. Uncore C-box 7 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C7_PMON_CTR1 (0x00000DF3)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR1);\r
  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.\r
**/\r
#define MSR_NEHALEM_C7_PMON_CTR1  0x00000DF3\r
\r
/**\r
  Package. Uncore C-box 7 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C7_PMON_EVNT_SEL2 (0x00000DF4)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2);\r
  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C7_PMON_EVNT_SEL2 is defined as MSR_C7_PMON_EVNT_SEL2 in SDM.\r
**/\r
#define MSR_NEHALEM_C7_PMON_EVNT_SEL2  0x00000DF4\r
\r
/**\r
  Package. Uncore C-box 7 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C7_PMON_CTR2 (0x00000DF5)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR2);\r
  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.\r
**/\r
#define MSR_NEHALEM_C7_PMON_CTR2  0x00000DF5\r
\r
/**\r
  Package. Uncore C-box 7 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C7_PMON_EVNT_SEL3 (0x00000DF6)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3);\r
  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C7_PMON_EVNT_SEL3 is defined as MSR_C7_PMON_EVNT_SEL3 in SDM.\r
**/\r
#define MSR_NEHALEM_C7_PMON_EVNT_SEL3  0x00000DF6\r
\r
/**\r
  Package. Uncore C-box 7 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C7_PMON_CTR3 (0x00000DF7)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR3);\r
  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.\r
**/\r
#define MSR_NEHALEM_C7_PMON_CTR3  0x00000DF7\r
\r
/**\r
  Package. Uncore C-box 7 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C7_PMON_EVNT_SEL4 (0x00000DF8)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4);\r
  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL4, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C7_PMON_EVNT_SEL4 is defined as MSR_C7_PMON_EVNT_SEL4 in SDM.\r
**/\r
#define MSR_NEHALEM_C7_PMON_EVNT_SEL4  0x00000DF8\r
\r
/**\r
  Package. Uncore C-box 7 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C7_PMON_CTR4 (0x00000DF9)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR4);\r
  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR4, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C7_PMON_CTR4 is defined as MSR_C7_PMON_CTR4 in SDM.\r
**/\r
#define MSR_NEHALEM_C7_PMON_CTR4  0x00000DF9\r
\r
/**\r
  Package. Uncore C-box 7 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C7_PMON_EVNT_SEL5 (0x00000DFA)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5);\r
  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_EVNT_SEL5, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C7_PMON_EVNT_SEL5 is defined as MSR_C7_PMON_EVNT_SEL5 in SDM.\r
**/\r
#define MSR_NEHALEM_C7_PMON_EVNT_SEL5  0x00000DFA\r
\r
/**\r
  Package. Uncore C-box 7 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_C7_PMON_CTR5 (0x00000DFB)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_C7_PMON_CTR5);\r
  AsmWriteMsr64 (MSR_NEHALEM_C7_PMON_CTR5, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_C7_PMON_CTR5 is defined as MSR_C7_PMON_CTR5 in SDM.\r
**/\r
#define MSR_NEHALEM_C7_PMON_CTR5  0x00000DFB\r
\r
/**\r
  Package. Uncore R-box 0 perfmon local box control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_BOX_CTRL (0x00000E00)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_BOX_CTRL is defined as MSR_R0_PMON_BOX_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_BOX_CTRL  0x00000E00\r
\r
/**\r
  Package. Uncore R-box 0 perfmon local box status MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_BOX_STATUS (0x00000E01)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_STATUS, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_BOX_STATUS is defined as MSR_R0_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_BOX_STATUS  0x00000E01\r
\r
/**\r
  Package. Uncore R-box 0 perfmon local box overflow control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL (0x00000E02)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL is defined as MSR_R0_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_BOX_OVF_CTRL  0x00000E02\r
\r
/**\r
  Package. Uncore R-box 0 perfmon IPERF0 unit Port 0 select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_IPERF0_P0 (0x00000E04)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_IPERF0_P0 is defined as MSR_R0_PMON_IPERF0_P0 in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_IPERF0_P0  0x00000E04\r
\r
/**\r
  Package. Uncore R-box 0 perfmon IPERF0 unit Port 1 select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_IPERF0_P1 (0x00000E05)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_IPERF0_P1 is defined as MSR_R0_PMON_IPERF0_P1 in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_IPERF0_P1  0x00000E05\r
\r
/**\r
  Package. Uncore R-box 0 perfmon IPERF0 unit Port 2 select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_IPERF0_P2 (0x00000E06)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_IPERF0_P2 is defined as MSR_R0_PMON_IPERF0_P2 in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_IPERF0_P2  0x00000E06\r
\r
/**\r
  Package. Uncore R-box 0 perfmon IPERF0 unit Port 3 select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_IPERF0_P3 (0x00000E07)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_IPERF0_P3 is defined as MSR_R0_PMON_IPERF0_P3 in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_IPERF0_P3  0x00000E07\r
\r
/**\r
  Package. Uncore R-box 0 perfmon IPERF0 unit Port 4 select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_IPERF0_P4 (0x00000E08)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P4, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_IPERF0_P4 is defined as MSR_R0_PMON_IPERF0_P4 in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_IPERF0_P4  0x00000E08\r
\r
/**\r
  Package. Uncore R-box 0 perfmon IPERF0 unit Port 5 select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_IPERF0_P5 (0x00000E09)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P5, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_IPERF0_P5 is defined as MSR_R0_PMON_IPERF0_P5 in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_IPERF0_P5  0x00000E09\r
\r
/**\r
  Package. Uncore R-box 0 perfmon IPERF0 unit Port 6 select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_IPERF0_P6 (0x00000E0A)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P6, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_IPERF0_P6 is defined as MSR_R0_PMON_IPERF0_P6 in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_IPERF0_P6  0x00000E0A\r
\r
/**\r
  Package. Uncore R-box 0 perfmon IPERF0 unit Port 7 select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_IPERF0_P7 (0x00000E0B)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_IPERF0_P7, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_IPERF0_P7 is defined as MSR_R0_PMON_IPERF0_P7 in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_IPERF0_P7  0x00000E0B\r
\r
/**\r
  Package. Uncore R-box 0 perfmon QLX unit Port 0 select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_QLX_P0 (0x00000E0C)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_QLX_P0 is defined as MSR_R0_PMON_QLX_P0 in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_QLX_P0  0x00000E0C\r
\r
/**\r
  Package. Uncore R-box 0 perfmon QLX unit Port 1 select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_QLX_P1 (0x00000E0D)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_QLX_P1 is defined as MSR_R0_PMON_QLX_P1 in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_QLX_P1  0x00000E0D\r
\r
/**\r
  Package. Uncore R-box 0 perfmon QLX unit Port 2 select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_QLX_P2 (0x00000E0E)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_QLX_P2 is defined as MSR_R0_PMON_QLX_P2 in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_QLX_P2  0x00000E0E\r
\r
/**\r
  Package. Uncore R-box 0 perfmon QLX unit Port 3 select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_QLX_P3 (0x00000E0F)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_QLX_P3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_QLX_P3 is defined as MSR_R0_PMON_QLX_P3 in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_QLX_P3  0x00000E0F\r
\r
/**\r
  Package. Uncore R-box 0 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_EVNT_SEL0 (0x00000E10)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_EVNT_SEL0 is defined as MSR_R0_PMON_EVNT_SEL0 in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_EVNT_SEL0  0x00000E10\r
\r
/**\r
  Package. Uncore R-box 0 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_CTR0 (0x00000E11)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR0);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR0, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_CTR0 is defined as MSR_R0_PMON_CTR0 in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_CTR0  0x00000E11\r
\r
/**\r
  Package. Uncore R-box 0 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_EVNT_SEL1 (0x00000E12)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_EVNT_SEL1 is defined as MSR_R0_PMON_EVNT_SEL1 in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_EVNT_SEL1  0x00000E12\r
\r
/**\r
  Package. Uncore R-box 0 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_CTR1 (0x00000E13)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR1);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR1, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_CTR1 is defined as MSR_R0_PMON_CTR1 in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_CTR1  0x00000E13\r
\r
/**\r
  Package. Uncore R-box 0 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_EVNT_SEL2 (0x00000E14)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_EVNT_SEL2 is defined as MSR_R0_PMON_EVNT_SEL2 in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_EVNT_SEL2  0x00000E14\r
\r
/**\r
  Package. Uncore R-box 0 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_CTR2 (0x00000E15)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR2);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR2, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_CTR2 is defined as MSR_R0_PMON_CTR2 in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_CTR2  0x00000E15\r
\r
/**\r
  Package. Uncore R-box 0 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_EVNT_SEL3 (0x00000E16)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_EVNT_SEL3 is defined as MSR_R0_PMON_EVNT_SEL3 in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_EVNT_SEL3  0x00000E16\r
\r
/**\r
  Package. Uncore R-box 0 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_CTR3 (0x00000E17)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR3);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR3, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_CTR3 is defined as MSR_R0_PMON_CTR3 in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_CTR3  0x00000E17\r
\r
/**\r
  Package. Uncore R-box 0 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_EVNT_SEL4 (0x00000E18)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL4, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_EVNT_SEL4 is defined as MSR_R0_PMON_EVNT_SEL4 in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_EVNT_SEL4  0x00000E18\r
\r
/**\r
  Package. Uncore R-box 0 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_CTR4 (0x00000E19)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR4);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR4, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_CTR4 is defined as MSR_R0_PMON_CTR4 in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_CTR4  0x00000E19\r
\r
/**\r
  Package. Uncore R-box 0 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_EVNT_SEL5 (0x00000E1A)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL5, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_EVNT_SEL5 is defined as MSR_R0_PMON_EVNT_SEL5 in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_EVNT_SEL5  0x00000E1A\r
\r
/**\r
  Package. Uncore R-box 0 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_CTR5 (0x00000E1B)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR5);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR5, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_CTR5 is defined as MSR_R0_PMON_CTR5 in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_CTR5  0x00000E1B\r
\r
/**\r
  Package. Uncore R-box 0 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_EVNT_SEL6 (0x00000E1C)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL6, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_EVNT_SEL6 is defined as MSR_R0_PMON_EVNT_SEL6 in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_EVNT_SEL6  0x00000E1C\r
\r
/**\r
  Package. Uncore R-box 0 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_CTR6 (0x00000E1D)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR6);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR6, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_CTR6 is defined as MSR_R0_PMON_CTR6 in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_CTR6  0x00000E1D\r
\r
/**\r
  Package. Uncore R-box 0 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_EVNT_SEL7 (0x00000E1E)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_EVNT_SEL7, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_EVNT_SEL7 is defined as MSR_R0_PMON_EVNT_SEL7 in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_EVNT_SEL7  0x00000E1E\r
\r
/**\r
  Package. Uncore R-box 0 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R0_PMON_CTR7 (0x00000E1F)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R0_PMON_CTR7);\r
  AsmWriteMsr64 (MSR_NEHALEM_R0_PMON_CTR7, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R0_PMON_CTR7 is defined as MSR_R0_PMON_CTR7 in SDM.\r
**/\r
#define MSR_NEHALEM_R0_PMON_CTR7  0x00000E1F\r
\r
/**\r
  Package. Uncore R-box 1 perfmon local box control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_BOX_CTRL (0x00000E20)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_BOX_CTRL is defined as MSR_R1_PMON_BOX_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_BOX_CTRL  0x00000E20\r
\r
/**\r
  Package. Uncore R-box 1 perfmon local box status MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_BOX_STATUS (0x00000E21)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_STATUS, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_BOX_STATUS is defined as MSR_R1_PMON_BOX_STATUS in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_BOX_STATUS  0x00000E21\r
\r
/**\r
  Package. Uncore R-box 1 perfmon local box overflow control MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL (0x00000E22)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL is defined as MSR_R1_PMON_BOX_OVF_CTRL in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_BOX_OVF_CTRL  0x00000E22\r
\r
/**\r
  Package. Uncore R-box 1 perfmon IPERF1 unit Port 8 select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_IPERF1_P8 (0x00000E24)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P8, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_IPERF1_P8 is defined as MSR_R1_PMON_IPERF1_P8 in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_IPERF1_P8  0x00000E24\r
\r
/**\r
  Package. Uncore R-box 1 perfmon IPERF1 unit Port 9 select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_IPERF1_P9 (0x00000E25)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P9, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_IPERF1_P9 is defined as MSR_R1_PMON_IPERF1_P9 in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_IPERF1_P9  0x00000E25\r
\r
/**\r
  Package. Uncore R-box 1 perfmon IPERF1 unit Port 10 select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_IPERF1_P10 (0x00000E26)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P10, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_IPERF1_P10 is defined as MSR_R1_PMON_IPERF1_P10 in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_IPERF1_P10  0x00000E26\r
\r
/**\r
  Package. Uncore R-box 1 perfmon IPERF1 unit Port 11 select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_IPERF1_P11 (0x00000E27)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P11, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_IPERF1_P11 is defined as MSR_R1_PMON_IPERF1_P11 in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_IPERF1_P11  0x00000E27\r
\r
/**\r
  Package. Uncore R-box 1 perfmon IPERF1 unit Port 12 select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_IPERF1_P12 (0x00000E28)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P12, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_IPERF1_P12 is defined as MSR_R1_PMON_IPERF1_P12 in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_IPERF1_P12  0x00000E28\r
\r
/**\r
  Package. Uncore R-box 1 perfmon IPERF1 unit Port 13 select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_IPERF1_P13 (0x00000E29)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P13, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_IPERF1_P13 is defined as MSR_R1_PMON_IPERF1_P13 in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_IPERF1_P13  0x00000E29\r
\r
/**\r
  Package. Uncore R-box 1 perfmon IPERF1 unit Port 14 select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_IPERF1_P14 (0x00000E2A)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P14, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_IPERF1_P14 is defined as MSR_R1_PMON_IPERF1_P14 in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_IPERF1_P14  0x00000E2A\r
\r
/**\r
  Package. Uncore R-box 1 perfmon IPERF1 unit Port 15 select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_IPERF1_P15 (0x00000E2B)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_IPERF1_P15, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_IPERF1_P15 is defined as MSR_R1_PMON_IPERF1_P15 in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_IPERF1_P15  0x00000E2B\r
\r
/**\r
  Package. Uncore R-box 1 perfmon QLX unit Port 4 select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_QLX_P4 (0x00000E2C)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P4, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_QLX_P4 is defined as MSR_R1_PMON_QLX_P4 in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_QLX_P4  0x00000E2C\r
\r
/**\r
  Package. Uncore R-box 1 perfmon QLX unit Port 5 select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_QLX_P5 (0x00000E2D)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P5, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_QLX_P5 is defined as MSR_R1_PMON_QLX_P5 in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_QLX_P5  0x00000E2D\r
\r
/**\r
  Package. Uncore R-box 1 perfmon QLX unit Port 6 select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_QLX_P6 (0x00000E2E)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P6, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_QLX_P6 is defined as MSR_R1_PMON_QLX_P6 in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_QLX_P6  0x00000E2E\r
\r
/**\r
  Package. Uncore R-box 1 perfmon QLX unit Port 7 select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_QLX_P7 (0x00000E2F)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_QLX_P7, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_QLX_P7 is defined as MSR_R1_PMON_QLX_P7 in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_QLX_P7  0x00000E2F\r
\r
/**\r
  Package. Uncore R-box 1 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_EVNT_SEL8 (0x00000E30)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL8, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_EVNT_SEL8 is defined as MSR_R1_PMON_EVNT_SEL8 in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_EVNT_SEL8  0x00000E30\r
\r
/**\r
  Package. Uncore R-box 1 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_CTR8 (0x00000E31)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR8);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR8, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_CTR8 is defined as MSR_R1_PMON_CTR8 in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_CTR8  0x00000E31\r
\r
/**\r
  Package. Uncore R-box 1 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_EVNT_SEL9 (0x00000E32)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL9, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_EVNT_SEL9 is defined as MSR_R1_PMON_EVNT_SEL9 in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_EVNT_SEL9  0x00000E32\r
\r
/**\r
  Package. Uncore R-box 1 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_CTR9 (0x00000E33)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR9);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR9, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_CTR9 is defined as MSR_R1_PMON_CTR9 in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_CTR9  0x00000E33\r
\r
/**\r
  Package. Uncore R-box 1 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_EVNT_SEL10 (0x00000E34)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL10, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_EVNT_SEL10 is defined as MSR_R1_PMON_EVNT_SEL10 in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_EVNT_SEL10  0x00000E34\r
\r
/**\r
  Package. Uncore R-box 1 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_CTR10 (0x00000E35)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR10);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR10, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_CTR10 is defined as MSR_R1_PMON_CTR10 in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_CTR10  0x00000E35\r
\r
/**\r
  Package. Uncore R-box 1 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_EVNT_SEL11 (0x00000E36)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL11, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_EVNT_SEL11 is defined as MSR_R1_PMON_EVNT_SEL11 in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_EVNT_SEL11  0x00000E36\r
\r
/**\r
  Package. Uncore R-box 1 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_CTR11 (0x00000E37)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR11);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR11, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_CTR11 is defined as MSR_R1_PMON_CTR11 in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_CTR11  0x00000E37\r
\r
/**\r
  Package. Uncore R-box 1 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_EVNT_SEL12 (0x00000E38)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL12, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_EVNT_SEL12 is defined as MSR_R1_PMON_EVNT_SEL12 in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_EVNT_SEL12  0x00000E38\r
\r
/**\r
  Package. Uncore R-box 1 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_CTR12 (0x00000E39)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR12);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR12, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_CTR12 is defined as MSR_R1_PMON_CTR12 in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_CTR12  0x00000E39\r
\r
/**\r
  Package. Uncore R-box 1 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_EVNT_SEL13 (0x00000E3A)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL13, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_EVNT_SEL13 is defined as MSR_R1_PMON_EVNT_SEL13 in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_EVNT_SEL13  0x00000E3A\r
\r
/**\r
  Package. Uncore R-box 1perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_CTR13 (0x00000E3B)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR13);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR13, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_CTR13 is defined as MSR_R1_PMON_CTR13 in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_CTR13  0x00000E3B\r
\r
/**\r
  Package. Uncore R-box 1 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_EVNT_SEL14 (0x00000E3C)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL14, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_EVNT_SEL14 is defined as MSR_R1_PMON_EVNT_SEL14 in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_EVNT_SEL14  0x00000E3C\r
\r
/**\r
  Package. Uncore R-box 1 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_CTR14 (0x00000E3D)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR14);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR14, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_CTR14 is defined as MSR_R1_PMON_CTR14 in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_CTR14  0x00000E3D\r
\r
/**\r
  Package. Uncore R-box 1 perfmon event select MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_EVNT_SEL15 (0x00000E3E)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_EVNT_SEL15, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_EVNT_SEL15 is defined as MSR_R1_PMON_EVNT_SEL15 in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_EVNT_SEL15  0x00000E3E\r
\r
/**\r
  Package. Uncore R-box 1 perfmon counter MSR.\r
\r
  @param  ECX  MSR_NEHALEM_R1_PMON_CTR15 (0x00000E3F)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_R1_PMON_CTR15);\r
  AsmWriteMsr64 (MSR_NEHALEM_R1_PMON_CTR15, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_R1_PMON_CTR15 is defined as MSR_R1_PMON_CTR15 in SDM.\r
**/\r
#define MSR_NEHALEM_R1_PMON_CTR15  0x00000E3F\r
\r
/**\r
  Package. Uncore B-box 0 perfmon local box match MSR.\r
\r
  @param  ECX  MSR_NEHALEM_B0_PMON_MATCH (0x00000E45)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MATCH);\r
  AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MATCH, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_B0_PMON_MATCH is defined as MSR_B0_PMON_MATCH in SDM.\r
**/\r
#define MSR_NEHALEM_B0_PMON_MATCH  0x00000E45\r
\r
/**\r
  Package. Uncore B-box 0 perfmon local box mask MSR.\r
\r
  @param  ECX  MSR_NEHALEM_B0_PMON_MASK (0x00000E46)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_B0_PMON_MASK);\r
  AsmWriteMsr64 (MSR_NEHALEM_B0_PMON_MASK, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_B0_PMON_MASK is defined as MSR_B0_PMON_MASK in SDM.\r
**/\r
#define MSR_NEHALEM_B0_PMON_MASK  0x00000E46\r
\r
/**\r
  Package. Uncore S-box 0 perfmon local box match MSR.\r
\r
  @param  ECX  MSR_NEHALEM_S0_PMON_MATCH (0x00000E49)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MATCH);\r
  AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MATCH, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_S0_PMON_MATCH is defined as MSR_S0_PMON_MATCH in SDM.\r
**/\r
#define MSR_NEHALEM_S0_PMON_MATCH  0x00000E49\r
\r
/**\r
  Package. Uncore S-box 0 perfmon local box mask MSR.\r
\r
  @param  ECX  MSR_NEHALEM_S0_PMON_MASK (0x00000E4A)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_S0_PMON_MASK);\r
  AsmWriteMsr64 (MSR_NEHALEM_S0_PMON_MASK, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_S0_PMON_MASK is defined as MSR_S0_PMON_MASK in SDM.\r
**/\r
#define MSR_NEHALEM_S0_PMON_MASK  0x00000E4A\r
\r
/**\r
  Package. Uncore B-box 1 perfmon local box match MSR.\r
\r
  @param  ECX  MSR_NEHALEM_B1_PMON_MATCH (0x00000E4D)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MATCH);\r
  AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MATCH, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_B1_PMON_MATCH is defined as MSR_B1_PMON_MATCH in SDM.\r
**/\r
#define MSR_NEHALEM_B1_PMON_MATCH  0x00000E4D\r
\r
/**\r
  Package. Uncore B-box 1 perfmon local box mask MSR.\r
\r
  @param  ECX  MSR_NEHALEM_B1_PMON_MASK (0x00000E4E)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_B1_PMON_MASK);\r
  AsmWriteMsr64 (MSR_NEHALEM_B1_PMON_MASK, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_B1_PMON_MASK is defined as MSR_B1_PMON_MASK in SDM.\r
**/\r
#define MSR_NEHALEM_B1_PMON_MASK  0x00000E4E\r
\r
/**\r
  Package. Uncore M-box 0 perfmon local box address match/mask config MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M0_PMON_MM_CONFIG (0x00000E54)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG);\r
  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_MM_CONFIG, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M0_PMON_MM_CONFIG is defined as MSR_M0_PMON_MM_CONFIG in SDM.\r
**/\r
#define MSR_NEHALEM_M0_PMON_MM_CONFIG  0x00000E54\r
\r
/**\r
  Package. Uncore M-box 0 perfmon local box address match MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M0_PMON_ADDR_MATCH (0x00000E55)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH);\r
  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MATCH, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M0_PMON_ADDR_MATCH is defined as MSR_M0_PMON_ADDR_MATCH in SDM.\r
**/\r
#define MSR_NEHALEM_M0_PMON_ADDR_MATCH  0x00000E55\r
\r
/**\r
  Package. Uncore M-box 0 perfmon local box address mask MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M0_PMON_ADDR_MASK (0x00000E56)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK);\r
  AsmWriteMsr64 (MSR_NEHALEM_M0_PMON_ADDR_MASK, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M0_PMON_ADDR_MASK is defined as MSR_M0_PMON_ADDR_MASK in SDM.\r
**/\r
#define MSR_NEHALEM_M0_PMON_ADDR_MASK  0x00000E56\r
\r
/**\r
  Package. Uncore S-box 1 perfmon local box match MSR.\r
\r
  @param  ECX  MSR_NEHALEM_S1_PMON_MATCH (0x00000E59)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MATCH);\r
  AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MATCH, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_S1_PMON_MATCH is defined as MSR_S1_PMON_MATCH in SDM.\r
**/\r
#define MSR_NEHALEM_S1_PMON_MATCH  0x00000E59\r
\r
/**\r
  Package. Uncore S-box 1 perfmon local box mask MSR.\r
\r
  @param  ECX  MSR_NEHALEM_S1_PMON_MASK (0x00000E5A)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_S1_PMON_MASK);\r
  AsmWriteMsr64 (MSR_NEHALEM_S1_PMON_MASK, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_S1_PMON_MASK is defined as MSR_S1_PMON_MASK in SDM.\r
**/\r
#define MSR_NEHALEM_S1_PMON_MASK  0x00000E5A\r
\r
/**\r
  Package. Uncore M-box 1 perfmon local box address match/mask config MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M1_PMON_MM_CONFIG (0x00000E5C)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG);\r
  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_MM_CONFIG, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M1_PMON_MM_CONFIG is defined as MSR_M1_PMON_MM_CONFIG in SDM.\r
**/\r
#define MSR_NEHALEM_M1_PMON_MM_CONFIG  0x00000E5C\r
\r
/**\r
  Package. Uncore M-box 1 perfmon local box address match MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M1_PMON_ADDR_MATCH (0x00000E5D)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH);\r
  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MATCH, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M1_PMON_ADDR_MATCH is defined as MSR_M1_PMON_ADDR_MATCH in SDM.\r
**/\r
#define MSR_NEHALEM_M1_PMON_ADDR_MATCH  0x00000E5D\r
\r
/**\r
  Package. Uncore M-box 1 perfmon local box address mask MSR.\r
\r
  @param  ECX  MSR_NEHALEM_M1_PMON_ADDR_MASK (0x00000E5E)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK);\r
  AsmWriteMsr64 (MSR_NEHALEM_M1_PMON_ADDR_MASK, Msr);\r
  @endcode\r
  @note MSR_NEHALEM_M1_PMON_ADDR_MASK is defined as MSR_M1_PMON_ADDR_MASK in SDM.\r
**/\r
#define MSR_NEHALEM_M1_PMON_ADDR_MASK  0x00000E5E\r
\r
#endif\r