]>
Commit | Line | Data |
---|---|---|
f4d9afde MK |
1 | /** @file\r |
2 | MSR Definitions for Pentium(R) 4 Processors.\r | |
3 | \r | |
4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
7 | provided for that MSR.\r | |
8 | \r | |
e057908f | 9 | Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r |
0acd8697 | 10 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
f4d9afde MK |
11 | \r |
12 | @par Specification Reference:\r | |
ba1a2d11 ED |
13 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r |
14 | May 2018, Volume 4: Model-Specific-Registers (MSR)\r | |
f4d9afde MK |
15 | \r |
16 | **/\r | |
17 | \r | |
18 | #ifndef __PENTIUM_4_MSR_H__\r | |
19 | #define __PENTIUM_4_MSR_H__\r | |
20 | \r | |
e057908f | 21 | #include <Register/Intel/ArchitecturalMsr.h>\r |
f4d9afde | 22 | \r |
f4c982bf JF |
23 | /**\r |
24 | Is Pentium(R) 4 Processors?\r | |
25 | \r | |
26 | @param DisplayFamily Display Family ID\r | |
27 | @param DisplayModel Display Model ID\r | |
28 | \r | |
29 | @retval TRUE Yes, it is.\r | |
30 | @retval FALSE No, it isn't.\r | |
31 | **/\r | |
32 | #define IS_PENTIUM_4_PROCESSOR(DisplayFamily, DisplayModel) \\r | |
33 | (DisplayFamily == 0x0F \\r | |
34 | )\r | |
35 | \r | |
f4d9afde MK |
36 | /**\r |
37 | 3, 4, 6. Shared. See Section 8.10.5, "Monitor/Mwait Address Range\r | |
38 | Determination.".\r | |
39 | \r | |
40 | @param ECX MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE (0x00000006)\r | |
41 | @param EAX Lower 32-bits of MSR value.\r | |
42 | @param EDX Upper 32-bits of MSR value.\r | |
43 | \r | |
44 | <b>Example usage</b>\r | |
45 | @code\r | |
46 | UINT64 Msr;\r | |
47 | \r | |
48 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE);\r | |
49 | AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE, Msr);\r | |
50 | @endcode\r | |
8bf98bd0 | 51 | @note MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE is defined as IA32_MONITOR_FILTER_LINE_SIZE in SDM.\r |
f4d9afde | 52 | **/\r |
2f88bd3a | 53 | #define MSR_PENTIUM_4_IA32_MONITOR_FILTER_LINE_SIZE 0x00000006\r |
f4d9afde MK |
54 | \r |
55 | /**\r | |
56 | 0, 1, 2, 3, 4, 6. Shared. Processor Hard Power-On Configuration (R/W)\r | |
57 | Enables and disables processor features; (R) indicates current processor\r | |
58 | configuration.\r | |
59 | \r | |
60 | @param ECX MSR_PENTIUM_4_EBC_HARD_POWERON (0x0000002A)\r | |
61 | @param EAX Lower 32-bits of MSR value.\r | |
62 | Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER.\r | |
63 | @param EDX Upper 32-bits of MSR value.\r | |
64 | Described by the type MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER.\r | |
65 | \r | |
66 | <b>Example usage</b>\r | |
67 | @code\r | |
68 | MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER Msr;\r | |
69 | \r | |
70 | Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON);\r | |
71 | AsmWriteMsr64 (MSR_PENTIUM_4_EBC_HARD_POWERON, Msr.Uint64);\r | |
72 | @endcode\r | |
8bf98bd0 | 73 | @note MSR_PENTIUM_4_EBC_HARD_POWERON is defined as MSR_EBC_HARD_POWERON in SDM.\r |
f4d9afde | 74 | **/\r |
2f88bd3a | 75 | #define MSR_PENTIUM_4_EBC_HARD_POWERON 0x0000002A\r |
f4d9afde MK |
76 | \r |
77 | /**\r | |
78 | MSR information returned for MSR index #MSR_PENTIUM_4_EBC_HARD_POWERON\r | |
79 | **/\r | |
80 | typedef union {\r | |
81 | ///\r | |
82 | /// Individual bit fields\r | |
83 | ///\r | |
84 | struct {\r | |
85 | ///\r | |
86 | /// [Bit 0] Output Tri-state Enabled (R) Indicates whether tri-state\r | |
87 | /// output is enabled (1) or disabled (0) as set by the strapping of SMI#.\r | |
88 | /// The value in this bit is written on the deassertion of RESET#; the bit\r | |
89 | /// is set to 1 when the address bus signal is asserted.\r | |
90 | ///\r | |
2f88bd3a | 91 | UINT32 OutputTriStateEnabled : 1;\r |
f4d9afde MK |
92 | ///\r |
93 | /// [Bit 1] Execute BIST (R) Indicates whether the execution of the BIST\r | |
94 | /// is enabled (1) or disabled (0) as set by the strapping of INIT#. The\r | |
95 | /// value in this bit is written on the deassertion of RESET#; the bit is\r | |
96 | /// set to 1 when the address bus signal is asserted.\r | |
97 | ///\r | |
2f88bd3a | 98 | UINT32 ExecuteBIST : 1;\r |
f4d9afde MK |
99 | ///\r |
100 | /// [Bit 2] In Order Queue Depth (R) Indicates whether the in order queue\r | |
101 | /// depth for the system bus is 1 (1) or up to 12 (0) as set by the\r | |
102 | /// strapping of A7#. The value in this bit is written on the deassertion\r | |
103 | /// of RESET#; the bit is set to 1 when the address bus signal is asserted.\r | |
104 | ///\r | |
2f88bd3a | 105 | UINT32 InOrderQueueDepth : 1;\r |
f4d9afde MK |
106 | ///\r |
107 | /// [Bit 3] MCERR# Observation Disabled (R) Indicates whether MCERR#\r | |
108 | /// observation is enabled (0) or disabled (1) as determined by the\r | |
109 | /// strapping of A9#. The value in this bit is written on the deassertion\r | |
110 | /// of RESET#; the bit is set to 1 when the address bus signal is asserted.\r | |
111 | ///\r | |
2f88bd3a | 112 | UINT32 MCERR_ObservationDisabled : 1;\r |
f4d9afde MK |
113 | ///\r |
114 | /// [Bit 4] BINIT# Observation Enabled (R) Indicates whether BINIT#\r | |
115 | /// observation is enabled (0) or disabled (1) as determined by the\r | |
116 | /// strapping of A10#. The value in this bit is written on the deassertion\r | |
117 | /// of RESET#; the bit is set to 1 when the address bus signal is asserted.\r | |
118 | ///\r | |
2f88bd3a | 119 | UINT32 BINIT_ObservationEnabled : 1;\r |
f4d9afde MK |
120 | ///\r |
121 | /// [Bits 6:5] APIC Cluster ID (R) Contains the logical APIC cluster ID\r | |
122 | /// value as set by the strapping of A12# and A11#. The logical cluster ID\r | |
123 | /// value is written into the field on the deassertion of RESET#; the\r | |
124 | /// field is set to 1 when the address bus signal is asserted.\r | |
125 | ///\r | |
2f88bd3a | 126 | UINT32 APICClusterID : 2;\r |
f4d9afde MK |
127 | ///\r |
128 | /// [Bit 7] Bus Park Disable (R) Indicates whether bus park is enabled\r | |
129 | /// (0) or disabled (1) as set by the strapping of A15#. The value in this\r | |
130 | /// bit is written on the deassertion of RESET#; the bit is set to 1 when\r | |
131 | /// the address bus signal is asserted.\r | |
132 | ///\r | |
2f88bd3a MK |
133 | UINT32 BusParkDisable : 1;\r |
134 | UINT32 Reserved1 : 4;\r | |
f4d9afde MK |
135 | ///\r |
136 | /// [Bits 13:12] Agent ID (R) Contains the logical agent ID value as set\r | |
137 | /// by the strapping of BR[3:0]. The logical ID value is written into the\r | |
138 | /// field on the deassertion of RESET#; the field is set to 1 when the\r | |
139 | /// address bus signal is asserted.\r | |
140 | ///\r | |
2f88bd3a MK |
141 | UINT32 AgentID : 2;\r |
142 | UINT32 Reserved2 : 18;\r | |
143 | UINT32 Reserved3 : 32;\r | |
f4d9afde MK |
144 | } Bits;\r |
145 | ///\r | |
146 | /// All bit fields as a 32-bit value\r | |
147 | ///\r | |
2f88bd3a | 148 | UINT32 Uint32;\r |
f4d9afde MK |
149 | ///\r |
150 | /// All bit fields as a 64-bit value\r | |
151 | ///\r | |
2f88bd3a | 152 | UINT64 Uint64;\r |
f4d9afde MK |
153 | } MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER;\r |
154 | \r | |
f4d9afde MK |
155 | /**\r |
156 | 0, 1, 2, 3, 4, 6. Shared. Processor Soft Power-On Configuration (R/W)\r | |
157 | Enables and disables processor features.\r | |
158 | \r | |
159 | @param ECX MSR_PENTIUM_4_EBC_SOFT_POWERON (0x0000002B)\r | |
160 | @param EAX Lower 32-bits of MSR value.\r | |
161 | Described by the type MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER.\r | |
162 | @param EDX Upper 32-bits of MSR value.\r | |
163 | Described by the type MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER.\r | |
164 | \r | |
165 | <b>Example usage</b>\r | |
166 | @code\r | |
167 | MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER Msr;\r | |
168 | \r | |
169 | Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON);\r | |
170 | AsmWriteMsr64 (MSR_PENTIUM_4_EBC_SOFT_POWERON, Msr.Uint64);\r | |
171 | @endcode\r | |
8bf98bd0 | 172 | @note MSR_PENTIUM_4_EBC_SOFT_POWERON is defined as MSR_EBC_SOFT_POWERON in SDM.\r |
f4d9afde | 173 | **/\r |
2f88bd3a | 174 | #define MSR_PENTIUM_4_EBC_SOFT_POWERON 0x0000002B\r |
f4d9afde MK |
175 | \r |
176 | /**\r | |
177 | MSR information returned for MSR index #MSR_PENTIUM_4_EBC_SOFT_POWERON\r | |
178 | **/\r | |
179 | typedef union {\r | |
180 | ///\r | |
181 | /// Individual bit fields\r | |
182 | ///\r | |
183 | struct {\r | |
184 | ///\r | |
185 | /// [Bit 0] RCNT/SCNT On Request Encoding Enable (R/W) Controls the\r | |
186 | /// driving of RCNT/SCNT on the request encoding. Set to enable (1); clear\r | |
187 | /// to disabled (0, default).\r | |
188 | ///\r | |
2f88bd3a | 189 | UINT32 RCNT_SCNT : 1;\r |
f4d9afde MK |
190 | ///\r |
191 | /// [Bit 1] Data Error Checking Disable (R/W) Set to disable system data\r | |
192 | /// bus parity checking; clear to enable parity checking.\r | |
193 | ///\r | |
2f88bd3a | 194 | UINT32 DataErrorCheckingDisable : 1;\r |
f4d9afde MK |
195 | ///\r |
196 | /// [Bit 2] Response Error Checking Disable (R/W) Set to disable\r | |
197 | /// (default); clear to enable.\r | |
198 | ///\r | |
2f88bd3a | 199 | UINT32 ResponseErrorCheckingDisable : 1;\r |
f4d9afde MK |
200 | ///\r |
201 | /// [Bit 3] Address/Request Error Checking Disable (R/W) Set to disable\r | |
202 | /// (default); clear to enable.\r | |
203 | ///\r | |
2f88bd3a | 204 | UINT32 AddressRequestErrorCheckingDisable : 1;\r |
f4d9afde MK |
205 | ///\r |
206 | /// [Bit 4] Initiator MCERR# Disable (R/W) Set to disable MCERR# driving\r | |
207 | /// for initiator bus requests (default); clear to enable.\r | |
208 | ///\r | |
2f88bd3a | 209 | UINT32 InitiatorMCERR_Disable : 1;\r |
f4d9afde MK |
210 | ///\r |
211 | /// [Bit 5] Internal MCERR# Disable (R/W) Set to disable MCERR# driving\r | |
212 | /// for initiator internal errors (default); clear to enable.\r | |
213 | ///\r | |
2f88bd3a | 214 | UINT32 InternalMCERR_Disable : 1;\r |
f4d9afde MK |
215 | ///\r |
216 | /// [Bit 6] BINIT# Driver Disable (R/W) Set to disable BINIT# driver\r | |
217 | /// (default); clear to enable driver.\r | |
218 | ///\r | |
2f88bd3a MK |
219 | UINT32 BINIT_DriverDisable : 1;\r |
220 | UINT32 Reserved1 : 25;\r | |
221 | UINT32 Reserved2 : 32;\r | |
f4d9afde MK |
222 | } Bits;\r |
223 | ///\r | |
224 | /// All bit fields as a 32-bit value\r | |
225 | ///\r | |
2f88bd3a | 226 | UINT32 Uint32;\r |
f4d9afde MK |
227 | ///\r |
228 | /// All bit fields as a 64-bit value\r | |
229 | ///\r | |
2f88bd3a | 230 | UINT64 Uint64;\r |
f4d9afde MK |
231 | } MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER;\r |
232 | \r | |
f4d9afde MK |
233 | /**\r |
234 | 2,3, 4, 6. Shared. Processor Frequency Configuration The bit field layout of\r | |
235 | this MSR varies according to the MODEL value in the CPUID version\r | |
236 | information. The following bit field layout applies to Pentium 4 and Xeon\r | |
237 | Processors with MODEL encoding equal or greater than 2. (R) The field\r | |
238 | Indicates the current processor frequency configuration.\r | |
239 | \r | |
240 | @param ECX MSR_PENTIUM_4_EBC_FREQUENCY_ID (0x0000002C)\r | |
241 | @param EAX Lower 32-bits of MSR value.\r | |
242 | Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER.\r | |
243 | @param EDX Upper 32-bits of MSR value.\r | |
244 | Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER.\r | |
245 | \r | |
246 | <b>Example usage</b>\r | |
247 | @code\r | |
248 | MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER Msr;\r | |
249 | \r | |
250 | Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID);\r | |
251 | @endcode\r | |
8bf98bd0 | 252 | @note MSR_PENTIUM_4_EBC_FREQUENCY_ID is defined as MSR_EBC_FREQUENCY_ID in SDM.\r |
f4d9afde | 253 | **/\r |
2f88bd3a | 254 | #define MSR_PENTIUM_4_EBC_FREQUENCY_ID 0x0000002C\r |
f4d9afde MK |
255 | \r |
256 | /**\r | |
257 | MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID\r | |
258 | **/\r | |
259 | typedef union {\r | |
260 | ///\r | |
261 | /// Individual bit fields\r | |
262 | ///\r | |
263 | struct {\r | |
2f88bd3a | 264 | UINT32 Reserved1 : 16;\r |
f4d9afde MK |
265 | ///\r |
266 | /// [Bits 18:16] Scalable Bus Speed (R/W) Indicates the intended scalable\r | |
267 | /// bus speed: *EncodingScalable Bus Speed*\r | |
268 | ///\r | |
269 | /// 000B 100 MHz (Model 2).\r | |
270 | /// 000B 266 MHz (Model 3 or 4)\r | |
271 | /// 001B 133 MHz\r | |
272 | /// 010B 200 MHz\r | |
273 | /// 011B 166 MHz\r | |
274 | /// 100B 333 MHz (Model 6)\r | |
275 | ///\r | |
276 | /// 133.33 MHz should be utilized if performing calculation with System\r | |
277 | /// Bus Speed when encoding is 001B. 166.67 MHz should be utilized if\r | |
278 | /// performing calculation with System Bus Speed when encoding is 011B.\r | |
279 | /// 266.67 MHz should be utilized if performing calculation with System\r | |
280 | /// Bus Speed when encoding is 000B and model encoding = 3 or 4. 333.33\r | |
281 | /// MHz should be utilized if performing calculation with System Bus\r | |
282 | /// Speed when encoding is 100B and model encoding = 6. All other values\r | |
283 | /// are reserved.\r | |
284 | ///\r | |
2f88bd3a MK |
285 | UINT32 ScalableBusSpeed : 3;\r |
286 | UINT32 Reserved2 : 5;\r | |
f4d9afde MK |
287 | ///\r |
288 | /// [Bits 31:24] Core Clock Frequency to System Bus Frequency Ratio (R)\r | |
289 | /// The processor core clock frequency to system bus frequency ratio\r | |
290 | /// observed at the de-assertion of the reset pin.\r | |
291 | ///\r | |
2f88bd3a MK |
292 | UINT32 ClockRatio : 8;\r |
293 | UINT32 Reserved3 : 32;\r | |
f4d9afde MK |
294 | } Bits;\r |
295 | ///\r | |
296 | /// All bit fields as a 32-bit value\r | |
297 | ///\r | |
2f88bd3a | 298 | UINT32 Uint32;\r |
f4d9afde MK |
299 | ///\r |
300 | /// All bit fields as a 64-bit value\r | |
301 | ///\r | |
2f88bd3a | 302 | UINT64 Uint64;\r |
f4d9afde MK |
303 | } MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER;\r |
304 | \r | |
f4d9afde MK |
305 | /**\r |
306 | 0, 1. Shared. Processor Frequency Configuration (R) The bit field layout of\r | |
307 | this MSR varies according to the MODEL value of the CPUID version\r | |
308 | information. This bit field layout applies to Pentium 4 and Xeon Processors\r | |
309 | with MODEL encoding less than 2. Indicates current processor frequency\r | |
310 | configuration.\r | |
311 | \r | |
312 | @param ECX MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 (0x0000002C)\r | |
313 | @param EAX Lower 32-bits of MSR value.\r | |
314 | Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER.\r | |
315 | @param EDX Upper 32-bits of MSR value.\r | |
316 | Described by the type MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER.\r | |
317 | \r | |
318 | <b>Example usage</b>\r | |
319 | @code\r | |
320 | MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER Msr;\r | |
321 | \r | |
322 | Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_EBC_FREQUENCY_ID_1);\r | |
323 | @endcode\r | |
8bf98bd0 | 324 | @note MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 is defined as MSR_EBC_FREQUENCY_ID_1 in SDM.\r |
f4d9afde | 325 | **/\r |
2f88bd3a | 326 | #define MSR_PENTIUM_4_EBC_FREQUENCY_ID_1 0x0000002C\r |
f4d9afde MK |
327 | \r |
328 | /**\r | |
329 | MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID_1\r | |
330 | **/\r | |
331 | typedef union {\r | |
332 | ///\r | |
333 | /// Individual bit fields\r | |
334 | ///\r | |
335 | struct {\r | |
2f88bd3a | 336 | UINT32 Reserved1 : 21;\r |
f4d9afde MK |
337 | ///\r |
338 | /// [Bits 23:21] Scalable Bus Speed (R/W) Indicates the intended scalable\r | |
339 | /// bus speed: *Encoding* *Scalable Bus Speed*\r | |
340 | ///\r | |
341 | /// 000B 100 MHz All others values reserved.\r | |
342 | ///\r | |
2f88bd3a MK |
343 | UINT32 ScalableBusSpeed : 3;\r |
344 | UINT32 Reserved2 : 8;\r | |
345 | UINT32 Reserved3 : 32;\r | |
f4d9afde MK |
346 | } Bits;\r |
347 | ///\r | |
348 | /// All bit fields as a 32-bit value\r | |
349 | ///\r | |
2f88bd3a | 350 | UINT32 Uint32;\r |
f4d9afde MK |
351 | ///\r |
352 | /// All bit fields as a 64-bit value\r | |
353 | ///\r | |
2f88bd3a | 354 | UINT64 Uint64;\r |
f4d9afde MK |
355 | } MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER;\r |
356 | \r | |
f4d9afde MK |
357 | /**\r |
358 | 0, 1, 2, 3, 4, 6. Unique. Machine Check EAX/RAX Save State See Section\r | |
359 | 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r | |
360 | state at time of machine check error. When in non-64-bit modes at the time\r | |
361 | of the error, bits 63-32 do not contain valid data.\r | |
362 | \r | |
363 | @param ECX MSR_PENTIUM_4_MCG_RAX (0x00000180)\r | |
364 | @param EAX Lower 32-bits of MSR value.\r | |
365 | @param EDX Upper 32-bits of MSR value.\r | |
366 | \r | |
367 | <b>Example usage</b>\r | |
368 | @code\r | |
369 | UINT64 Msr;\r | |
370 | \r | |
371 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RAX);\r | |
372 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RAX, Msr);\r | |
373 | @endcode\r | |
8bf98bd0 | 374 | @note MSR_PENTIUM_4_MCG_RAX is defined as MSR_MCG_RAX in SDM.\r |
f4d9afde | 375 | **/\r |
2f88bd3a | 376 | #define MSR_PENTIUM_4_MCG_RAX 0x00000180\r |
f4d9afde MK |
377 | \r |
378 | /**\r | |
379 | 0, 1, 2, 3, 4, 6. Unique. Machine Check EBX/RBX Save State See Section\r | |
380 | 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r | |
381 | state at time of machine check error. When in non-64-bit modes at the time\r | |
382 | of the error, bits 63-32 do not contain valid data.\r | |
383 | \r | |
384 | @param ECX MSR_PENTIUM_4_MCG_RBX (0x00000181)\r | |
385 | @param EAX Lower 32-bits of MSR value.\r | |
386 | @param EDX Upper 32-bits of MSR value.\r | |
387 | \r | |
388 | <b>Example usage</b>\r | |
389 | @code\r | |
390 | UINT64 Msr;\r | |
391 | \r | |
392 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBX);\r | |
393 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBX, Msr);\r | |
394 | @endcode\r | |
8bf98bd0 | 395 | @note MSR_PENTIUM_4_MCG_RBX is defined as MSR_MCG_RBX in SDM.\r |
f4d9afde | 396 | **/\r |
2f88bd3a | 397 | #define MSR_PENTIUM_4_MCG_RBX 0x00000181\r |
f4d9afde MK |
398 | \r |
399 | /**\r | |
400 | 0, 1, 2, 3, 4, 6. Unique. Machine Check ECX/RCX Save State See Section\r | |
401 | 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r | |
402 | state at time of machine check error. When in non-64-bit modes at the time\r | |
403 | of the error, bits 63-32 do not contain valid data.\r | |
404 | \r | |
405 | @param ECX MSR_PENTIUM_4_MCG_RCX (0x00000182)\r | |
406 | @param EAX Lower 32-bits of MSR value.\r | |
407 | @param EDX Upper 32-bits of MSR value.\r | |
408 | \r | |
409 | <b>Example usage</b>\r | |
410 | @code\r | |
411 | UINT64 Msr;\r | |
412 | \r | |
413 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RCX);\r | |
414 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RCX, Msr);\r | |
415 | @endcode\r | |
8bf98bd0 | 416 | @note MSR_PENTIUM_4_MCG_RCX is defined as MSR_MCG_RCX in SDM.\r |
f4d9afde | 417 | **/\r |
2f88bd3a | 418 | #define MSR_PENTIUM_4_MCG_RCX 0x00000182\r |
f4d9afde MK |
419 | \r |
420 | /**\r | |
421 | 0, 1, 2, 3, 4, 6. Unique. Machine Check EDX/RDX Save State See Section\r | |
422 | 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r | |
423 | state at time of machine check error. When in non-64-bit modes at the time\r | |
424 | of the error, bits 63-32 do not contain valid data.\r | |
425 | \r | |
426 | @param ECX MSR_PENTIUM_4_MCG_RDX (0x00000183)\r | |
427 | @param EAX Lower 32-bits of MSR value.\r | |
428 | @param EDX Upper 32-bits of MSR value.\r | |
429 | \r | |
430 | <b>Example usage</b>\r | |
431 | @code\r | |
432 | UINT64 Msr;\r | |
433 | \r | |
434 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDX);\r | |
435 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDX, Msr);\r | |
436 | @endcode\r | |
8bf98bd0 | 437 | @note MSR_PENTIUM_4_MCG_RDX is defined as MSR_MCG_RDX in SDM.\r |
f4d9afde | 438 | **/\r |
2f88bd3a | 439 | #define MSR_PENTIUM_4_MCG_RDX 0x00000183\r |
f4d9afde MK |
440 | \r |
441 | /**\r | |
442 | 0, 1, 2, 3, 4, 6. Unique. Machine Check ESI/RSI Save State See Section\r | |
443 | 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r | |
444 | state at time of machine check error. When in non-64-bit modes at the time\r | |
445 | of the error, bits 63-32 do not contain valid data.\r | |
446 | \r | |
447 | @param ECX MSR_PENTIUM_4_MCG_RSI (0x00000184)\r | |
448 | @param EAX Lower 32-bits of MSR value.\r | |
449 | @param EDX Upper 32-bits of MSR value.\r | |
450 | \r | |
451 | <b>Example usage</b>\r | |
452 | @code\r | |
453 | UINT64 Msr;\r | |
454 | \r | |
455 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSI);\r | |
456 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSI, Msr);\r | |
457 | @endcode\r | |
8bf98bd0 | 458 | @note MSR_PENTIUM_4_MCG_RSI is defined as MSR_MCG_RSI in SDM.\r |
f4d9afde | 459 | **/\r |
2f88bd3a | 460 | #define MSR_PENTIUM_4_MCG_RSI 0x00000184\r |
f4d9afde MK |
461 | \r |
462 | /**\r | |
463 | 0, 1, 2, 3, 4, 6. Unique. Machine Check EDI/RDI Save State See Section\r | |
464 | 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r | |
465 | state at time of machine check error. When in non-64-bit modes at the time\r | |
466 | of the error, bits 63-32 do not contain valid data.\r | |
467 | \r | |
468 | @param ECX MSR_PENTIUM_4_MCG_RDI (0x00000185)\r | |
469 | @param EAX Lower 32-bits of MSR value.\r | |
470 | @param EDX Upper 32-bits of MSR value.\r | |
471 | \r | |
472 | <b>Example usage</b>\r | |
473 | @code\r | |
474 | UINT64 Msr;\r | |
475 | \r | |
476 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RDI);\r | |
477 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RDI, Msr);\r | |
478 | @endcode\r | |
8bf98bd0 | 479 | @note MSR_PENTIUM_4_MCG_RDI is defined as MSR_MCG_RDI in SDM.\r |
f4d9afde | 480 | **/\r |
2f88bd3a | 481 | #define MSR_PENTIUM_4_MCG_RDI 0x00000185\r |
f4d9afde MK |
482 | \r |
483 | /**\r | |
484 | 0, 1, 2, 3, 4, 6. Unique. Machine Check EBP/RBP Save State See Section\r | |
485 | 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r | |
486 | state at time of machine check error. When in non-64-bit modes at the time\r | |
487 | of the error, bits 63-32 do not contain valid data.\r | |
488 | \r | |
489 | @param ECX MSR_PENTIUM_4_MCG_RBP (0x00000186)\r | |
490 | @param EAX Lower 32-bits of MSR value.\r | |
491 | @param EDX Upper 32-bits of MSR value.\r | |
492 | \r | |
493 | <b>Example usage</b>\r | |
494 | @code\r | |
495 | UINT64 Msr;\r | |
496 | \r | |
497 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RBP);\r | |
498 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RBP, Msr);\r | |
499 | @endcode\r | |
8bf98bd0 | 500 | @note MSR_PENTIUM_4_MCG_RBP is defined as MSR_MCG_RBP in SDM.\r |
f4d9afde | 501 | **/\r |
2f88bd3a | 502 | #define MSR_PENTIUM_4_MCG_RBP 0x00000186\r |
f4d9afde MK |
503 | \r |
504 | /**\r | |
505 | 0, 1, 2, 3, 4, 6. Unique. Machine Check ESP/RSP Save State See Section\r | |
506 | 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r | |
507 | state at time of machine check error. When in non-64-bit modes at the time\r | |
508 | of the error, bits 63-32 do not contain valid data.\r | |
509 | \r | |
510 | @param ECX MSR_PENTIUM_4_MCG_RSP (0x00000187)\r | |
511 | @param EAX Lower 32-bits of MSR value.\r | |
512 | @param EDX Upper 32-bits of MSR value.\r | |
513 | \r | |
514 | <b>Example usage</b>\r | |
515 | @code\r | |
516 | UINT64 Msr;\r | |
517 | \r | |
518 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RSP);\r | |
519 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RSP, Msr);\r | |
520 | @endcode\r | |
8bf98bd0 | 521 | @note MSR_PENTIUM_4_MCG_RSP is defined as MSR_MCG_RSP in SDM.\r |
f4d9afde | 522 | **/\r |
2f88bd3a | 523 | #define MSR_PENTIUM_4_MCG_RSP 0x00000187\r |
f4d9afde MK |
524 | \r |
525 | /**\r | |
526 | 0, 1, 2, 3, 4, 6. Unique. Machine Check EFLAGS/RFLAG Save State See Section\r | |
527 | 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r | |
528 | state at time of machine check error. When in non-64-bit modes at the time\r | |
529 | of the error, bits 63-32 do not contain valid data.\r | |
530 | \r | |
531 | @param ECX MSR_PENTIUM_4_MCG_RFLAGS (0x00000188)\r | |
532 | @param EAX Lower 32-bits of MSR value.\r | |
533 | @param EDX Upper 32-bits of MSR value.\r | |
534 | \r | |
535 | <b>Example usage</b>\r | |
536 | @code\r | |
537 | UINT64 Msr;\r | |
538 | \r | |
539 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RFLAGS);\r | |
540 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RFLAGS, Msr);\r | |
541 | @endcode\r | |
8bf98bd0 | 542 | @note MSR_PENTIUM_4_MCG_RFLAGS is defined as MSR_MCG_RFLAGS in SDM.\r |
f4d9afde | 543 | **/\r |
2f88bd3a | 544 | #define MSR_PENTIUM_4_MCG_RFLAGS 0x00000188\r |
f4d9afde MK |
545 | \r |
546 | /**\r | |
547 | 0, 1, 2, 3, 4, 6. Unique. Machine Check EIP/RIP Save State See Section\r | |
548 | 15.3.2.6, "IA32_MCG Extended Machine Check State MSRs.". Contains register\r | |
549 | state at time of machine check error. When in non-64-bit modes at the time\r | |
550 | of the error, bits 63-32 do not contain valid data.\r | |
551 | \r | |
552 | @param ECX MSR_PENTIUM_4_MCG_RIP (0x00000189)\r | |
553 | @param EAX Lower 32-bits of MSR value.\r | |
554 | @param EDX Upper 32-bits of MSR value.\r | |
555 | \r | |
556 | <b>Example usage</b>\r | |
557 | @code\r | |
558 | UINT64 Msr;\r | |
559 | \r | |
560 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_RIP);\r | |
561 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_RIP, Msr);\r | |
562 | @endcode\r | |
8bf98bd0 | 563 | @note MSR_PENTIUM_4_MCG_RIP is defined as MSR_MCG_RIP in SDM.\r |
f4d9afde | 564 | **/\r |
2f88bd3a | 565 | #define MSR_PENTIUM_4_MCG_RIP 0x00000189\r |
f4d9afde MK |
566 | \r |
567 | /**\r | |
568 | 0, 1, 2, 3, 4, 6. Unique. Machine Check Miscellaneous See Section 15.3.2.6,\r | |
569 | "IA32_MCG Extended Machine Check State MSRs.".\r | |
570 | \r | |
571 | @param ECX MSR_PENTIUM_4_MCG_MISC (0x0000018A)\r | |
572 | @param EAX Lower 32-bits of MSR value.\r | |
573 | Described by the type MSR_PENTIUM_4_MCG_MISC_REGISTER.\r | |
574 | @param EDX Upper 32-bits of MSR value.\r | |
575 | Described by the type MSR_PENTIUM_4_MCG_MISC_REGISTER.\r | |
576 | \r | |
577 | <b>Example usage</b>\r | |
578 | @code\r | |
579 | MSR_PENTIUM_4_MCG_MISC_REGISTER Msr;\r | |
580 | \r | |
581 | Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_MCG_MISC);\r | |
582 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_MISC, Msr.Uint64);\r | |
583 | @endcode\r | |
8bf98bd0 | 584 | @note MSR_PENTIUM_4_MCG_MISC is defined as MSR_MCG_MISC in SDM.\r |
f4d9afde | 585 | **/\r |
2f88bd3a | 586 | #define MSR_PENTIUM_4_MCG_MISC 0x0000018A\r |
f4d9afde MK |
587 | \r |
588 | /**\r | |
589 | MSR information returned for MSR index #MSR_PENTIUM_4_MCG_MISC\r | |
590 | **/\r | |
591 | typedef union {\r | |
592 | ///\r | |
593 | /// Individual bit fields\r | |
594 | ///\r | |
595 | struct {\r | |
596 | ///\r | |
597 | /// [Bit 0] DS When set, the bit indicates that a page assist or page\r | |
598 | /// fault occurred during DS normal operation. The processors response is\r | |
599 | /// to shut down. The bit is used as an aid for debugging DS handling\r | |
600 | /// code. It is the responsibility of the user (BIOS or operating system)\r | |
601 | /// to clear this bit for normal operation.\r | |
602 | ///\r | |
2f88bd3a MK |
603 | UINT32 DS : 1;\r |
604 | UINT32 Reserved1 : 31;\r | |
605 | UINT32 Reserved2 : 32;\r | |
f4d9afde MK |
606 | } Bits;\r |
607 | ///\r | |
608 | /// All bit fields as a 32-bit value\r | |
609 | ///\r | |
2f88bd3a | 610 | UINT32 Uint32;\r |
f4d9afde MK |
611 | ///\r |
612 | /// All bit fields as a 64-bit value\r | |
613 | ///\r | |
2f88bd3a | 614 | UINT64 Uint64;\r |
f4d9afde MK |
615 | } MSR_PENTIUM_4_MCG_MISC_REGISTER;\r |
616 | \r | |
f4d9afde MK |
617 | /**\r |
618 | 0, 1, 2, 3, 4, 6. Unique. Machine Check R8 See Section 15.3.2.6, "IA32_MCG\r | |
619 | Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r | |
620 | state-save MSRs) exist only in Intel 64 processors. These registers contain\r | |
621 | valid information only when the processor is operating in 64-bit mode at the\r | |
622 | time of the error.\r | |
623 | \r | |
624 | @param ECX MSR_PENTIUM_4_MCG_R8 (0x00000190)\r | |
625 | @param EAX Lower 32-bits of MSR value.\r | |
626 | @param EDX Upper 32-bits of MSR value.\r | |
627 | \r | |
628 | <b>Example usage</b>\r | |
629 | @code\r | |
630 | UINT64 Msr;\r | |
631 | \r | |
632 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R8);\r | |
633 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R8, Msr);\r | |
634 | @endcode\r | |
8bf98bd0 | 635 | @note MSR_PENTIUM_4_MCG_R8 is defined as MSR_MCG_R8 in SDM.\r |
f4d9afde | 636 | **/\r |
2f88bd3a | 637 | #define MSR_PENTIUM_4_MCG_R8 0x00000190\r |
f4d9afde MK |
638 | \r |
639 | /**\r | |
640 | 0, 1, 2, 3, 4, 6. Unique. Machine Check R9D/R9 See Section 15.3.2.6,\r | |
641 | "IA32_MCG Extended Machine Check State MSRs.". Registers R8-15 (and the\r | |
642 | associated state-save MSRs) exist only in Intel 64 processors. These\r | |
643 | registers contain valid information only when the processor is operating in\r | |
644 | 64-bit mode at the time of the error.\r | |
645 | \r | |
646 | @param ECX MSR_PENTIUM_4_MCG_R9 (0x00000191)\r | |
647 | @param EAX Lower 32-bits of MSR value.\r | |
648 | @param EDX Upper 32-bits of MSR value.\r | |
649 | \r | |
650 | <b>Example usage</b>\r | |
651 | @code\r | |
652 | UINT64 Msr;\r | |
653 | \r | |
654 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R9);\r | |
655 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R9, Msr);\r | |
656 | @endcode\r | |
8bf98bd0 | 657 | @note MSR_PENTIUM_4_MCG_R9 is defined as MSR_MCG_R9 in SDM.\r |
f4d9afde | 658 | **/\r |
2f88bd3a | 659 | #define MSR_PENTIUM_4_MCG_R9 0x00000191\r |
f4d9afde MK |
660 | \r |
661 | /**\r | |
662 | 0, 1, 2, 3, 4, 6. Unique. Machine Check R10 See Section 15.3.2.6, "IA32_MCG\r | |
663 | Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r | |
664 | state-save MSRs) exist only in Intel 64 processors. These registers contain\r | |
665 | valid information only when the processor is operating in 64-bit mode at the\r | |
666 | time of the error.\r | |
667 | \r | |
668 | @param ECX MSR_PENTIUM_4_MCG_R10 (0x00000192)\r | |
669 | @param EAX Lower 32-bits of MSR value.\r | |
670 | @param EDX Upper 32-bits of MSR value.\r | |
671 | \r | |
672 | <b>Example usage</b>\r | |
673 | @code\r | |
674 | UINT64 Msr;\r | |
675 | \r | |
676 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R10);\r | |
677 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R10, Msr);\r | |
678 | @endcode\r | |
8bf98bd0 | 679 | @note MSR_PENTIUM_4_MCG_R10 is defined as MSR_MCG_R10 in SDM.\r |
f4d9afde | 680 | **/\r |
2f88bd3a | 681 | #define MSR_PENTIUM_4_MCG_R10 0x00000192\r |
f4d9afde MK |
682 | \r |
683 | /**\r | |
684 | 0, 1, 2, 3, 4, 6. Unique. Machine Check R11 See Section 15.3.2.6, "IA32_MCG\r | |
685 | Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r | |
686 | state-save MSRs) exist only in Intel 64 processors. These registers contain\r | |
687 | valid information only when the processor is operating in 64-bit mode at the\r | |
688 | time of the error.\r | |
689 | \r | |
690 | @param ECX MSR_PENTIUM_4_MCG_R11 (0x00000193)\r | |
691 | @param EAX Lower 32-bits of MSR value.\r | |
692 | @param EDX Upper 32-bits of MSR value.\r | |
693 | \r | |
694 | <b>Example usage</b>\r | |
695 | @code\r | |
696 | UINT64 Msr;\r | |
697 | \r | |
698 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R11);\r | |
699 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R11, Msr);\r | |
700 | @endcode\r | |
8bf98bd0 | 701 | @note MSR_PENTIUM_4_MCG_R11 is defined as MSR_MCG_R11 in SDM.\r |
f4d9afde | 702 | **/\r |
2f88bd3a | 703 | #define MSR_PENTIUM_4_MCG_R11 0x00000193\r |
f4d9afde MK |
704 | \r |
705 | /**\r | |
706 | 0, 1, 2, 3, 4, 6. Unique. Machine Check R12 See Section 15.3.2.6, "IA32_MCG\r | |
707 | Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r | |
708 | state-save MSRs) exist only in Intel 64 processors. These registers contain\r | |
709 | valid information only when the processor is operating in 64-bit mode at the\r | |
710 | time of the error.\r | |
711 | \r | |
712 | @param ECX MSR_PENTIUM_4_MCG_R12 (0x00000194)\r | |
713 | @param EAX Lower 32-bits of MSR value.\r | |
714 | @param EDX Upper 32-bits of MSR value.\r | |
715 | \r | |
716 | <b>Example usage</b>\r | |
717 | @code\r | |
718 | UINT64 Msr;\r | |
719 | \r | |
720 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R12);\r | |
721 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R12, Msr);\r | |
722 | @endcode\r | |
8bf98bd0 | 723 | @note MSR_PENTIUM_4_MCG_R12 is defined as MSR_MCG_R12 in SDM.\r |
f4d9afde | 724 | **/\r |
2f88bd3a | 725 | #define MSR_PENTIUM_4_MCG_R12 0x00000194\r |
f4d9afde MK |
726 | \r |
727 | /**\r | |
728 | 0, 1, 2, 3, 4, 6. Unique. Machine Check R13 See Section 15.3.2.6, "IA32_MCG\r | |
729 | Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r | |
730 | state-save MSRs) exist only in Intel 64 processors. These registers contain\r | |
731 | valid information only when the processor is operating in 64-bit mode at the\r | |
732 | time of the error.\r | |
733 | \r | |
734 | @param ECX MSR_PENTIUM_4_MCG_R13 (0x00000195)\r | |
735 | @param EAX Lower 32-bits of MSR value.\r | |
736 | @param EDX Upper 32-bits of MSR value.\r | |
737 | \r | |
738 | <b>Example usage</b>\r | |
739 | @code\r | |
740 | UINT64 Msr;\r | |
741 | \r | |
742 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R13);\r | |
743 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R13, Msr);\r | |
744 | @endcode\r | |
8bf98bd0 | 745 | @note MSR_PENTIUM_4_MCG_R13 is defined as MSR_MCG_R13 in SDM.\r |
f4d9afde | 746 | **/\r |
2f88bd3a | 747 | #define MSR_PENTIUM_4_MCG_R13 0x00000195\r |
f4d9afde MK |
748 | \r |
749 | /**\r | |
750 | 0, 1, 2, 3, 4, 6. Unique. Machine Check R14 See Section 15.3.2.6, "IA32_MCG\r | |
751 | Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r | |
752 | state-save MSRs) exist only in Intel 64 processors. These registers contain\r | |
753 | valid information only when the processor is operating in 64-bit mode at the\r | |
754 | time of the error.\r | |
755 | \r | |
756 | @param ECX MSR_PENTIUM_4_MCG_R14 (0x00000196)\r | |
757 | @param EAX Lower 32-bits of MSR value.\r | |
758 | @param EDX Upper 32-bits of MSR value.\r | |
759 | \r | |
760 | <b>Example usage</b>\r | |
761 | @code\r | |
762 | UINT64 Msr;\r | |
763 | \r | |
764 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R14);\r | |
765 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R14, Msr);\r | |
766 | @endcode\r | |
8bf98bd0 | 767 | @note MSR_PENTIUM_4_MCG_R14 is defined as MSR_MCG_R14 in SDM.\r |
f4d9afde | 768 | **/\r |
2f88bd3a | 769 | #define MSR_PENTIUM_4_MCG_R14 0x00000196\r |
f4d9afde MK |
770 | \r |
771 | /**\r | |
772 | 0, 1, 2, 3, 4, 6. Unique. Machine Check R15 See Section 15.3.2.6, "IA32_MCG\r | |
773 | Extended Machine Check State MSRs.". Registers R8-15 (and the associated\r | |
774 | state-save MSRs) exist only in Intel 64 processors. These registers contain\r | |
775 | valid information only when the processor is operating in 64-bit mode at the\r | |
776 | time of the error.\r | |
777 | \r | |
778 | @param ECX MSR_PENTIUM_4_MCG_R15 (0x00000197)\r | |
779 | @param EAX Lower 32-bits of MSR value.\r | |
780 | @param EDX Upper 32-bits of MSR value.\r | |
781 | \r | |
782 | <b>Example usage</b>\r | |
783 | @code\r | |
784 | UINT64 Msr;\r | |
785 | \r | |
786 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MCG_R15);\r | |
787 | AsmWriteMsr64 (MSR_PENTIUM_4_MCG_R15, Msr);\r | |
788 | @endcode\r | |
8bf98bd0 | 789 | @note MSR_PENTIUM_4_MCG_R15 is defined as MSR_MCG_R15 in SDM.\r |
f4d9afde | 790 | **/\r |
2f88bd3a | 791 | #define MSR_PENTIUM_4_MCG_R15 0x00000197\r |
f4d9afde MK |
792 | \r |
793 | /**\r | |
794 | Thermal Monitor 2 Control. 3,. Shared. For Family F, Model 3 processors:\r | |
795 | When read, specifies the value of the target TM2 transition last written.\r | |
796 | When set, it sets the next target value for TM2 transition. 4, 6. Shared.\r | |
797 | For Family F, Model 4 and Model 6 processors: When read, specifies the value\r | |
798 | of the target TM2 transition last written. Writes may cause #GP exceptions.\r | |
799 | \r | |
800 | @param ECX MSR_PENTIUM_4_THERM2_CTL (0x0000019D)\r | |
801 | @param EAX Lower 32-bits of MSR value.\r | |
802 | @param EDX Upper 32-bits of MSR value.\r | |
803 | \r | |
804 | <b>Example usage</b>\r | |
805 | @code\r | |
806 | UINT64 Msr;\r | |
807 | \r | |
808 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_THERM2_CTL);\r | |
809 | AsmWriteMsr64 (MSR_PENTIUM_4_THERM2_CTL, Msr);\r | |
810 | @endcode\r | |
8bf98bd0 | 811 | @note MSR_PENTIUM_4_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r |
f4d9afde | 812 | **/\r |
2f88bd3a | 813 | #define MSR_PENTIUM_4_THERM2_CTL 0x0000019D\r |
f4d9afde MK |
814 | \r |
815 | /**\r | |
816 | 0, 1, 2, 3, 4, 6. Shared. Enable Miscellaneous Processor Features (R/W).\r | |
817 | \r | |
818 | @param ECX MSR_PENTIUM_4_IA32_MISC_ENABLE (0x000001A0)\r | |
819 | @param EAX Lower 32-bits of MSR value.\r | |
820 | Described by the type MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER.\r | |
821 | @param EDX Upper 32-bits of MSR value.\r | |
822 | Described by the type MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER.\r | |
823 | \r | |
824 | <b>Example usage</b>\r | |
825 | @code\r | |
826 | MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER Msr;\r | |
827 | \r | |
828 | Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE);\r | |
829 | AsmWriteMsr64 (MSR_PENTIUM_4_IA32_MISC_ENABLE, Msr.Uint64);\r | |
830 | @endcode\r | |
8bf98bd0 | 831 | @note MSR_PENTIUM_4_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r |
f4d9afde | 832 | **/\r |
2f88bd3a | 833 | #define MSR_PENTIUM_4_IA32_MISC_ENABLE 0x000001A0\r |
f4d9afde MK |
834 | \r |
835 | /**\r | |
836 | MSR information returned for MSR index #MSR_PENTIUM_4_IA32_MISC_ENABLE\r | |
837 | **/\r | |
838 | typedef union {\r | |
839 | ///\r | |
840 | /// Individual bit fields\r | |
841 | ///\r | |
842 | struct {\r | |
843 | ///\r | |
ba1a2d11 | 844 | /// [Bit 0] Fast-Strings Enable. See Table 2-2.\r |
f4d9afde | 845 | ///\r |
2f88bd3a MK |
846 | UINT32 FastStrings : 1;\r |
847 | UINT32 Reserved1 : 1;\r | |
f4d9afde MK |
848 | ///\r |
849 | /// [Bit 2] x87 FPU Fopcode Compatibility Mode Enable.\r | |
850 | ///\r | |
2f88bd3a | 851 | UINT32 FPU : 1;\r |
f4d9afde MK |
852 | ///\r |
853 | /// [Bit 3] Thermal Monitor 1 Enable See Section 14.7.2, "Thermal\r | |
ba1a2d11 | 854 | /// Monitor," and see Table 2-2.\r |
f4d9afde | 855 | ///\r |
2f88bd3a | 856 | UINT32 TM1 : 1;\r |
f4d9afde MK |
857 | ///\r |
858 | /// [Bit 4] Split-Lock Disable When set, the bit causes an #AC exception\r | |
859 | /// to be issued instead of a split-lock cycle. Operating systems that set\r | |
860 | /// this bit must align system structures to avoid split-lock scenarios.\r | |
861 | /// When the bit is clear (default), normal split-locks are issued to the\r | |
862 | /// bus.\r | |
863 | /// This debug feature is specific to the Pentium 4 processor.\r | |
864 | ///\r | |
2f88bd3a MK |
865 | UINT32 SplitLockDisable : 1;\r |
866 | UINT32 Reserved2 : 1;\r | |
f4d9afde MK |
867 | ///\r |
868 | /// [Bit 6] Third-Level Cache Disable (R/W) When set, the third-level\r | |
869 | /// cache is disabled; when clear (default) the third-level cache is\r | |
870 | /// enabled. This flag is reserved for processors that do not have a\r | |
871 | /// third-level cache. Note that the bit controls only the third-level\r | |
872 | /// cache; and only if overall caching is enabled through the CD flag of\r | |
873 | /// control register CR0, the page-level cache controls, and/or the MTRRs.\r | |
874 | /// See Section 11.5.4, "Disabling and Enabling the L3 Cache.".\r | |
875 | ///\r | |
2f88bd3a | 876 | UINT32 ThirdLevelCacheDisable : 1;\r |
f4d9afde | 877 | ///\r |
ba1a2d11 | 878 | /// [Bit 7] Performance Monitoring Available (R) See Table 2-2.\r |
f4d9afde | 879 | ///\r |
2f88bd3a | 880 | UINT32 PerformanceMonitoring : 1;\r |
f4d9afde MK |
881 | ///\r |
882 | /// [Bit 8] Suppress Lock Enable When set, assertion of LOCK on the bus is\r | |
883 | /// suppressed during a Split Lock access. When clear (default), LOCK is\r | |
884 | /// not suppressed.\r | |
885 | ///\r | |
2f88bd3a | 886 | UINT32 SuppressLockEnable : 1;\r |
f4d9afde MK |
887 | ///\r |
888 | /// [Bit 9] Prefetch Queue Disable When set, disables the prefetch queue.\r | |
889 | /// When clear (default), enables the prefetch queue.\r | |
890 | ///\r | |
2f88bd3a | 891 | UINT32 PrefetchQueueDisable : 1;\r |
f4d9afde MK |
892 | ///\r |
893 | /// [Bit 10] FERR# Interrupt Reporting Enable (R/W) When set, interrupt\r | |
894 | /// reporting through the FERR# pin is enabled; when clear, this interrupt\r | |
895 | /// reporting function is disabled.\r | |
896 | /// When this flag is set and the processor is in the stop-clock state\r | |
897 | /// (STPCLK# is asserted), asserting the FERR# pin signals to the\r | |
898 | /// processor that an interrupt (such as, INIT#, BINIT#, INTR, NMI,\r | |
899 | /// SMI#, or RESET#) is pending and that the processor should return to\r | |
900 | /// normal operation to handle the interrupt. This flag does not affect\r | |
901 | /// the normal operation of the FERR# pin (to indicate an unmasked\r | |
902 | /// floatingpoint error) when the STPCLK# pin is not asserted.\r | |
903 | ///\r | |
2f88bd3a | 904 | UINT32 FERR : 1;\r |
f4d9afde MK |
905 | ///\r |
906 | /// [Bit 11] Branch Trace Storage Unavailable (BTS_UNAVILABLE) (R) See\r | |
ba1a2d11 | 907 | /// Table 2-2. When set, the processor does not support branch trace\r |
f4d9afde MK |
908 | /// storage (BTS); when clear, BTS is supported.\r |
909 | ///\r | |
2f88bd3a | 910 | UINT32 BTS : 1;\r |
f4d9afde | 911 | ///\r |
0f16be6d | 912 | /// [Bit 12] PEBS_UNAVILABLE: Processor Event Based Sampling Unavailable\r |
ba1a2d11 | 913 | /// (R) See Table 2-2. When set, the processor does not support processor\r |
f4d9afde MK |
914 | /// event-based sampling (PEBS); when clear, PEBS is supported.\r |
915 | ///\r | |
2f88bd3a | 916 | UINT32 PEBS : 1;\r |
f4d9afde MK |
917 | ///\r |
918 | /// [Bit 13] 3. TM2 Enable (R/W) When this bit is set (1) and the thermal\r | |
919 | /// sensor indicates that the die temperature is at the predetermined\r | |
920 | /// threshold, the Thermal Monitor 2 mechanism is engaged. TM2 will reduce\r | |
921 | /// the bus to core ratio and voltage according to the value last written\r | |
922 | /// to MSR_THERM2_CTL bits 15:0. When this bit is clear (0, default), the\r | |
923 | /// processor does not change the VID signals or the bus to core ratio\r | |
924 | /// when the processor enters a thermal managed state. If the TM2 feature\r | |
925 | /// flag (ECX[8]) is not set to 1 after executing CPUID with EAX = 1, then\r | |
926 | /// this feature is not supported and BIOS must not alter the contents of\r | |
927 | /// this bit location. The processor is operating out of spec if both this\r | |
928 | /// bit and the TM1 bit are set to disabled states.\r | |
929 | ///\r | |
2f88bd3a MK |
930 | UINT32 TM2 : 1;\r |
931 | UINT32 Reserved3 : 4;\r | |
f4d9afde | 932 | ///\r |
ba1a2d11 | 933 | /// [Bit 18] 3, 4, 6. ENABLE MONITOR FSM (R/W) See Table 2-2.\r |
f4d9afde | 934 | ///\r |
2f88bd3a | 935 | UINT32 MONITOR : 1;\r |
f4d9afde MK |
936 | ///\r |
937 | /// [Bit 19] Adjacent Cache Line Prefetch Disable (R/W) When set to 1,\r | |
938 | /// the processor fetches the cache line of the 128-byte sector containing\r | |
939 | /// currently required data. When set to 0, the processor fetches both\r | |
940 | /// cache lines in the sector.\r | |
941 | /// Single processor platforms should not set this bit. Server platforms\r | |
942 | /// should set or clear this bit based on platform performance observed\r | |
943 | /// in validation and testing. BIOS may contain a setup option that\r | |
944 | /// controls the setting of this bit.\r | |
945 | ///\r | |
2f88bd3a MK |
946 | UINT32 AdjacentCacheLinePrefetchDisable : 1;\r |
947 | UINT32 Reserved4 : 2;\r | |
f4d9afde | 948 | ///\r |
ba1a2d11 ED |
949 | /// [Bit 22] 3, 4, 6. Limit CPUID MAXVAL (R/W) See Table 2-2. Setting this\r |
950 | /// can cause unexpected behavior to software that depends on the\r | |
f4d9afde MK |
951 | /// availability of CPUID leaves greater than 3.\r |
952 | ///\r | |
2f88bd3a | 953 | UINT32 LimitCpuidMaxval : 1;\r |
f4d9afde | 954 | ///\r |
ba1a2d11 | 955 | /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.\r |
f4d9afde | 956 | ///\r |
2f88bd3a | 957 | UINT32 xTPR_Message_Disable : 1;\r |
f4d9afde MK |
958 | ///\r |
959 | /// [Bit 24] L1 Data Cache Context Mode (R/W) When set, the L1 data cache\r | |
960 | /// is placed in shared mode; when clear (default), the cache is placed in\r | |
961 | /// adaptive mode. This bit is only enabled for IA-32 processors that\r | |
962 | /// support Intel Hyper-Threading Technology. See Section 11.5.6, "L1 Data\r | |
963 | /// Cache Context Mode." When L1 is running in adaptive mode and CR3s are\r | |
964 | /// identical, data in L1 is shared across logical processors. Otherwise,\r | |
965 | /// L1 is not shared and cache use is competitive. If the Context ID\r | |
966 | /// feature flag (ECX[10]) is set to 0 after executing CPUID with EAX = 1,\r | |
967 | /// the ability to switch modes is not supported. BIOS must not alter the\r | |
968 | /// contents of IA32_MISC_ENABLE[24].\r | |
969 | ///\r | |
2f88bd3a MK |
970 | UINT32 L1DataCacheContextMode : 1;\r |
971 | UINT32 Reserved5 : 7;\r | |
972 | UINT32 Reserved6 : 2;\r | |
f4d9afde | 973 | ///\r |
ba1a2d11 | 974 | /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.\r |
f4d9afde | 975 | ///\r |
2f88bd3a MK |
976 | UINT32 XD : 1;\r |
977 | UINT32 Reserved7 : 29;\r | |
f4d9afde MK |
978 | } Bits;\r |
979 | ///\r | |
980 | /// All bit fields as a 64-bit value\r | |
981 | ///\r | |
2f88bd3a | 982 | UINT64 Uint64;\r |
f4d9afde MK |
983 | } MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER;\r |
984 | \r | |
f4d9afde MK |
985 | /**\r |
986 | 3, 4, 6. Shared. Platform Feature Requirements (R).\r | |
987 | \r | |
988 | @param ECX MSR_PENTIUM_4_PLATFORM_BRV (0x000001A1)\r | |
989 | @param EAX Lower 32-bits of MSR value.\r | |
990 | Described by the type MSR_PENTIUM_4_PLATFORM_BRV_REGISTER.\r | |
991 | @param EDX Upper 32-bits of MSR value.\r | |
992 | Described by the type MSR_PENTIUM_4_PLATFORM_BRV_REGISTER.\r | |
993 | \r | |
994 | <b>Example usage</b>\r | |
995 | @code\r | |
996 | MSR_PENTIUM_4_PLATFORM_BRV_REGISTER Msr;\r | |
997 | \r | |
998 | Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PLATFORM_BRV);\r | |
999 | @endcode\r | |
8bf98bd0 | 1000 | @note MSR_PENTIUM_4_PLATFORM_BRV is defined as MSR_PLATFORM_BRV in SDM.\r |
f4d9afde | 1001 | **/\r |
2f88bd3a | 1002 | #define MSR_PENTIUM_4_PLATFORM_BRV 0x000001A1\r |
f4d9afde MK |
1003 | \r |
1004 | /**\r | |
1005 | MSR information returned for MSR index #MSR_PENTIUM_4_PLATFORM_BRV\r | |
1006 | **/\r | |
1007 | typedef union {\r | |
1008 | ///\r | |
1009 | /// Individual bit fields\r | |
1010 | ///\r | |
1011 | struct {\r | |
2f88bd3a | 1012 | UINT32 Reserved1 : 18;\r |
f4d9afde MK |
1013 | ///\r |
1014 | /// [Bit 18] PLATFORM Requirements When set to 1, indicates the processor\r | |
1015 | /// has specific platform requirements. The details of the platform\r | |
1016 | /// requirements are listed in the respective data sheets of the processor.\r | |
1017 | ///\r | |
2f88bd3a MK |
1018 | UINT32 PLATFORM : 1;\r |
1019 | UINT32 Reserved2 : 13;\r | |
1020 | UINT32 Reserved3 : 32;\r | |
f4d9afde MK |
1021 | } Bits;\r |
1022 | ///\r | |
1023 | /// All bit fields as a 32-bit value\r | |
1024 | ///\r | |
2f88bd3a | 1025 | UINT32 Uint32;\r |
f4d9afde MK |
1026 | ///\r |
1027 | /// All bit fields as a 64-bit value\r | |
1028 | ///\r | |
2f88bd3a | 1029 | UINT64 Uint64;\r |
f4d9afde MK |
1030 | } MSR_PENTIUM_4_PLATFORM_BRV_REGISTER;\r |
1031 | \r | |
f4d9afde MK |
1032 | /**\r |
1033 | 0, 1, 2, 3, 4, 6. Unique. Last Exception Record From Linear IP (R) Contains\r | |
1034 | a pointer to the last branch instruction that the processor executed prior\r | |
1035 | to the last exception that was generated or the last interrupt that was\r | |
ba1a2d11 ED |
1036 | handled. See Section 17.13.3, "Last Exception Records.". Unique. From Linear\r |
1037 | IP Linear address of the last branch instruction (If IA-32e mode is active).\r | |
f4d9afde MK |
1038 | From Linear IP Linear address of the last branch instruction. Reserved.\r |
1039 | \r | |
1040 | @param ECX MSR_PENTIUM_4_LER_FROM_LIP (0x000001D7)\r | |
1041 | @param EAX Lower 32-bits of MSR value.\r | |
1042 | @param EDX Upper 32-bits of MSR value.\r | |
1043 | \r | |
1044 | <b>Example usage</b>\r | |
1045 | @code\r | |
1046 | UINT64 Msr;\r | |
1047 | \r | |
1048 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_FROM_LIP);\r | |
1049 | @endcode\r | |
8bf98bd0 | 1050 | @note MSR_PENTIUM_4_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r |
f4d9afde | 1051 | **/\r |
2f88bd3a | 1052 | #define MSR_PENTIUM_4_LER_FROM_LIP 0x000001D7\r |
f4d9afde MK |
1053 | \r |
1054 | /**\r | |
1055 | 0, 1, 2, 3, 4, 6. Unique. Last Exception Record To Linear IP (R) This area\r | |
1056 | contains a pointer to the target of the last branch instruction that the\r | |
1057 | processor executed prior to the last exception that was generated or the\r | |
ba1a2d11 | 1058 | last interrupt that was handled. See Section 17.13.3, "Last Exception\r |
f4d9afde MK |
1059 | Records.". Unique. From Linear IP Linear address of the target of the last\r |
1060 | branch instruction (If IA-32e mode is active). From Linear IP Linear address\r | |
1061 | of the target of the last branch instruction. Reserved.\r | |
1062 | \r | |
1063 | @param ECX MSR_PENTIUM_4_LER_TO_LIP (0x000001D8)\r | |
1064 | @param EAX Lower 32-bits of MSR value.\r | |
1065 | @param EDX Upper 32-bits of MSR value.\r | |
1066 | \r | |
1067 | <b>Example usage</b>\r | |
1068 | @code\r | |
1069 | UINT64 Msr;\r | |
1070 | \r | |
1071 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_LER_TO_LIP);\r | |
1072 | @endcode\r | |
8bf98bd0 | 1073 | @note MSR_PENTIUM_4_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r |
f4d9afde | 1074 | **/\r |
2f88bd3a | 1075 | #define MSR_PENTIUM_4_LER_TO_LIP 0x000001D8\r |
f4d9afde MK |
1076 | \r |
1077 | /**\r | |
1078 | 0, 1, 2, 3, 4, 6. Unique. Debug Control (R/W) Controls how several debug\r | |
1079 | features are used. Bit definitions are discussed in the referenced section.\r | |
ba1a2d11 | 1080 | See Section 17.13.1, "MSR_DEBUGCTLA MSR.".\r |
f4d9afde MK |
1081 | \r |
1082 | @param ECX MSR_PENTIUM_4_DEBUGCTLA (0x000001D9)\r | |
1083 | @param EAX Lower 32-bits of MSR value.\r | |
1084 | @param EDX Upper 32-bits of MSR value.\r | |
1085 | \r | |
1086 | <b>Example usage</b>\r | |
1087 | @code\r | |
1088 | UINT64 Msr;\r | |
1089 | \r | |
1090 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_DEBUGCTLA);\r | |
1091 | AsmWriteMsr64 (MSR_PENTIUM_4_DEBUGCTLA, Msr);\r | |
1092 | @endcode\r | |
8bf98bd0 | 1093 | @note MSR_PENTIUM_4_DEBUGCTLA is defined as MSR_DEBUGCTLA in SDM.\r |
f4d9afde | 1094 | **/\r |
2f88bd3a | 1095 | #define MSR_PENTIUM_4_DEBUGCTLA 0x000001D9\r |
f4d9afde MK |
1096 | \r |
1097 | /**\r | |
1098 | 0, 1, 2, 3, 4, 6. Unique. Last Branch Record Stack TOS (R/W) Contains an\r | |
1099 | index (0-3 or 0-15) that points to the top of the last branch record stack\r | |
1100 | (that is, that points the index of the MSR containing the most recent branch\r | |
ba1a2d11 | 1101 | record). See Section 17.13.2, "LBR Stack for Processors Based on Intel\r |
f4d9afde MK |
1102 | NetBurst(R) Microarchitecture"; and addresses 1DBH-1DEH and 680H-68FH.\r |
1103 | \r | |
1104 | @param ECX MSR_PENTIUM_4_LASTBRANCH_TOS (0x000001DA)\r | |
1105 | @param EAX Lower 32-bits of MSR value.\r | |
1106 | @param EDX Upper 32-bits of MSR value.\r | |
1107 | \r | |
1108 | <b>Example usage</b>\r | |
1109 | @code\r | |
1110 | UINT64 Msr;\r | |
1111 | \r | |
1112 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS);\r | |
1113 | AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_TOS, Msr);\r | |
1114 | @endcode\r | |
8bf98bd0 | 1115 | @note MSR_PENTIUM_4_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r |
f4d9afde | 1116 | **/\r |
2f88bd3a | 1117 | #define MSR_PENTIUM_4_LASTBRANCH_TOS 0x000001DA\r |
f4d9afde MK |
1118 | \r |
1119 | /**\r | |
1120 | 0, 1, 2. Unique. Last Branch Record n (R/W) One of four last branch record\r | |
1121 | registers on the last branch record stack. It contains pointers to the\r | |
1122 | source and destination instruction for one of the last four branches,\r | |
1123 | exceptions, or interrupts that the processor took. MSR_LASTBRANCH_0 through\r | |
1124 | MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH, models\r | |
1125 | 0H-02H. They have been replaced by the MSRs at 680H68FH and 6C0H-6CFH. See\r | |
ba1a2d11 | 1126 | Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording\r |
f4d9afde MK |
1127 | for Processors based on Skylake Microarchitecture.".\r |
1128 | \r | |
1129 | @param ECX MSR_PENTIUM_4_LASTBRANCH_n\r | |
1130 | @param EAX Lower 32-bits of MSR value.\r | |
1131 | @param EDX Upper 32-bits of MSR value.\r | |
1132 | \r | |
1133 | <b>Example usage</b>\r | |
1134 | @code\r | |
1135 | UINT64 Msr;\r | |
1136 | \r | |
1137 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0);\r | |
1138 | AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0, Msr);\r | |
1139 | @endcode\r | |
8bf98bd0 JF |
1140 | @note MSR_PENTIUM_4_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.\r |
1141 | MSR_PENTIUM_4_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.\r | |
1142 | MSR_PENTIUM_4_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.\r | |
1143 | MSR_PENTIUM_4_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.\r | |
f4d9afde MK |
1144 | @{\r |
1145 | **/\r | |
2f88bd3a MK |
1146 | #define MSR_PENTIUM_4_LASTBRANCH_0 0x000001DB\r |
1147 | #define MSR_PENTIUM_4_LASTBRANCH_1 0x000001DC\r | |
1148 | #define MSR_PENTIUM_4_LASTBRANCH_2 0x000001DD\r | |
1149 | #define MSR_PENTIUM_4_LASTBRANCH_3 0x000001DE\r | |
f4d9afde MK |
1150 | /// @}\r |
1151 | \r | |
f4d9afde | 1152 | /**\r |
ba1a2d11 | 1153 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".\r |
f4d9afde MK |
1154 | \r |
1155 | @param ECX MSR_PENTIUM_4_BPU_COUNTERn\r | |
1156 | @param EAX Lower 32-bits of MSR value.\r | |
1157 | @param EDX Upper 32-bits of MSR value.\r | |
1158 | \r | |
1159 | <b>Example usage</b>\r | |
1160 | @code\r | |
1161 | UINT64 Msr;\r | |
1162 | \r | |
1163 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_COUNTER0);\r | |
1164 | AsmWriteMsr64 (MSR_PENTIUM_4_BPU_COUNTER0, Msr);\r | |
1165 | @endcode\r | |
8bf98bd0 JF |
1166 | @note MSR_PENTIUM_4_BPU_COUNTER0 is defined as MSR_BPU_COUNTER0 in SDM.\r |
1167 | MSR_PENTIUM_4_BPU_COUNTER1 is defined as MSR_BPU_COUNTER1 in SDM.\r | |
1168 | MSR_PENTIUM_4_BPU_COUNTER2 is defined as MSR_BPU_COUNTER2 in SDM.\r | |
1169 | MSR_PENTIUM_4_BPU_COUNTER3 is defined as MSR_BPU_COUNTER3 in SDM.\r | |
f4d9afde MK |
1170 | @{\r |
1171 | **/\r | |
2f88bd3a MK |
1172 | #define MSR_PENTIUM_4_BPU_COUNTER0 0x00000300\r |
1173 | #define MSR_PENTIUM_4_BPU_COUNTER1 0x00000301\r | |
1174 | #define MSR_PENTIUM_4_BPU_COUNTER2 0x00000302\r | |
1175 | #define MSR_PENTIUM_4_BPU_COUNTER3 0x00000303\r | |
f4d9afde MK |
1176 | /// @}\r |
1177 | \r | |
f4d9afde | 1178 | /**\r |
ba1a2d11 | 1179 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".\r |
f4d9afde MK |
1180 | \r |
1181 | @param ECX MSR_PENTIUM_4_MS_COUNTERn\r | |
1182 | @param EAX Lower 32-bits of MSR value.\r | |
1183 | @param EDX Upper 32-bits of MSR value.\r | |
1184 | \r | |
1185 | <b>Example usage</b>\r | |
1186 | @code\r | |
1187 | UINT64 Msr;\r | |
1188 | \r | |
1189 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_COUNTER0);\r | |
1190 | AsmWriteMsr64 (MSR_PENTIUM_4_MS_COUNTER0, Msr);\r | |
1191 | @endcode\r | |
8bf98bd0 JF |
1192 | @note MSR_PENTIUM_4_MS_COUNTER0 is defined as MSR_MS_COUNTER0 in SDM.\r |
1193 | MSR_PENTIUM_4_MS_COUNTER1 is defined as MSR_MS_COUNTER1 in SDM.\r | |
1194 | MSR_PENTIUM_4_MS_COUNTER2 is defined as MSR_MS_COUNTER2 in SDM.\r | |
1195 | MSR_PENTIUM_4_MS_COUNTER3 is defined as MSR_MS_COUNTER3 in SDM.\r | |
f4d9afde MK |
1196 | @{\r |
1197 | **/\r | |
2f88bd3a MK |
1198 | #define MSR_PENTIUM_4_MS_COUNTER0 0x00000304\r |
1199 | #define MSR_PENTIUM_4_MS_COUNTER1 0x00000305\r | |
1200 | #define MSR_PENTIUM_4_MS_COUNTER2 0x00000306\r | |
1201 | #define MSR_PENTIUM_4_MS_COUNTER3 0x00000307\r | |
f4d9afde MK |
1202 | /// @}\r |
1203 | \r | |
f4d9afde | 1204 | /**\r |
ba1a2d11 | 1205 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".\r |
f4d9afde MK |
1206 | \r |
1207 | @param ECX MSR_PENTIUM_4_FLAME_COUNTERn (0x00000308)\r | |
1208 | @param EAX Lower 32-bits of MSR value.\r | |
1209 | @param EDX Upper 32-bits of MSR value.\r | |
1210 | \r | |
1211 | <b>Example usage</b>\r | |
1212 | @code\r | |
1213 | UINT64 Msr;\r | |
1214 | \r | |
1215 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0);\r | |
1216 | AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_COUNTER0, Msr);\r | |
1217 | @endcode\r | |
8bf98bd0 JF |
1218 | @note MSR_PENTIUM_4_FLAME_COUNTER0 is defined as MSR_FLAME_COUNTER0 in SDM.\r |
1219 | MSR_PENTIUM_4_FLAME_COUNTER1 is defined as MSR_FLAME_COUNTER1 in SDM.\r | |
1220 | MSR_PENTIUM_4_FLAME_COUNTER2 is defined as MSR_FLAME_COUNTER2 in SDM.\r | |
1221 | MSR_PENTIUM_4_FLAME_COUNTER3 is defined as MSR_FLAME_COUNTER3 in SDM.\r | |
f4d9afde MK |
1222 | @{\r |
1223 | **/\r | |
2f88bd3a MK |
1224 | #define MSR_PENTIUM_4_FLAME_COUNTER0 0x00000308\r |
1225 | #define MSR_PENTIUM_4_FLAME_COUNTER1 0x00000309\r | |
1226 | #define MSR_PENTIUM_4_FLAME_COUNTER2 0x0000030A\r | |
1227 | #define MSR_PENTIUM_4_FLAME_COUNTER3 0x0000030B\r | |
f4d9afde MK |
1228 | /// @}\r |
1229 | \r | |
f4d9afde | 1230 | /**\r |
ba1a2d11 | 1231 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.2, "Performance Counters.".\r |
f4d9afde MK |
1232 | \r |
1233 | @param ECX MSR_PENTIUM_4_IQ_COUNTERn\r | |
1234 | @param EAX Lower 32-bits of MSR value.\r | |
1235 | @param EDX Upper 32-bits of MSR value.\r | |
1236 | \r | |
1237 | <b>Example usage</b>\r | |
1238 | @code\r | |
1239 | UINT64 Msr;\r | |
1240 | \r | |
1241 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_COUNTER0);\r | |
1242 | AsmWriteMsr64 (MSR_PENTIUM_4_IQ_COUNTER0, Msr);\r | |
1243 | @endcode\r | |
8bf98bd0 JF |
1244 | @note MSR_PENTIUM_4_IQ_COUNTER0 is defined as MSR_IQ_COUNTER0 in SDM.\r |
1245 | MSR_PENTIUM_4_IQ_COUNTER1 is defined as MSR_IQ_COUNTER1 in SDM.\r | |
1246 | MSR_PENTIUM_4_IQ_COUNTER2 is defined as MSR_IQ_COUNTER2 in SDM.\r | |
1247 | MSR_PENTIUM_4_IQ_COUNTER3 is defined as MSR_IQ_COUNTER3 in SDM.\r | |
1248 | MSR_PENTIUM_4_IQ_COUNTER4 is defined as MSR_IQ_COUNTER4 in SDM.\r | |
1249 | MSR_PENTIUM_4_IQ_COUNTER5 is defined as MSR_IQ_COUNTER5 in SDM.\r | |
f4d9afde MK |
1250 | @{\r |
1251 | **/\r | |
2f88bd3a MK |
1252 | #define MSR_PENTIUM_4_IQ_COUNTER0 0x0000030C\r |
1253 | #define MSR_PENTIUM_4_IQ_COUNTER1 0x0000030D\r | |
1254 | #define MSR_PENTIUM_4_IQ_COUNTER2 0x0000030E\r | |
1255 | #define MSR_PENTIUM_4_IQ_COUNTER3 0x0000030F\r | |
1256 | #define MSR_PENTIUM_4_IQ_COUNTER4 0x00000310\r | |
1257 | #define MSR_PENTIUM_4_IQ_COUNTER5 0x00000311\r | |
f4d9afde MK |
1258 | /// @}\r |
1259 | \r | |
f4d9afde | 1260 | /**\r |
ba1a2d11 | 1261 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".\r |
f4d9afde MK |
1262 | \r |
1263 | @param ECX MSR_PENTIUM_4_BPU_CCCRn\r | |
1264 | @param EAX Lower 32-bits of MSR value.\r | |
1265 | @param EDX Upper 32-bits of MSR value.\r | |
1266 | \r | |
1267 | <b>Example usage</b>\r | |
1268 | @code\r | |
1269 | UINT64 Msr;\r | |
1270 | \r | |
1271 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_CCCR0);\r | |
1272 | AsmWriteMsr64 (MSR_PENTIUM_4_BPU_CCCR0, Msr);\r | |
1273 | @endcode\r | |
8bf98bd0 JF |
1274 | @note MSR_PENTIUM_4_BPU_CCCR0 is defined as MSR_BPU_CCCR0 in SDM.\r |
1275 | MSR_PENTIUM_4_BPU_CCCR1 is defined as MSR_BPU_CCCR1 in SDM.\r | |
1276 | MSR_PENTIUM_4_BPU_CCCR2 is defined as MSR_BPU_CCCR2 in SDM.\r | |
1277 | MSR_PENTIUM_4_BPU_CCCR3 is defined as MSR_BPU_CCCR3 in SDM.\r | |
f4d9afde MK |
1278 | @{\r |
1279 | **/\r | |
2f88bd3a MK |
1280 | #define MSR_PENTIUM_4_BPU_CCCR0 0x00000360\r |
1281 | #define MSR_PENTIUM_4_BPU_CCCR1 0x00000361\r | |
1282 | #define MSR_PENTIUM_4_BPU_CCCR2 0x00000362\r | |
1283 | #define MSR_PENTIUM_4_BPU_CCCR3 0x00000363\r | |
f4d9afde MK |
1284 | /// @}\r |
1285 | \r | |
f4d9afde | 1286 | /**\r |
ba1a2d11 | 1287 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".\r |
f4d9afde MK |
1288 | \r |
1289 | @param ECX MSR_PENTIUM_4_MS_CCCRn\r | |
1290 | @param EAX Lower 32-bits of MSR value.\r | |
1291 | @param EDX Upper 32-bits of MSR value.\r | |
1292 | \r | |
1293 | <b>Example usage</b>\r | |
1294 | @code\r | |
1295 | UINT64 Msr;\r | |
1296 | \r | |
1297 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_CCCR0);\r | |
1298 | AsmWriteMsr64 (MSR_PENTIUM_4_MS_CCCR0, Msr);\r | |
1299 | @endcode\r | |
8bf98bd0 JF |
1300 | @note MSR_PENTIUM_4_MS_CCCR0 is defined as MSR_MS_CCCR0 in SDM.\r |
1301 | MSR_PENTIUM_4_MS_CCCR1 is defined as MSR_MS_CCCR1 in SDM.\r | |
1302 | MSR_PENTIUM_4_MS_CCCR2 is defined as MSR_MS_CCCR2 in SDM.\r | |
1303 | MSR_PENTIUM_4_MS_CCCR3 is defined as MSR_MS_CCCR3 in SDM.\r | |
f4d9afde MK |
1304 | @{\r |
1305 | **/\r | |
2f88bd3a MK |
1306 | #define MSR_PENTIUM_4_MS_CCCR0 0x00000364\r |
1307 | #define MSR_PENTIUM_4_MS_CCCR1 0x00000365\r | |
1308 | #define MSR_PENTIUM_4_MS_CCCR2 0x00000366\r | |
1309 | #define MSR_PENTIUM_4_MS_CCCR3 0x00000367\r | |
f4d9afde MK |
1310 | /// @}\r |
1311 | \r | |
f4d9afde | 1312 | /**\r |
ba1a2d11 | 1313 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".\r |
f4d9afde MK |
1314 | \r |
1315 | @param ECX MSR_PENTIUM_4_FLAME_CCCRn\r | |
1316 | @param EAX Lower 32-bits of MSR value.\r | |
1317 | @param EDX Upper 32-bits of MSR value.\r | |
1318 | \r | |
1319 | <b>Example usage</b>\r | |
1320 | @code\r | |
1321 | UINT64 Msr;\r | |
1322 | \r | |
1323 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_CCCR0);\r | |
1324 | AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_CCCR0, Msr);\r | |
1325 | @endcode\r | |
8bf98bd0 JF |
1326 | @note MSR_PENTIUM_4_FLAME_CCCR0 is defined as MSR_FLAME_CCCR0 in SDM.\r |
1327 | MSR_PENTIUM_4_FLAME_CCCR1 is defined as MSR_FLAME_CCCR1 in SDM.\r | |
1328 | MSR_PENTIUM_4_FLAME_CCCR2 is defined as MSR_FLAME_CCCR2 in SDM.\r | |
1329 | MSR_PENTIUM_4_FLAME_CCCR3 is defined as MSR_FLAME_CCCR3 in SDM.\r | |
f4d9afde MK |
1330 | @{\r |
1331 | **/\r | |
2f88bd3a MK |
1332 | #define MSR_PENTIUM_4_FLAME_CCCR0 0x00000368\r |
1333 | #define MSR_PENTIUM_4_FLAME_CCCR1 0x00000369\r | |
1334 | #define MSR_PENTIUM_4_FLAME_CCCR2 0x0000036A\r | |
1335 | #define MSR_PENTIUM_4_FLAME_CCCR3 0x0000036B\r | |
f4d9afde MK |
1336 | /// @}\r |
1337 | \r | |
f4d9afde | 1338 | /**\r |
ba1a2d11 | 1339 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.3, "CCCR MSRs.".\r |
f4d9afde MK |
1340 | \r |
1341 | @param ECX MSR_PENTIUM_4_IQ_CCCRn\r | |
1342 | @param EAX Lower 32-bits of MSR value.\r | |
1343 | @param EDX Upper 32-bits of MSR value.\r | |
1344 | \r | |
1345 | <b>Example usage</b>\r | |
1346 | @code\r | |
1347 | UINT64 Msr;\r | |
1348 | \r | |
1349 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_CCCR0);\r | |
1350 | AsmWriteMsr64 (MSR_PENTIUM_4_IQ_CCCR0, Msr);\r | |
1351 | @endcode\r | |
8bf98bd0 JF |
1352 | @note MSR_PENTIUM_4_IQ_CCCR0 is defined as MSR_IQ_CCCR0 in SDM.\r |
1353 | MSR_PENTIUM_4_IQ_CCCR1 is defined as MSR_IQ_CCCR1 in SDM.\r | |
1354 | MSR_PENTIUM_4_IQ_CCCR2 is defined as MSR_IQ_CCCR2 in SDM.\r | |
1355 | MSR_PENTIUM_4_IQ_CCCR3 is defined as MSR_IQ_CCCR3 in SDM.\r | |
1356 | MSR_PENTIUM_4_IQ_CCCR4 is defined as MSR_IQ_CCCR4 in SDM.\r | |
1357 | MSR_PENTIUM_4_IQ_CCCR5 is defined as MSR_IQ_CCCR5 in SDM.\r | |
f4d9afde MK |
1358 | @{\r |
1359 | **/\r | |
2f88bd3a MK |
1360 | #define MSR_PENTIUM_4_IQ_CCCR0 0x0000036C\r |
1361 | #define MSR_PENTIUM_4_IQ_CCCR1 0x0000036D\r | |
1362 | #define MSR_PENTIUM_4_IQ_CCCR2 0x0000036E\r | |
1363 | #define MSR_PENTIUM_4_IQ_CCCR3 0x0000036F\r | |
1364 | #define MSR_PENTIUM_4_IQ_CCCR4 0x00000370\r | |
1365 | #define MSR_PENTIUM_4_IQ_CCCR5 0x00000371\r | |
f4d9afde MK |
1366 | /// @}\r |
1367 | \r | |
f4d9afde | 1368 | /**\r |
ba1a2d11 | 1369 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1370 | \r |
1371 | @param ECX MSR_PENTIUM_4_BSU_ESCR0 (0x000003A0)\r | |
1372 | @param EAX Lower 32-bits of MSR value.\r | |
1373 | @param EDX Upper 32-bits of MSR value.\r | |
1374 | \r | |
1375 | <b>Example usage</b>\r | |
1376 | @code\r | |
1377 | UINT64 Msr;\r | |
1378 | \r | |
1379 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR0);\r | |
1380 | AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR0, Msr);\r | |
1381 | @endcode\r | |
8bf98bd0 | 1382 | @note MSR_PENTIUM_4_BSU_ESCR0 is defined as MSR_BSU_ESCR0 in SDM.\r |
f4d9afde | 1383 | **/\r |
2f88bd3a | 1384 | #define MSR_PENTIUM_4_BSU_ESCR0 0x000003A0\r |
f4d9afde MK |
1385 | \r |
1386 | /**\r | |
ba1a2d11 | 1387 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1388 | \r |
1389 | @param ECX MSR_PENTIUM_4_BSU_ESCR1 (0x000003A1)\r | |
1390 | @param EAX Lower 32-bits of MSR value.\r | |
1391 | @param EDX Upper 32-bits of MSR value.\r | |
1392 | \r | |
1393 | <b>Example usage</b>\r | |
1394 | @code\r | |
1395 | UINT64 Msr;\r | |
1396 | \r | |
1397 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_BSU_ESCR1);\r | |
1398 | AsmWriteMsr64 (MSR_PENTIUM_4_BSU_ESCR1, Msr);\r | |
1399 | @endcode\r | |
8bf98bd0 | 1400 | @note MSR_PENTIUM_4_BSU_ESCR1 is defined as MSR_BSU_ESCR1 in SDM.\r |
f4d9afde | 1401 | **/\r |
2f88bd3a | 1402 | #define MSR_PENTIUM_4_BSU_ESCR1 0x000003A1\r |
f4d9afde MK |
1403 | \r |
1404 | /**\r | |
ba1a2d11 | 1405 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1406 | \r |
1407 | @param ECX MSR_PENTIUM_4_FSB_ESCR0 (0x000003A2)\r | |
1408 | @param EAX Lower 32-bits of MSR value.\r | |
1409 | @param EDX Upper 32-bits of MSR value.\r | |
1410 | \r | |
1411 | <b>Example usage</b>\r | |
1412 | @code\r | |
1413 | UINT64 Msr;\r | |
1414 | \r | |
1415 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR0);\r | |
1416 | AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR0, Msr);\r | |
1417 | @endcode\r | |
8bf98bd0 | 1418 | @note MSR_PENTIUM_4_FSB_ESCR0 is defined as MSR_FSB_ESCR0 in SDM.\r |
f4d9afde | 1419 | **/\r |
2f88bd3a | 1420 | #define MSR_PENTIUM_4_FSB_ESCR0 0x000003A2\r |
f4d9afde MK |
1421 | \r |
1422 | /**\r | |
ba1a2d11 | 1423 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1424 | \r |
1425 | @param ECX MSR_PENTIUM_4_FSB_ESCR1 (0x000003A3)\r | |
1426 | @param EAX Lower 32-bits of MSR value.\r | |
1427 | @param EDX Upper 32-bits of MSR value.\r | |
1428 | \r | |
1429 | <b>Example usage</b>\r | |
1430 | @code\r | |
1431 | UINT64 Msr;\r | |
1432 | \r | |
1433 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_FSB_ESCR1);\r | |
1434 | AsmWriteMsr64 (MSR_PENTIUM_4_FSB_ESCR1, Msr);\r | |
1435 | @endcode\r | |
8bf98bd0 | 1436 | @note MSR_PENTIUM_4_FSB_ESCR1 is defined as MSR_FSB_ESCR1 in SDM.\r |
f4d9afde | 1437 | **/\r |
2f88bd3a | 1438 | #define MSR_PENTIUM_4_FSB_ESCR1 0x000003A3\r |
f4d9afde MK |
1439 | \r |
1440 | /**\r | |
ba1a2d11 | 1441 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1442 | \r |
1443 | @param ECX MSR_PENTIUM_4_FIRM_ESCR0 (0x000003A4)\r | |
1444 | @param EAX Lower 32-bits of MSR value.\r | |
1445 | @param EDX Upper 32-bits of MSR value.\r | |
1446 | \r | |
1447 | <b>Example usage</b>\r | |
1448 | @code\r | |
1449 | UINT64 Msr;\r | |
1450 | \r | |
1451 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR0);\r | |
1452 | AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR0, Msr);\r | |
1453 | @endcode\r | |
8bf98bd0 | 1454 | @note MSR_PENTIUM_4_FIRM_ESCR0 is defined as MSR_FIRM_ESCR0 in SDM.\r |
f4d9afde | 1455 | **/\r |
2f88bd3a | 1456 | #define MSR_PENTIUM_4_FIRM_ESCR0 0x000003A4\r |
f4d9afde MK |
1457 | \r |
1458 | /**\r | |
ba1a2d11 | 1459 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1460 | \r |
1461 | @param ECX MSR_PENTIUM_4_FIRM_ESCR1 (0x000003A5)\r | |
1462 | @param EAX Lower 32-bits of MSR value.\r | |
1463 | @param EDX Upper 32-bits of MSR value.\r | |
1464 | \r | |
1465 | <b>Example usage</b>\r | |
1466 | @code\r | |
1467 | UINT64 Msr;\r | |
1468 | \r | |
1469 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_FIRM_ESCR1);\r | |
1470 | AsmWriteMsr64 (MSR_PENTIUM_4_FIRM_ESCR1, Msr);\r | |
1471 | @endcode\r | |
8bf98bd0 | 1472 | @note MSR_PENTIUM_4_FIRM_ESCR1 is defined as MSR_FIRM_ESCR1 in SDM.\r |
f4d9afde | 1473 | **/\r |
2f88bd3a | 1474 | #define MSR_PENTIUM_4_FIRM_ESCR1 0x000003A5\r |
f4d9afde MK |
1475 | \r |
1476 | /**\r | |
ba1a2d11 | 1477 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1478 | \r |
1479 | @param ECX MSR_PENTIUM_4_FLAME_ESCR0 (0x000003A6)\r | |
1480 | @param EAX Lower 32-bits of MSR value.\r | |
1481 | @param EDX Upper 32-bits of MSR value.\r | |
1482 | \r | |
1483 | <b>Example usage</b>\r | |
1484 | @code\r | |
1485 | UINT64 Msr;\r | |
1486 | \r | |
1487 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR0);\r | |
1488 | AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR0, Msr);\r | |
1489 | @endcode\r | |
8bf98bd0 | 1490 | @note MSR_PENTIUM_4_FLAME_ESCR0 is defined as MSR_FLAME_ESCR0 in SDM.\r |
f4d9afde | 1491 | **/\r |
2f88bd3a | 1492 | #define MSR_PENTIUM_4_FLAME_ESCR0 0x000003A6\r |
f4d9afde MK |
1493 | \r |
1494 | /**\r | |
ba1a2d11 | 1495 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1496 | \r |
1497 | @param ECX MSR_PENTIUM_4_FLAME_ESCR1 (0x000003A7)\r | |
1498 | @param EAX Lower 32-bits of MSR value.\r | |
1499 | @param EDX Upper 32-bits of MSR value.\r | |
1500 | \r | |
1501 | <b>Example usage</b>\r | |
1502 | @code\r | |
1503 | UINT64 Msr;\r | |
1504 | \r | |
1505 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_FLAME_ESCR1);\r | |
1506 | AsmWriteMsr64 (MSR_PENTIUM_4_FLAME_ESCR1, Msr);\r | |
1507 | @endcode\r | |
8bf98bd0 | 1508 | @note MSR_PENTIUM_4_FLAME_ESCR1 is defined as MSR_FLAME_ESCR1 in SDM.\r |
f4d9afde | 1509 | **/\r |
2f88bd3a | 1510 | #define MSR_PENTIUM_4_FLAME_ESCR1 0x000003A7\r |
f4d9afde MK |
1511 | \r |
1512 | /**\r | |
ba1a2d11 | 1513 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1514 | \r |
1515 | @param ECX MSR_PENTIUM_4_DAC_ESCR0 (0x000003A8)\r | |
1516 | @param EAX Lower 32-bits of MSR value.\r | |
1517 | @param EDX Upper 32-bits of MSR value.\r | |
1518 | \r | |
1519 | <b>Example usage</b>\r | |
1520 | @code\r | |
1521 | UINT64 Msr;\r | |
1522 | \r | |
1523 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR0);\r | |
1524 | AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR0, Msr);\r | |
1525 | @endcode\r | |
8bf98bd0 | 1526 | @note MSR_PENTIUM_4_DAC_ESCR0 is defined as MSR_DAC_ESCR0 in SDM.\r |
f4d9afde | 1527 | **/\r |
2f88bd3a | 1528 | #define MSR_PENTIUM_4_DAC_ESCR0 0x000003A8\r |
f4d9afde MK |
1529 | \r |
1530 | /**\r | |
ba1a2d11 | 1531 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1532 | \r |
1533 | @param ECX MSR_PENTIUM_4_DAC_ESCR1 (0x000003A9)\r | |
1534 | @param EAX Lower 32-bits of MSR value.\r | |
1535 | @param EDX Upper 32-bits of MSR value.\r | |
1536 | \r | |
1537 | <b>Example usage</b>\r | |
1538 | @code\r | |
1539 | UINT64 Msr;\r | |
1540 | \r | |
1541 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_DAC_ESCR1);\r | |
1542 | AsmWriteMsr64 (MSR_PENTIUM_4_DAC_ESCR1, Msr);\r | |
1543 | @endcode\r | |
8bf98bd0 | 1544 | @note MSR_PENTIUM_4_DAC_ESCR1 is defined as MSR_DAC_ESCR1 in SDM.\r |
f4d9afde | 1545 | **/\r |
2f88bd3a | 1546 | #define MSR_PENTIUM_4_DAC_ESCR1 0x000003A9\r |
f4d9afde MK |
1547 | \r |
1548 | /**\r | |
ba1a2d11 | 1549 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1550 | \r |
1551 | @param ECX MSR_PENTIUM_4_MOB_ESCR0 (0x000003AA)\r | |
1552 | @param EAX Lower 32-bits of MSR value.\r | |
1553 | @param EDX Upper 32-bits of MSR value.\r | |
1554 | \r | |
1555 | <b>Example usage</b>\r | |
1556 | @code\r | |
1557 | UINT64 Msr;\r | |
1558 | \r | |
1559 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR0);\r | |
1560 | AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR0, Msr);\r | |
1561 | @endcode\r | |
8bf98bd0 | 1562 | @note MSR_PENTIUM_4_MOB_ESCR0 is defined as MSR_MOB_ESCR0 in SDM.\r |
f4d9afde | 1563 | **/\r |
2f88bd3a | 1564 | #define MSR_PENTIUM_4_MOB_ESCR0 0x000003AA\r |
f4d9afde MK |
1565 | \r |
1566 | /**\r | |
ba1a2d11 | 1567 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1568 | \r |
1569 | @param ECX MSR_PENTIUM_4_MOB_ESCR1 (0x000003AB)\r | |
1570 | @param EAX Lower 32-bits of MSR value.\r | |
1571 | @param EDX Upper 32-bits of MSR value.\r | |
1572 | \r | |
1573 | <b>Example usage</b>\r | |
1574 | @code\r | |
1575 | UINT64 Msr;\r | |
1576 | \r | |
1577 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MOB_ESCR1);\r | |
1578 | AsmWriteMsr64 (MSR_PENTIUM_4_MOB_ESCR1, Msr);\r | |
1579 | @endcode\r | |
8bf98bd0 | 1580 | @note MSR_PENTIUM_4_MOB_ESCR1 is defined as MSR_MOB_ESCR1 in SDM.\r |
f4d9afde | 1581 | **/\r |
2f88bd3a | 1582 | #define MSR_PENTIUM_4_MOB_ESCR1 0x000003AB\r |
f4d9afde MK |
1583 | \r |
1584 | /**\r | |
ba1a2d11 | 1585 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1586 | \r |
1587 | @param ECX MSR_PENTIUM_4_PMH_ESCR0 (0x000003AC)\r | |
1588 | @param EAX Lower 32-bits of MSR value.\r | |
1589 | @param EDX Upper 32-bits of MSR value.\r | |
1590 | \r | |
1591 | <b>Example usage</b>\r | |
1592 | @code\r | |
1593 | UINT64 Msr;\r | |
1594 | \r | |
1595 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR0);\r | |
1596 | AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR0, Msr);\r | |
1597 | @endcode\r | |
8bf98bd0 | 1598 | @note MSR_PENTIUM_4_PMH_ESCR0 is defined as MSR_PMH_ESCR0 in SDM.\r |
f4d9afde | 1599 | **/\r |
2f88bd3a | 1600 | #define MSR_PENTIUM_4_PMH_ESCR0 0x000003AC\r |
f4d9afde MK |
1601 | \r |
1602 | /**\r | |
ba1a2d11 | 1603 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1604 | \r |
1605 | @param ECX MSR_PENTIUM_4_PMH_ESCR1 (0x000003AD)\r | |
1606 | @param EAX Lower 32-bits of MSR value.\r | |
1607 | @param EDX Upper 32-bits of MSR value.\r | |
1608 | \r | |
1609 | <b>Example usage</b>\r | |
1610 | @code\r | |
1611 | UINT64 Msr;\r | |
1612 | \r | |
1613 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_PMH_ESCR1);\r | |
1614 | AsmWriteMsr64 (MSR_PENTIUM_4_PMH_ESCR1, Msr);\r | |
1615 | @endcode\r | |
8bf98bd0 | 1616 | @note MSR_PENTIUM_4_PMH_ESCR1 is defined as MSR_PMH_ESCR1 in SDM.\r |
f4d9afde | 1617 | **/\r |
2f88bd3a | 1618 | #define MSR_PENTIUM_4_PMH_ESCR1 0x000003AD\r |
f4d9afde MK |
1619 | \r |
1620 | /**\r | |
ba1a2d11 | 1621 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1622 | \r |
1623 | @param ECX MSR_PENTIUM_4_SAAT_ESCR0 (0x000003AE)\r | |
1624 | @param EAX Lower 32-bits of MSR value.\r | |
1625 | @param EDX Upper 32-bits of MSR value.\r | |
1626 | \r | |
1627 | <b>Example usage</b>\r | |
1628 | @code\r | |
1629 | UINT64 Msr;\r | |
1630 | \r | |
1631 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR0);\r | |
1632 | AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR0, Msr);\r | |
1633 | @endcode\r | |
8bf98bd0 | 1634 | @note MSR_PENTIUM_4_SAAT_ESCR0 is defined as MSR_SAAT_ESCR0 in SDM.\r |
f4d9afde | 1635 | **/\r |
2f88bd3a | 1636 | #define MSR_PENTIUM_4_SAAT_ESCR0 0x000003AE\r |
f4d9afde MK |
1637 | \r |
1638 | /**\r | |
ba1a2d11 | 1639 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1640 | \r |
1641 | @param ECX MSR_PENTIUM_4_SAAT_ESCR1 (0x000003AF)\r | |
1642 | @param EAX Lower 32-bits of MSR value.\r | |
1643 | @param EDX Upper 32-bits of MSR value.\r | |
1644 | \r | |
1645 | <b>Example usage</b>\r | |
1646 | @code\r | |
1647 | UINT64 Msr;\r | |
1648 | \r | |
1649 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_SAAT_ESCR1);\r | |
1650 | AsmWriteMsr64 (MSR_PENTIUM_4_SAAT_ESCR1, Msr);\r | |
1651 | @endcode\r | |
8bf98bd0 | 1652 | @note MSR_PENTIUM_4_SAAT_ESCR1 is defined as MSR_SAAT_ESCR1 in SDM.\r |
f4d9afde | 1653 | **/\r |
2f88bd3a | 1654 | #define MSR_PENTIUM_4_SAAT_ESCR1 0x000003AF\r |
f4d9afde MK |
1655 | \r |
1656 | /**\r | |
ba1a2d11 | 1657 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1658 | \r |
1659 | @param ECX MSR_PENTIUM_4_U2L_ESCR0 (0x000003B0)\r | |
1660 | @param EAX Lower 32-bits of MSR value.\r | |
1661 | @param EDX Upper 32-bits of MSR value.\r | |
1662 | \r | |
1663 | <b>Example usage</b>\r | |
1664 | @code\r | |
1665 | UINT64 Msr;\r | |
1666 | \r | |
1667 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR0);\r | |
1668 | AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR0, Msr);\r | |
1669 | @endcode\r | |
8bf98bd0 | 1670 | @note MSR_PENTIUM_4_U2L_ESCR0 is defined as MSR_U2L_ESCR0 in SDM.\r |
f4d9afde | 1671 | **/\r |
2f88bd3a | 1672 | #define MSR_PENTIUM_4_U2L_ESCR0 0x000003B0\r |
f4d9afde MK |
1673 | \r |
1674 | /**\r | |
ba1a2d11 | 1675 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1676 | \r |
1677 | @param ECX MSR_PENTIUM_4_U2L_ESCR1 (0x000003B1)\r | |
1678 | @param EAX Lower 32-bits of MSR value.\r | |
1679 | @param EDX Upper 32-bits of MSR value.\r | |
1680 | \r | |
1681 | <b>Example usage</b>\r | |
1682 | @code\r | |
1683 | UINT64 Msr;\r | |
1684 | \r | |
1685 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_U2L_ESCR1);\r | |
1686 | AsmWriteMsr64 (MSR_PENTIUM_4_U2L_ESCR1, Msr);\r | |
1687 | @endcode\r | |
8bf98bd0 | 1688 | @note MSR_PENTIUM_4_U2L_ESCR1 is defined as MSR_U2L_ESCR1 in SDM.\r |
f4d9afde | 1689 | **/\r |
2f88bd3a | 1690 | #define MSR_PENTIUM_4_U2L_ESCR1 0x000003B1\r |
f4d9afde MK |
1691 | \r |
1692 | /**\r | |
ba1a2d11 | 1693 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1694 | \r |
1695 | @param ECX MSR_PENTIUM_4_BPU_ESCR0 (0x000003B2)\r | |
1696 | @param EAX Lower 32-bits of MSR value.\r | |
1697 | @param EDX Upper 32-bits of MSR value.\r | |
1698 | \r | |
1699 | <b>Example usage</b>\r | |
1700 | @code\r | |
1701 | UINT64 Msr;\r | |
1702 | \r | |
1703 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR0);\r | |
1704 | AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR0, Msr);\r | |
1705 | @endcode\r | |
8bf98bd0 | 1706 | @note MSR_PENTIUM_4_BPU_ESCR0 is defined as MSR_BPU_ESCR0 in SDM.\r |
f4d9afde | 1707 | **/\r |
2f88bd3a | 1708 | #define MSR_PENTIUM_4_BPU_ESCR0 0x000003B2\r |
f4d9afde MK |
1709 | \r |
1710 | /**\r | |
ba1a2d11 | 1711 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1712 | \r |
1713 | @param ECX MSR_PENTIUM_4_BPU_ESCR1 (0x000003B3)\r | |
1714 | @param EAX Lower 32-bits of MSR value.\r | |
1715 | @param EDX Upper 32-bits of MSR value.\r | |
1716 | \r | |
1717 | <b>Example usage</b>\r | |
1718 | @code\r | |
1719 | UINT64 Msr;\r | |
1720 | \r | |
1721 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_BPU_ESCR1);\r | |
1722 | AsmWriteMsr64 (MSR_PENTIUM_4_BPU_ESCR1, Msr);\r | |
1723 | @endcode\r | |
8bf98bd0 | 1724 | @note MSR_PENTIUM_4_BPU_ESCR1 is defined as MSR_BPU_ESCR1 in SDM.\r |
f4d9afde | 1725 | **/\r |
2f88bd3a | 1726 | #define MSR_PENTIUM_4_BPU_ESCR1 0x000003B3\r |
f4d9afde MK |
1727 | \r |
1728 | /**\r | |
ba1a2d11 | 1729 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1730 | \r |
1731 | @param ECX MSR_PENTIUM_4_IS_ESCR0 (0x000003B4)\r | |
1732 | @param EAX Lower 32-bits of MSR value.\r | |
1733 | @param EDX Upper 32-bits of MSR value.\r | |
1734 | \r | |
1735 | <b>Example usage</b>\r | |
1736 | @code\r | |
1737 | UINT64 Msr;\r | |
1738 | \r | |
1739 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR0);\r | |
1740 | AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR0, Msr);\r | |
1741 | @endcode\r | |
8bf98bd0 | 1742 | @note MSR_PENTIUM_4_IS_ESCR0 is defined as MSR_IS_ESCR0 in SDM.\r |
f4d9afde | 1743 | **/\r |
2f88bd3a | 1744 | #define MSR_PENTIUM_4_IS_ESCR0 0x000003B4\r |
f4d9afde MK |
1745 | \r |
1746 | /**\r | |
ba1a2d11 | 1747 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1748 | \r |
1749 | @param ECX MSR_PENTIUM_4_IS_ESCR1 (0x000003B5)\r | |
1750 | @param EAX Lower 32-bits of MSR value.\r | |
1751 | @param EDX Upper 32-bits of MSR value.\r | |
1752 | \r | |
1753 | <b>Example usage</b>\r | |
1754 | @code\r | |
1755 | UINT64 Msr;\r | |
1756 | \r | |
1757 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IS_ESCR1);\r | |
1758 | AsmWriteMsr64 (MSR_PENTIUM_4_IS_ESCR1, Msr);\r | |
1759 | @endcode\r | |
8bf98bd0 | 1760 | @note MSR_PENTIUM_4_IS_ESCR1 is defined as MSR_IS_ESCR1 in SDM.\r |
f4d9afde | 1761 | **/\r |
2f88bd3a | 1762 | #define MSR_PENTIUM_4_IS_ESCR1 0x000003B5\r |
f4d9afde MK |
1763 | \r |
1764 | /**\r | |
ba1a2d11 | 1765 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1766 | \r |
1767 | @param ECX MSR_PENTIUM_4_ITLB_ESCR0 (0x000003B6)\r | |
1768 | @param EAX Lower 32-bits of MSR value.\r | |
1769 | @param EDX Upper 32-bits of MSR value.\r | |
1770 | \r | |
1771 | <b>Example usage</b>\r | |
1772 | @code\r | |
1773 | UINT64 Msr;\r | |
1774 | \r | |
1775 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR0);\r | |
1776 | AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR0, Msr);\r | |
1777 | @endcode\r | |
8bf98bd0 | 1778 | @note MSR_PENTIUM_4_ITLB_ESCR0 is defined as MSR_ITLB_ESCR0 in SDM.\r |
f4d9afde | 1779 | **/\r |
2f88bd3a | 1780 | #define MSR_PENTIUM_4_ITLB_ESCR0 0x000003B6\r |
f4d9afde MK |
1781 | \r |
1782 | /**\r | |
ba1a2d11 | 1783 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1784 | \r |
1785 | @param ECX MSR_PENTIUM_4_ITLB_ESCR1 (0x000003B7)\r | |
1786 | @param EAX Lower 32-bits of MSR value.\r | |
1787 | @param EDX Upper 32-bits of MSR value.\r | |
1788 | \r | |
1789 | <b>Example usage</b>\r | |
1790 | @code\r | |
1791 | UINT64 Msr;\r | |
1792 | \r | |
1793 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_ITLB_ESCR1);\r | |
1794 | AsmWriteMsr64 (MSR_PENTIUM_4_ITLB_ESCR1, Msr);\r | |
1795 | @endcode\r | |
8bf98bd0 | 1796 | @note MSR_PENTIUM_4_ITLB_ESCR1 is defined as MSR_ITLB_ESCR1 in SDM.\r |
f4d9afde | 1797 | **/\r |
2f88bd3a | 1798 | #define MSR_PENTIUM_4_ITLB_ESCR1 0x000003B7\r |
f4d9afde MK |
1799 | \r |
1800 | /**\r | |
ba1a2d11 | 1801 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1802 | \r |
1803 | @param ECX MSR_PENTIUM_4_CRU_ESCR0 (0x000003B8)\r | |
1804 | @param EAX Lower 32-bits of MSR value.\r | |
1805 | @param EDX Upper 32-bits of MSR value.\r | |
1806 | \r | |
1807 | <b>Example usage</b>\r | |
1808 | @code\r | |
1809 | UINT64 Msr;\r | |
1810 | \r | |
1811 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR0);\r | |
1812 | AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR0, Msr);\r | |
1813 | @endcode\r | |
8bf98bd0 | 1814 | @note MSR_PENTIUM_4_CRU_ESCR0 is defined as MSR_CRU_ESCR0 in SDM.\r |
f4d9afde | 1815 | **/\r |
2f88bd3a | 1816 | #define MSR_PENTIUM_4_CRU_ESCR0 0x000003B8\r |
f4d9afde MK |
1817 | \r |
1818 | /**\r | |
ba1a2d11 | 1819 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1820 | \r |
1821 | @param ECX MSR_PENTIUM_4_CRU_ESCR1 (0x000003B9)\r | |
1822 | @param EAX Lower 32-bits of MSR value.\r | |
1823 | @param EDX Upper 32-bits of MSR value.\r | |
1824 | \r | |
1825 | <b>Example usage</b>\r | |
1826 | @code\r | |
1827 | UINT64 Msr;\r | |
1828 | \r | |
1829 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_CRU_ESCR1);\r | |
1830 | AsmWriteMsr64 (MSR_PENTIUM_4_CRU_ESCR1, Msr);\r | |
1831 | @endcode\r | |
8bf98bd0 | 1832 | @note MSR_PENTIUM_4_CRU_ESCR1 is defined as MSR_CRU_ESCR1 in SDM.\r |
f4d9afde | 1833 | **/\r |
2f88bd3a | 1834 | #define MSR_PENTIUM_4_CRU_ESCR1 0x000003B9\r |
f4d9afde MK |
1835 | \r |
1836 | /**\r | |
ba1a2d11 ED |
1837 | 0, 1, 2. Shared. See Section 18.6.3.1, "ESCR MSRs." This MSR is not\r |
1838 | available on later processors. It is only available on processor family 0FH,\r | |
1839 | models 01H-02H.\r | |
f4d9afde MK |
1840 | \r |
1841 | @param ECX MSR_PENTIUM_4_IQ_ESCR0 (0x000003BA)\r | |
1842 | @param EAX Lower 32-bits of MSR value.\r | |
1843 | @param EDX Upper 32-bits of MSR value.\r | |
1844 | \r | |
1845 | <b>Example usage</b>\r | |
1846 | @code\r | |
1847 | UINT64 Msr;\r | |
1848 | \r | |
1849 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR0);\r | |
1850 | AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR0, Msr);\r | |
1851 | @endcode\r | |
8bf98bd0 | 1852 | @note MSR_PENTIUM_4_IQ_ESCR0 is defined as MSR_IQ_ESCR0 in SDM.\r |
f4d9afde | 1853 | **/\r |
2f88bd3a | 1854 | #define MSR_PENTIUM_4_IQ_ESCR0 0x000003BA\r |
f4d9afde MK |
1855 | \r |
1856 | /**\r | |
ba1a2d11 ED |
1857 | 0, 1, 2. Shared. See Section 18.6.3.1, "ESCR MSRs." This MSR is not\r |
1858 | available on later processors. It is only available on processor family 0FH,\r | |
1859 | models 01H-02H.\r | |
f4d9afde MK |
1860 | \r |
1861 | @param ECX MSR_PENTIUM_4_IQ_ESCR1 (0x000003BB)\r | |
1862 | @param EAX Lower 32-bits of MSR value.\r | |
1863 | @param EDX Upper 32-bits of MSR value.\r | |
1864 | \r | |
1865 | <b>Example usage</b>\r | |
1866 | @code\r | |
1867 | UINT64 Msr;\r | |
1868 | \r | |
1869 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IQ_ESCR1);\r | |
1870 | AsmWriteMsr64 (MSR_PENTIUM_4_IQ_ESCR1, Msr);\r | |
1871 | @endcode\r | |
8bf98bd0 | 1872 | @note MSR_PENTIUM_4_IQ_ESCR1 is defined as MSR_IQ_ESCR1 in SDM.\r |
f4d9afde | 1873 | **/\r |
2f88bd3a | 1874 | #define MSR_PENTIUM_4_IQ_ESCR1 0x000003BB\r |
f4d9afde MK |
1875 | \r |
1876 | /**\r | |
ba1a2d11 | 1877 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1878 | \r |
1879 | @param ECX MSR_PENTIUM_4_RAT_ESCR0 (0x000003BC)\r | |
1880 | @param EAX Lower 32-bits of MSR value.\r | |
1881 | @param EDX Upper 32-bits of MSR value.\r | |
1882 | \r | |
1883 | <b>Example usage</b>\r | |
1884 | @code\r | |
1885 | UINT64 Msr;\r | |
1886 | \r | |
1887 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR0);\r | |
1888 | AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR0, Msr);\r | |
1889 | @endcode\r | |
8bf98bd0 | 1890 | @note MSR_PENTIUM_4_RAT_ESCR0 is defined as MSR_RAT_ESCR0 in SDM.\r |
f4d9afde | 1891 | **/\r |
2f88bd3a | 1892 | #define MSR_PENTIUM_4_RAT_ESCR0 0x000003BC\r |
f4d9afde MK |
1893 | \r |
1894 | /**\r | |
ba1a2d11 | 1895 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1896 | \r |
1897 | @param ECX MSR_PENTIUM_4_RAT_ESCR1 (0x000003BD)\r | |
1898 | @param EAX Lower 32-bits of MSR value.\r | |
1899 | @param EDX Upper 32-bits of MSR value.\r | |
1900 | \r | |
1901 | <b>Example usage</b>\r | |
1902 | @code\r | |
1903 | UINT64 Msr;\r | |
1904 | \r | |
1905 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_RAT_ESCR1);\r | |
1906 | AsmWriteMsr64 (MSR_PENTIUM_4_RAT_ESCR1, Msr);\r | |
1907 | @endcode\r | |
8bf98bd0 | 1908 | @note MSR_PENTIUM_4_RAT_ESCR1 is defined as MSR_RAT_ESCR1 in SDM.\r |
f4d9afde | 1909 | **/\r |
2f88bd3a | 1910 | #define MSR_PENTIUM_4_RAT_ESCR1 0x000003BD\r |
f4d9afde MK |
1911 | \r |
1912 | /**\r | |
ba1a2d11 | 1913 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1914 | \r |
1915 | @param ECX MSR_PENTIUM_4_SSU_ESCR0 (0x000003BE)\r | |
1916 | @param EAX Lower 32-bits of MSR value.\r | |
1917 | @param EDX Upper 32-bits of MSR value.\r | |
1918 | \r | |
1919 | <b>Example usage</b>\r | |
1920 | @code\r | |
1921 | UINT64 Msr;\r | |
1922 | \r | |
1923 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_SSU_ESCR0);\r | |
1924 | AsmWriteMsr64 (MSR_PENTIUM_4_SSU_ESCR0, Msr);\r | |
1925 | @endcode\r | |
8bf98bd0 | 1926 | @note MSR_PENTIUM_4_SSU_ESCR0 is defined as MSR_SSU_ESCR0 in SDM.\r |
f4d9afde | 1927 | **/\r |
2f88bd3a | 1928 | #define MSR_PENTIUM_4_SSU_ESCR0 0x000003BE\r |
f4d9afde MK |
1929 | \r |
1930 | /**\r | |
ba1a2d11 | 1931 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1932 | \r |
1933 | @param ECX MSR_PENTIUM_4_MS_ESCR0 (0x000003C0)\r | |
1934 | @param EAX Lower 32-bits of MSR value.\r | |
1935 | @param EDX Upper 32-bits of MSR value.\r | |
1936 | \r | |
1937 | <b>Example usage</b>\r | |
1938 | @code\r | |
1939 | UINT64 Msr;\r | |
1940 | \r | |
1941 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR0);\r | |
1942 | AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR0, Msr);\r | |
1943 | @endcode\r | |
8bf98bd0 | 1944 | @note MSR_PENTIUM_4_MS_ESCR0 is defined as MSR_MS_ESCR0 in SDM.\r |
f4d9afde | 1945 | **/\r |
2f88bd3a | 1946 | #define MSR_PENTIUM_4_MS_ESCR0 0x000003C0\r |
f4d9afde MK |
1947 | \r |
1948 | /**\r | |
ba1a2d11 | 1949 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1950 | \r |
1951 | @param ECX MSR_PENTIUM_4_MS_ESCR1 (0x000003C1)\r | |
1952 | @param EAX Lower 32-bits of MSR value.\r | |
1953 | @param EDX Upper 32-bits of MSR value.\r | |
1954 | \r | |
1955 | <b>Example usage</b>\r | |
1956 | @code\r | |
1957 | UINT64 Msr;\r | |
1958 | \r | |
1959 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_MS_ESCR1);\r | |
1960 | AsmWriteMsr64 (MSR_PENTIUM_4_MS_ESCR1, Msr);\r | |
1961 | @endcode\r | |
8bf98bd0 | 1962 | @note MSR_PENTIUM_4_MS_ESCR1 is defined as MSR_MS_ESCR1 in SDM.\r |
f4d9afde | 1963 | **/\r |
2f88bd3a | 1964 | #define MSR_PENTIUM_4_MS_ESCR1 0x000003C1\r |
f4d9afde MK |
1965 | \r |
1966 | /**\r | |
ba1a2d11 | 1967 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1968 | \r |
1969 | @param ECX MSR_PENTIUM_4_TBPU_ESCR0 (0x000003C2)\r | |
1970 | @param EAX Lower 32-bits of MSR value.\r | |
1971 | @param EDX Upper 32-bits of MSR value.\r | |
1972 | \r | |
1973 | <b>Example usage</b>\r | |
1974 | @code\r | |
1975 | UINT64 Msr;\r | |
1976 | \r | |
1977 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR0);\r | |
1978 | AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR0, Msr);\r | |
1979 | @endcode\r | |
8bf98bd0 | 1980 | @note MSR_PENTIUM_4_TBPU_ESCR0 is defined as MSR_TBPU_ESCR0 in SDM.\r |
f4d9afde | 1981 | **/\r |
2f88bd3a | 1982 | #define MSR_PENTIUM_4_TBPU_ESCR0 0x000003C2\r |
f4d9afde MK |
1983 | \r |
1984 | /**\r | |
ba1a2d11 | 1985 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
1986 | \r |
1987 | @param ECX MSR_PENTIUM_4_TBPU_ESCR1 (0x000003C3)\r | |
1988 | @param EAX Lower 32-bits of MSR value.\r | |
1989 | @param EDX Upper 32-bits of MSR value.\r | |
1990 | \r | |
1991 | <b>Example usage</b>\r | |
1992 | @code\r | |
1993 | UINT64 Msr;\r | |
1994 | \r | |
1995 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_TBPU_ESCR1);\r | |
1996 | AsmWriteMsr64 (MSR_PENTIUM_4_TBPU_ESCR1, Msr);\r | |
1997 | @endcode\r | |
8bf98bd0 | 1998 | @note MSR_PENTIUM_4_TBPU_ESCR1 is defined as MSR_TBPU_ESCR1 in SDM.\r |
f4d9afde | 1999 | **/\r |
2f88bd3a | 2000 | #define MSR_PENTIUM_4_TBPU_ESCR1 0x000003C3\r |
f4d9afde MK |
2001 | \r |
2002 | /**\r | |
ba1a2d11 | 2003 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
2004 | \r |
2005 | @param ECX MSR_PENTIUM_4_TC_ESCR0 (0x000003C4)\r | |
2006 | @param EAX Lower 32-bits of MSR value.\r | |
2007 | @param EDX Upper 32-bits of MSR value.\r | |
2008 | \r | |
2009 | <b>Example usage</b>\r | |
2010 | @code\r | |
2011 | UINT64 Msr;\r | |
2012 | \r | |
2013 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR0);\r | |
2014 | AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR0, Msr);\r | |
2015 | @endcode\r | |
8bf98bd0 | 2016 | @note MSR_PENTIUM_4_TC_ESCR0 is defined as MSR_TC_ESCR0 in SDM.\r |
f4d9afde | 2017 | **/\r |
2f88bd3a | 2018 | #define MSR_PENTIUM_4_TC_ESCR0 0x000003C4\r |
f4d9afde MK |
2019 | \r |
2020 | /**\r | |
ba1a2d11 | 2021 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
2022 | \r |
2023 | @param ECX MSR_PENTIUM_4_TC_ESCR1 (0x000003C5)\r | |
2024 | @param EAX Lower 32-bits of MSR value.\r | |
2025 | @param EDX Upper 32-bits of MSR value.\r | |
2026 | \r | |
2027 | <b>Example usage</b>\r | |
2028 | @code\r | |
2029 | UINT64 Msr;\r | |
2030 | \r | |
2031 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_ESCR1);\r | |
2032 | AsmWriteMsr64 (MSR_PENTIUM_4_TC_ESCR1, Msr);\r | |
2033 | @endcode\r | |
8bf98bd0 | 2034 | @note MSR_PENTIUM_4_TC_ESCR1 is defined as MSR_TC_ESCR1 in SDM.\r |
f4d9afde | 2035 | **/\r |
2f88bd3a | 2036 | #define MSR_PENTIUM_4_TC_ESCR1 0x000003C5\r |
f4d9afde MK |
2037 | \r |
2038 | /**\r | |
ba1a2d11 | 2039 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
2040 | \r |
2041 | @param ECX MSR_PENTIUM_4_IX_ESCR0 (0x000003C8)\r | |
2042 | @param EAX Lower 32-bits of MSR value.\r | |
2043 | @param EDX Upper 32-bits of MSR value.\r | |
2044 | \r | |
2045 | <b>Example usage</b>\r | |
2046 | @code\r | |
2047 | UINT64 Msr;\r | |
2048 | \r | |
2049 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR0);\r | |
2050 | AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR0, Msr);\r | |
2051 | @endcode\r | |
8bf98bd0 | 2052 | @note MSR_PENTIUM_4_IX_ESCR0 is defined as MSR_IX_ESCR0 in SDM.\r |
f4d9afde | 2053 | **/\r |
2f88bd3a | 2054 | #define MSR_PENTIUM_4_IX_ESCR0 0x000003C8\r |
f4d9afde MK |
2055 | \r |
2056 | /**\r | |
ba1a2d11 | 2057 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
2058 | \r |
2059 | @param ECX MSR_PENTIUM_4_IX_ESCR1 (0x000003C9)\r | |
2060 | @param EAX Lower 32-bits of MSR value.\r | |
2061 | @param EDX Upper 32-bits of MSR value.\r | |
2062 | \r | |
2063 | <b>Example usage</b>\r | |
2064 | @code\r | |
2065 | UINT64 Msr;\r | |
2066 | \r | |
2067 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IX_ESCR1);\r | |
2068 | AsmWriteMsr64 (MSR_PENTIUM_4_IX_ESCR1, Msr);\r | |
2069 | @endcode\r | |
8bf98bd0 | 2070 | @note MSR_PENTIUM_4_IX_ESCR1 is defined as MSR_IX_ESCR1 in SDM.\r |
f4d9afde | 2071 | **/\r |
2f88bd3a | 2072 | #define MSR_PENTIUM_4_IX_ESCR1 0x000003C9\r |
f4d9afde MK |
2073 | \r |
2074 | /**\r | |
ba1a2d11 | 2075 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
2076 | \r |
2077 | @param ECX MSR_PENTIUM_4_ALF_ESCRn\r | |
2078 | @param EAX Lower 32-bits of MSR value.\r | |
2079 | @param EDX Upper 32-bits of MSR value.\r | |
2080 | \r | |
2081 | <b>Example usage</b>\r | |
2082 | @code\r | |
2083 | UINT64 Msr;\r | |
2084 | \r | |
2085 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_ALF_ESCR0);\r | |
2086 | AsmWriteMsr64 (MSR_PENTIUM_4_ALF_ESCR0, Msr);\r | |
2087 | @endcode\r | |
8bf98bd0 JF |
2088 | @note MSR_PENTIUM_4_ALF_ESCR0 is defined as MSR_ALF_ESCR0 in SDM.\r |
2089 | MSR_PENTIUM_4_ALF_ESCR1 is defined as MSR_ALF_ESCR1 in SDM.\r | |
2090 | MSR_PENTIUM_4_CRU_ESCR2 is defined as MSR_CRU_ESCR2 in SDM.\r | |
2091 | MSR_PENTIUM_4_CRU_ESCR3 is defined as MSR_CRU_ESCR3 in SDM.\r | |
2092 | MSR_PENTIUM_4_CRU_ESCR4 is defined as MSR_CRU_ESCR4 in SDM.\r | |
2093 | MSR_PENTIUM_4_CRU_ESCR5 is defined as MSR_CRU_ESCR5 in SDM.\r | |
f4d9afde MK |
2094 | @{\r |
2095 | **/\r | |
2f88bd3a MK |
2096 | #define MSR_PENTIUM_4_ALF_ESCR0 0x000003CA\r |
2097 | #define MSR_PENTIUM_4_ALF_ESCR1 0x000003CB\r | |
2098 | #define MSR_PENTIUM_4_CRU_ESCR2 0x000003CC\r | |
2099 | #define MSR_PENTIUM_4_CRU_ESCR3 0x000003CD\r | |
2100 | #define MSR_PENTIUM_4_CRU_ESCR4 0x000003E0\r | |
2101 | #define MSR_PENTIUM_4_CRU_ESCR5 0x000003E1\r | |
f4d9afde MK |
2102 | /// @}\r |
2103 | \r | |
f4d9afde | 2104 | /**\r |
ba1a2d11 | 2105 | 0, 1, 2, 3, 4, 6. Shared. See Section 18.6.3.1, "ESCR MSRs.".\r |
f4d9afde MK |
2106 | \r |
2107 | @param ECX MSR_PENTIUM_4_TC_PRECISE_EVENT (0x000003F0)\r | |
2108 | @param EAX Lower 32-bits of MSR value.\r | |
2109 | @param EDX Upper 32-bits of MSR value.\r | |
2110 | \r | |
2111 | <b>Example usage</b>\r | |
2112 | @code\r | |
2113 | UINT64 Msr;\r | |
2114 | \r | |
2115 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT);\r | |
2116 | AsmWriteMsr64 (MSR_PENTIUM_4_TC_PRECISE_EVENT, Msr);\r | |
2117 | @endcode\r | |
8bf98bd0 | 2118 | @note MSR_PENTIUM_4_TC_PRECISE_EVENT is defined as MSR_TC_PRECISE_EVENT in SDM.\r |
f4d9afde | 2119 | **/\r |
2f88bd3a | 2120 | #define MSR_PENTIUM_4_TC_PRECISE_EVENT 0x000003F0\r |
f4d9afde MK |
2121 | \r |
2122 | /**\r | |
0f16be6d HW |
2123 | 0, 1, 2, 3, 4, 6. Shared. Processor Event Based Sampling (PEBS) (R/W)\r |
2124 | Controls the enabling of processor event sampling and replay tagging.\r | |
f4d9afde MK |
2125 | \r |
2126 | @param ECX MSR_PENTIUM_4_PEBS_ENABLE (0x000003F1)\r | |
2127 | @param EAX Lower 32-bits of MSR value.\r | |
2128 | Described by the type MSR_PENTIUM_4_PEBS_ENABLE_REGISTER.\r | |
2129 | @param EDX Upper 32-bits of MSR value.\r | |
2130 | Described by the type MSR_PENTIUM_4_PEBS_ENABLE_REGISTER.\r | |
2131 | \r | |
2132 | <b>Example usage</b>\r | |
2133 | @code\r | |
2134 | MSR_PENTIUM_4_PEBS_ENABLE_REGISTER Msr;\r | |
2135 | \r | |
2136 | Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_ENABLE);\r | |
2137 | AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_ENABLE, Msr.Uint64);\r | |
2138 | @endcode\r | |
8bf98bd0 | 2139 | @note MSR_PENTIUM_4_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r |
f4d9afde | 2140 | **/\r |
2f88bd3a | 2141 | #define MSR_PENTIUM_4_PEBS_ENABLE 0x000003F1\r |
f4d9afde MK |
2142 | \r |
2143 | /**\r | |
2144 | MSR information returned for MSR index #MSR_PENTIUM_4_PEBS_ENABLE\r | |
2145 | **/\r | |
2146 | typedef union {\r | |
2147 | ///\r | |
2148 | /// Individual bit fields\r | |
2149 | ///\r | |
2150 | struct {\r | |
2151 | ///\r | |
ba1a2d11 | 2152 | /// [Bits 12:0] See Table 19-36.\r |
f4d9afde | 2153 | ///\r |
2f88bd3a MK |
2154 | UINT32 EventNum : 13;\r |
2155 | UINT32 Reserved1 : 11;\r | |
f4d9afde MK |
2156 | ///\r |
2157 | /// [Bit 24] UOP Tag Enables replay tagging when set.\r | |
2158 | ///\r | |
2f88bd3a | 2159 | UINT32 UOP : 1;\r |
f4d9afde MK |
2160 | ///\r |
2161 | /// [Bit 25] ENABLE_PEBS_MY_THR (R/W) Enables PEBS for the target logical\r | |
2162 | /// processor when set; disables PEBS when clear (default). See Section\r | |
ba1a2d11 | 2163 | /// 18.6.4.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target\r |
f4d9afde MK |
2164 | /// logical processor. This bit is called ENABLE_PEBS in IA-32 processors\r |
2165 | /// that do not support Intel HyperThreading Technology.\r | |
2166 | ///\r | |
2f88bd3a | 2167 | UINT32 ENABLE_PEBS_MY_THR : 1;\r |
f4d9afde MK |
2168 | ///\r |
2169 | /// [Bit 26] ENABLE_PEBS_OTH_THR (R/W) Enables PEBS for the target logical\r | |
2170 | /// processor when set; disables PEBS when clear (default). See Section\r | |
ba1a2d11 | 2171 | /// 18.6.4.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target\r |
f4d9afde MK |
2172 | /// logical processor. This bit is reserved for IA-32 processors that do\r |
2173 | /// not support Intel Hyper-Threading Technology.\r | |
2174 | ///\r | |
2f88bd3a MK |
2175 | UINT32 ENABLE_PEBS_OTH_THR : 1;\r |
2176 | UINT32 Reserved2 : 5;\r | |
2177 | UINT32 Reserved3 : 32;\r | |
f4d9afde MK |
2178 | } Bits;\r |
2179 | ///\r | |
2180 | /// All bit fields as a 32-bit value\r | |
2181 | ///\r | |
2f88bd3a | 2182 | UINT32 Uint32;\r |
f4d9afde MK |
2183 | ///\r |
2184 | /// All bit fields as a 64-bit value\r | |
2185 | ///\r | |
2f88bd3a | 2186 | UINT64 Uint64;\r |
f4d9afde MK |
2187 | } MSR_PENTIUM_4_PEBS_ENABLE_REGISTER;\r |
2188 | \r | |
f4d9afde | 2189 | /**\r |
ba1a2d11 | 2190 | 0, 1, 2, 3, 4, 6. Shared. See Table 19-36.\r |
f4d9afde MK |
2191 | \r |
2192 | @param ECX MSR_PENTIUM_4_PEBS_MATRIX_VERT (0x000003F2)\r | |
2193 | @param EAX Lower 32-bits of MSR value.\r | |
2194 | @param EDX Upper 32-bits of MSR value.\r | |
2195 | \r | |
2196 | <b>Example usage</b>\r | |
2197 | @code\r | |
2198 | UINT64 Msr;\r | |
2199 | \r | |
2200 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT);\r | |
2201 | AsmWriteMsr64 (MSR_PENTIUM_4_PEBS_MATRIX_VERT, Msr);\r | |
2202 | @endcode\r | |
8bf98bd0 | 2203 | @note MSR_PENTIUM_4_PEBS_MATRIX_VERT is defined as MSR_PEBS_MATRIX_VERT in SDM.\r |
f4d9afde | 2204 | **/\r |
2f88bd3a | 2205 | #define MSR_PENTIUM_4_PEBS_MATRIX_VERT 0x000003F2\r |
f4d9afde MK |
2206 | \r |
2207 | /**\r | |
2208 | 3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch\r | |
2209 | record registers on the last branch record stack (680H-68FH). This part of\r | |
2210 | the stack contains pointers to the source instruction for one of the last 16\r | |
2211 | branches, exceptions, or interrupts taken by the processor. The MSRs at\r | |
2212 | 680H-68FH, 6C0H-6CfH are not available in processor releases before family\r | |
2213 | 0FH, model 03H. These MSRs replace MSRs previously located at\r | |
2214 | 1DBH-1DEH.which performed the same function for early releases. See Section\r | |
ba1a2d11 | 2215 | 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording for\r |
f4d9afde MK |
2216 | Processors based on Skylake Microarchitecture.".\r |
2217 | \r | |
2218 | @param ECX MSR_PENTIUM_4_LASTBRANCH_n_FROM_IP\r | |
2219 | @param EAX Lower 32-bits of MSR value.\r | |
2220 | @param EDX Upper 32-bits of MSR value.\r | |
2221 | \r | |
2222 | <b>Example usage</b>\r | |
2223 | @code\r | |
2224 | UINT64 Msr;\r | |
2225 | \r | |
2226 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP);\r | |
2227 | AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP, Msr);\r | |
2228 | @endcode\r | |
8bf98bd0 JF |
2229 | @note MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r |
2230 | MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r | |
2231 | MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r | |
2232 | MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r | |
2233 | MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.\r | |
2234 | MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.\r | |
2235 | MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.\r | |
2236 | MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.\r | |
2237 | MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.\r | |
2238 | MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.\r | |
2239 | MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.\r | |
2240 | MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.\r | |
2241 | MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.\r | |
2242 | MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.\r | |
2243 | MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.\r | |
2244 | MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.\r | |
f4d9afde MK |
2245 | @{\r |
2246 | **/\r | |
2f88bd3a MK |
2247 | #define MSR_PENTIUM_4_LASTBRANCH_0_FROM_IP 0x00000680\r |
2248 | #define MSR_PENTIUM_4_LASTBRANCH_1_FROM_IP 0x00000681\r | |
2249 | #define MSR_PENTIUM_4_LASTBRANCH_2_FROM_IP 0x00000682\r | |
2250 | #define MSR_PENTIUM_4_LASTBRANCH_3_FROM_IP 0x00000683\r | |
2251 | #define MSR_PENTIUM_4_LASTBRANCH_4_FROM_IP 0x00000684\r | |
2252 | #define MSR_PENTIUM_4_LASTBRANCH_5_FROM_IP 0x00000685\r | |
2253 | #define MSR_PENTIUM_4_LASTBRANCH_6_FROM_IP 0x00000686\r | |
2254 | #define MSR_PENTIUM_4_LASTBRANCH_7_FROM_IP 0x00000687\r | |
2255 | #define MSR_PENTIUM_4_LASTBRANCH_8_FROM_IP 0x00000688\r | |
2256 | #define MSR_PENTIUM_4_LASTBRANCH_9_FROM_IP 0x00000689\r | |
2257 | #define MSR_PENTIUM_4_LASTBRANCH_10_FROM_IP 0x0000068A\r | |
2258 | #define MSR_PENTIUM_4_LASTBRANCH_11_FROM_IP 0x0000068B\r | |
2259 | #define MSR_PENTIUM_4_LASTBRANCH_12_FROM_IP 0x0000068C\r | |
2260 | #define MSR_PENTIUM_4_LASTBRANCH_13_FROM_IP 0x0000068D\r | |
2261 | #define MSR_PENTIUM_4_LASTBRANCH_14_FROM_IP 0x0000068E\r | |
2262 | #define MSR_PENTIUM_4_LASTBRANCH_15_FROM_IP 0x0000068F\r | |
f4d9afde MK |
2263 | /// @}\r |
2264 | \r | |
f4d9afde MK |
2265 | /**\r |
2266 | 3, 4, 6. Unique. Last Branch Record n (R/W) One of 16 pairs of last branch\r | |
2267 | record registers on the last branch record stack (6C0H-6CFH). This part of\r | |
2268 | the stack contains pointers to the destination instruction for one of the\r | |
2269 | last 16 branches, exceptions, or interrupts that the processor took. See\r | |
ba1a2d11 | 2270 | Section 17.12, "Last Branch, Call Stack, Interrupt, and Exception Recording\r |
f4d9afde MK |
2271 | for Processors based on Skylake Microarchitecture.".\r |
2272 | \r | |
2273 | @param ECX MSR_PENTIUM_4_LASTBRANCH_n_TO_IP\r | |
2274 | @param EAX Lower 32-bits of MSR value.\r | |
2275 | @param EDX Upper 32-bits of MSR value.\r | |
2276 | \r | |
2277 | <b>Example usage</b>\r | |
2278 | @code\r | |
2279 | UINT64 Msr;\r | |
2280 | \r | |
2281 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP);\r | |
2282 | AsmWriteMsr64 (MSR_PENTIUM_4_LASTBRANCH_0_TO_IP, Msr);\r | |
2283 | @endcode\r | |
8bf98bd0 JF |
2284 | @note MSR_PENTIUM_4_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r |
2285 | MSR_PENTIUM_4_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r | |
2286 | MSR_PENTIUM_4_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r | |
2287 | MSR_PENTIUM_4_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r | |
2288 | MSR_PENTIUM_4_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.\r | |
2289 | MSR_PENTIUM_4_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.\r | |
2290 | MSR_PENTIUM_4_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.\r | |
2291 | MSR_PENTIUM_4_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.\r | |
2292 | MSR_PENTIUM_4_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.\r | |
2293 | MSR_PENTIUM_4_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.\r | |
2294 | MSR_PENTIUM_4_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.\r | |
2295 | MSR_PENTIUM_4_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.\r | |
2296 | MSR_PENTIUM_4_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.\r | |
2297 | MSR_PENTIUM_4_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.\r | |
2298 | MSR_PENTIUM_4_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.\r | |
2299 | MSR_PENTIUM_4_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.\r | |
f4d9afde MK |
2300 | @{\r |
2301 | **/\r | |
2f88bd3a MK |
2302 | #define MSR_PENTIUM_4_LASTBRANCH_0_TO_IP 0x000006C0\r |
2303 | #define MSR_PENTIUM_4_LASTBRANCH_1_TO_IP 0x000006C1\r | |
2304 | #define MSR_PENTIUM_4_LASTBRANCH_2_TO_IP 0x000006C2\r | |
2305 | #define MSR_PENTIUM_4_LASTBRANCH_3_TO_IP 0x000006C3\r | |
2306 | #define MSR_PENTIUM_4_LASTBRANCH_4_TO_IP 0x000006C4\r | |
2307 | #define MSR_PENTIUM_4_LASTBRANCH_5_TO_IP 0x000006C5\r | |
2308 | #define MSR_PENTIUM_4_LASTBRANCH_6_TO_IP 0x000006C6\r | |
2309 | #define MSR_PENTIUM_4_LASTBRANCH_7_TO_IP 0x000006C7\r | |
2310 | #define MSR_PENTIUM_4_LASTBRANCH_8_TO_IP 0x000006C8\r | |
2311 | #define MSR_PENTIUM_4_LASTBRANCH_9_TO_IP 0x000006C9\r | |
2312 | #define MSR_PENTIUM_4_LASTBRANCH_10_TO_IP 0x000006CA\r | |
2313 | #define MSR_PENTIUM_4_LASTBRANCH_11_TO_IP 0x000006CB\r | |
2314 | #define MSR_PENTIUM_4_LASTBRANCH_12_TO_IP 0x000006CC\r | |
2315 | #define MSR_PENTIUM_4_LASTBRANCH_13_TO_IP 0x000006CD\r | |
2316 | #define MSR_PENTIUM_4_LASTBRANCH_14_TO_IP 0x000006CE\r | |
2317 | #define MSR_PENTIUM_4_LASTBRANCH_15_TO_IP 0x000006CF\r | |
f4d9afde MK |
2318 | /// @}\r |
2319 | \r | |
f4d9afde | 2320 | /**\r |
ba1a2d11 ED |
2321 | 3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W) See Section\r |
2322 | 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to\r | |
2323 | 8-MByte L3 Cache.".\r | |
f4d9afde MK |
2324 | \r |
2325 | @param ECX MSR_PENTIUM_4_IFSB_BUSQ0 (0x000107CC)\r | |
2326 | @param EAX Lower 32-bits of MSR value.\r | |
2327 | @param EDX Upper 32-bits of MSR value.\r | |
2328 | \r | |
2329 | <b>Example usage</b>\r | |
2330 | @code\r | |
2331 | UINT64 Msr;\r | |
2332 | \r | |
2333 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0);\r | |
2334 | AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ0, Msr);\r | |
2335 | @endcode\r | |
8bf98bd0 | 2336 | @note MSR_PENTIUM_4_IFSB_BUSQ0 is defined as MSR_IFSB_BUSQ0 in SDM.\r |
f4d9afde | 2337 | **/\r |
2f88bd3a | 2338 | #define MSR_PENTIUM_4_IFSB_BUSQ0 0x000107CC\r |
f4d9afde MK |
2339 | \r |
2340 | /**\r | |
2341 | 3, 4. Shared. IFSB BUSQ Event Control and Counter Register (R/W).\r | |
2342 | \r | |
2343 | @param ECX MSR_PENTIUM_4_IFSB_BUSQ1 (0x000107CD)\r | |
2344 | @param EAX Lower 32-bits of MSR value.\r | |
2345 | @param EDX Upper 32-bits of MSR value.\r | |
2346 | \r | |
2347 | <b>Example usage</b>\r | |
2348 | @code\r | |
2349 | UINT64 Msr;\r | |
2350 | \r | |
2351 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1);\r | |
2352 | AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_BUSQ1, Msr);\r | |
2353 | @endcode\r | |
8bf98bd0 | 2354 | @note MSR_PENTIUM_4_IFSB_BUSQ1 is defined as MSR_IFSB_BUSQ1 in SDM.\r |
f4d9afde | 2355 | **/\r |
2f88bd3a | 2356 | #define MSR_PENTIUM_4_IFSB_BUSQ1 0x000107CD\r |
f4d9afde MK |
2357 | \r |
2358 | /**\r | |
ba1a2d11 ED |
2359 | 3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W) See Section\r |
2360 | 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to\r | |
2361 | 8-MByte L3 Cache.".\r | |
f4d9afde MK |
2362 | \r |
2363 | @param ECX MSR_PENTIUM_4_IFSB_SNPQ0 (0x000107CE)\r | |
2364 | @param EAX Lower 32-bits of MSR value.\r | |
2365 | @param EDX Upper 32-bits of MSR value.\r | |
2366 | \r | |
2367 | <b>Example usage</b>\r | |
2368 | @code\r | |
2369 | UINT64 Msr;\r | |
2370 | \r | |
2371 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0);\r | |
2372 | AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ0, Msr);\r | |
2373 | @endcode\r | |
8bf98bd0 | 2374 | @note MSR_PENTIUM_4_IFSB_SNPQ0 is defined as MSR_IFSB_SNPQ0 in SDM.\r |
f4d9afde | 2375 | **/\r |
2f88bd3a | 2376 | #define MSR_PENTIUM_4_IFSB_SNPQ0 0x000107CE\r |
f4d9afde MK |
2377 | \r |
2378 | /**\r | |
2379 | 3, 4. Shared. IFSB SNPQ Event Control and Counter Register (R/W).\r | |
2380 | \r | |
2381 | @param ECX MSR_PENTIUM_4_IFSB_SNPQ1 (0x000107CF)\r | |
2382 | @param EAX Lower 32-bits of MSR value.\r | |
2383 | @param EDX Upper 32-bits of MSR value.\r | |
2384 | \r | |
2385 | <b>Example usage</b>\r | |
2386 | @code\r | |
2387 | UINT64 Msr;\r | |
2388 | \r | |
2389 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1);\r | |
2390 | AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_SNPQ1, Msr);\r | |
2391 | @endcode\r | |
8bf98bd0 | 2392 | @note MSR_PENTIUM_4_IFSB_SNPQ1 is defined as MSR_IFSB_SNPQ1 in SDM.\r |
f4d9afde | 2393 | **/\r |
2f88bd3a | 2394 | #define MSR_PENTIUM_4_IFSB_SNPQ1 0x000107CF\r |
f4d9afde MK |
2395 | \r |
2396 | /**\r | |
ba1a2d11 ED |
2397 | 3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W) See Section\r |
2398 | 18.6.6, "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to\r | |
2399 | 8-MByte L3 Cache.".\r | |
f4d9afde MK |
2400 | \r |
2401 | @param ECX MSR_PENTIUM_4_EFSB_DRDY0 (0x000107D0)\r | |
2402 | @param EAX Lower 32-bits of MSR value.\r | |
2403 | @param EDX Upper 32-bits of MSR value.\r | |
2404 | \r | |
2405 | <b>Example usage</b>\r | |
2406 | @code\r | |
2407 | UINT64 Msr;\r | |
2408 | \r | |
2409 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY0);\r | |
2410 | AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY0, Msr);\r | |
2411 | @endcode\r | |
8bf98bd0 | 2412 | @note MSR_PENTIUM_4_EFSB_DRDY0 is defined as MSR_EFSB_DRDY0 in SDM.\r |
f4d9afde | 2413 | **/\r |
2f88bd3a | 2414 | #define MSR_PENTIUM_4_EFSB_DRDY0 0x000107D0\r |
f4d9afde MK |
2415 | \r |
2416 | /**\r | |
2417 | 3, 4. Shared. EFSB DRDY Event Control and Counter Register (R/W).\r | |
2418 | \r | |
2419 | @param ECX MSR_PENTIUM_4_EFSB_DRDY1 (0x000107D1)\r | |
2420 | @param EAX Lower 32-bits of MSR value.\r | |
2421 | @param EDX Upper 32-bits of MSR value.\r | |
2422 | \r | |
2423 | <b>Example usage</b>\r | |
2424 | @code\r | |
2425 | UINT64 Msr;\r | |
2426 | \r | |
2427 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_EFSB_DRDY1);\r | |
2428 | AsmWriteMsr64 (MSR_PENTIUM_4_EFSB_DRDY1, Msr);\r | |
2429 | @endcode\r | |
8bf98bd0 | 2430 | @note MSR_PENTIUM_4_EFSB_DRDY1 is defined as MSR_EFSB_DRDY1 in SDM.\r |
f4d9afde | 2431 | **/\r |
2f88bd3a | 2432 | #define MSR_PENTIUM_4_EFSB_DRDY1 0x000107D1\r |
f4d9afde MK |
2433 | \r |
2434 | /**\r | |
ba1a2d11 ED |
2435 | 3, 4. Shared. IFSB Latency Event Control Register (R/W) See Section 18.6.6,\r |
2436 | "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte\r | |
2437 | L3 Cache.".\r | |
f4d9afde MK |
2438 | \r |
2439 | @param ECX MSR_PENTIUM_4_IFSB_CTL6 (0x000107D2)\r | |
2440 | @param EAX Lower 32-bits of MSR value.\r | |
2441 | @param EDX Upper 32-bits of MSR value.\r | |
2442 | \r | |
2443 | <b>Example usage</b>\r | |
2444 | @code\r | |
2445 | UINT64 Msr;\r | |
2446 | \r | |
2447 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CTL6);\r | |
2448 | AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CTL6, Msr);\r | |
2449 | @endcode\r | |
8bf98bd0 | 2450 | @note MSR_PENTIUM_4_IFSB_CTL6 is defined as MSR_IFSB_CTL6 in SDM.\r |
f4d9afde | 2451 | **/\r |
2f88bd3a | 2452 | #define MSR_PENTIUM_4_IFSB_CTL6 0x000107D2\r |
f4d9afde MK |
2453 | \r |
2454 | /**\r | |
ba1a2d11 ED |
2455 | 3, 4. Shared. IFSB Latency Event Counter Register (R/W) See Section 18.6.6,\r |
2456 | "Performance Monitoring on 64bit Intel Xeon Processor MP with Up to 8-MByte\r | |
f4d9afde MK |
2457 | L3 Cache.".\r |
2458 | \r | |
2459 | @param ECX MSR_PENTIUM_4_IFSB_CNTR7 (0x000107D3)\r | |
2460 | @param EAX Lower 32-bits of MSR value.\r | |
2461 | @param EDX Upper 32-bits of MSR value.\r | |
2462 | \r | |
2463 | <b>Example usage</b>\r | |
2464 | @code\r | |
2465 | UINT64 Msr;\r | |
2466 | \r | |
2467 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_IFSB_CNTR7);\r | |
2468 | AsmWriteMsr64 (MSR_PENTIUM_4_IFSB_CNTR7, Msr);\r | |
2469 | @endcode\r | |
8bf98bd0 | 2470 | @note MSR_PENTIUM_4_IFSB_CNTR7 is defined as MSR_IFSB_CNTR7 in SDM.\r |
f4d9afde | 2471 | **/\r |
2f88bd3a | 2472 | #define MSR_PENTIUM_4_IFSB_CNTR7 0x000107D3\r |
f4d9afde MK |
2473 | \r |
2474 | /**\r | |
ba1a2d11 ED |
2475 | 6. Shared. GBUSQ Event Control and Counter Register (R/W) See Section\r |
2476 | 18.6.6, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to\r | |
2477 | 8MByte L3 Cache.".\r | |
f4d9afde MK |
2478 | \r |
2479 | @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL0 (0x000107CC)\r | |
2480 | @param EAX Lower 32-bits of MSR value.\r | |
2481 | @param EDX Upper 32-bits of MSR value.\r | |
2482 | \r | |
2483 | <b>Example usage</b>\r | |
2484 | @code\r | |
2485 | UINT64 Msr;\r | |
2486 | \r | |
2487 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0);\r | |
2488 | AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL0, Msr);\r | |
2489 | @endcode\r | |
8bf98bd0 | 2490 | @note MSR_PENTIUM_4_EMON_L3_CTR_CTL0 is defined as MSR_EMON_L3_CTR_CTL0 in SDM.\r |
f4d9afde | 2491 | **/\r |
2f88bd3a | 2492 | #define MSR_PENTIUM_4_EMON_L3_CTR_CTL0 0x000107CC\r |
f4d9afde MK |
2493 | \r |
2494 | /**\r | |
2495 | 6. Shared. GBUSQ Event Control and Counter Register (R/W).\r | |
2496 | \r | |
2497 | @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL1 (0x000107CD)\r | |
2498 | @param EAX Lower 32-bits of MSR value.\r | |
2499 | @param EDX Upper 32-bits of MSR value.\r | |
2500 | \r | |
2501 | <b>Example usage</b>\r | |
2502 | @code\r | |
2503 | UINT64 Msr;\r | |
2504 | \r | |
2505 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1);\r | |
2506 | AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL1, Msr);\r | |
2507 | @endcode\r | |
8bf98bd0 | 2508 | @note MSR_PENTIUM_4_EMON_L3_CTR_CTL1 is defined as MSR_EMON_L3_CTR_CTL1 in SDM.\r |
f4d9afde | 2509 | **/\r |
2f88bd3a | 2510 | #define MSR_PENTIUM_4_EMON_L3_CTR_CTL1 0x000107CD\r |
f4d9afde MK |
2511 | \r |
2512 | /**\r | |
ba1a2d11 ED |
2513 | 6. Shared. GSNPQ Event Control and Counter Register (R/W) See Section\r |
2514 | 18.6.6, "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to\r | |
2515 | 8MByte L3 Cache.".\r | |
f4d9afde MK |
2516 | \r |
2517 | @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL2 (0x000107CE)\r | |
2518 | @param EAX Lower 32-bits of MSR value.\r | |
2519 | @param EDX Upper 32-bits of MSR value.\r | |
2520 | \r | |
2521 | <b>Example usage</b>\r | |
2522 | @code\r | |
2523 | UINT64 Msr;\r | |
2524 | \r | |
2525 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2);\r | |
2526 | AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL2, Msr);\r | |
2527 | @endcode\r | |
8bf98bd0 | 2528 | @note MSR_PENTIUM_4_EMON_L3_CTR_CTL2 is defined as MSR_EMON_L3_CTR_CTL2 in SDM.\r |
f4d9afde | 2529 | **/\r |
2f88bd3a | 2530 | #define MSR_PENTIUM_4_EMON_L3_CTR_CTL2 0x000107CE\r |
f4d9afde MK |
2531 | \r |
2532 | /**\r | |
2533 | 6. Shared. GSNPQ Event Control and Counter Register (R/W).\r | |
2534 | \r | |
2535 | @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL3 (0x000107CF)\r | |
2536 | @param EAX Lower 32-bits of MSR value.\r | |
2537 | @param EDX Upper 32-bits of MSR value.\r | |
2538 | \r | |
2539 | <b>Example usage</b>\r | |
2540 | @code\r | |
2541 | UINT64 Msr;\r | |
2542 | \r | |
2543 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3);\r | |
2544 | AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL3, Msr);\r | |
2545 | @endcode\r | |
8bf98bd0 | 2546 | @note MSR_PENTIUM_4_EMON_L3_CTR_CTL3 is defined as MSR_EMON_L3_CTR_CTL3 in SDM.\r |
f4d9afde | 2547 | **/\r |
2f88bd3a | 2548 | #define MSR_PENTIUM_4_EMON_L3_CTR_CTL3 0x000107CF\r |
f4d9afde MK |
2549 | \r |
2550 | /**\r | |
ba1a2d11 ED |
2551 | 6. Shared. FSB Event Control and Counter Register (R/W) See Section 18.6.6,\r |
2552 | "Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8MByte\r | |
2553 | L3 Cache.".\r | |
f4d9afde MK |
2554 | \r |
2555 | @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL4 (0x000107D0)\r | |
2556 | @param EAX Lower 32-bits of MSR value.\r | |
2557 | @param EDX Upper 32-bits of MSR value.\r | |
2558 | \r | |
2559 | <b>Example usage</b>\r | |
2560 | @code\r | |
2561 | UINT64 Msr;\r | |
2562 | \r | |
2563 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4);\r | |
2564 | AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL4, Msr);\r | |
2565 | @endcode\r | |
8bf98bd0 | 2566 | @note MSR_PENTIUM_4_EMON_L3_CTR_CTL4 is defined as MSR_EMON_L3_CTR_CTL4 in SDM.\r |
f4d9afde | 2567 | **/\r |
2f88bd3a | 2568 | #define MSR_PENTIUM_4_EMON_L3_CTR_CTL4 0x000107D0\r |
f4d9afde MK |
2569 | \r |
2570 | /**\r | |
2571 | 6. Shared. FSB Event Control and Counter Register (R/W).\r | |
2572 | \r | |
2573 | @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL5 (0x000107D1)\r | |
2574 | @param EAX Lower 32-bits of MSR value.\r | |
2575 | @param EDX Upper 32-bits of MSR value.\r | |
2576 | \r | |
2577 | <b>Example usage</b>\r | |
2578 | @code\r | |
2579 | UINT64 Msr;\r | |
2580 | \r | |
2581 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5);\r | |
2582 | AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL5, Msr);\r | |
2583 | @endcode\r | |
8bf98bd0 | 2584 | @note MSR_PENTIUM_4_EMON_L3_CTR_CTL5 is defined as MSR_EMON_L3_CTR_CTL5 in SDM.\r |
f4d9afde | 2585 | **/\r |
2f88bd3a | 2586 | #define MSR_PENTIUM_4_EMON_L3_CTR_CTL5 0x000107D1\r |
f4d9afde MK |
2587 | \r |
2588 | /**\r | |
2589 | 6. Shared. FSB Event Control and Counter Register (R/W).\r | |
2590 | \r | |
2591 | @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL6 (0x000107D2)\r | |
2592 | @param EAX Lower 32-bits of MSR value.\r | |
2593 | @param EDX Upper 32-bits of MSR value.\r | |
2594 | \r | |
2595 | <b>Example usage</b>\r | |
2596 | @code\r | |
2597 | UINT64 Msr;\r | |
2598 | \r | |
2599 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6);\r | |
2600 | AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL6, Msr);\r | |
2601 | @endcode\r | |
8bf98bd0 | 2602 | @note MSR_PENTIUM_4_EMON_L3_CTR_CTL6 is defined as MSR_EMON_L3_CTR_CTL6 in SDM.\r |
f4d9afde | 2603 | **/\r |
2f88bd3a | 2604 | #define MSR_PENTIUM_4_EMON_L3_CTR_CTL6 0x000107D2\r |
f4d9afde MK |
2605 | \r |
2606 | /**\r | |
2607 | 6. Shared. FSB Event Control and Counter Register (R/W).\r | |
2608 | \r | |
2609 | @param ECX MSR_PENTIUM_4_EMON_L3_CTR_CTL7 (0x000107D3)\r | |
2610 | @param EAX Lower 32-bits of MSR value.\r | |
2611 | @param EDX Upper 32-bits of MSR value.\r | |
2612 | \r | |
2613 | <b>Example usage</b>\r | |
2614 | @code\r | |
2615 | UINT64 Msr;\r | |
2616 | \r | |
2617 | Msr = AsmReadMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7);\r | |
2618 | AsmWriteMsr64 (MSR_PENTIUM_4_EMON_L3_CTR_CTL7, Msr);\r | |
2619 | @endcode\r | |
8bf98bd0 | 2620 | @note MSR_PENTIUM_4_EMON_L3_CTR_CTL7 is defined as MSR_EMON_L3_CTR_CTL7 in SDM.\r |
f4d9afde | 2621 | **/\r |
2f88bd3a | 2622 | #define MSR_PENTIUM_4_EMON_L3_CTR_CTL7 0x000107D3\r |
f4d9afde MK |
2623 | \r |
2624 | #endif\r |