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83d4e58c
MK		 1/** @file\r
2 MSR Definitions for Pentium M Processors.\r
3\r
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
5 are provided for MSRs that contain one or more bit fields. If the MSR value\r
6 returned is a single 32-bit or 64-bit value, then a data structure is not\r
7 provided for that MSR.\r
8\r
e057908f 9 Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
0acd8697 10 SPDX-License-Identifier: BSD-2-Clause-Patent\r
83d4e58c
MK		 11\r
12 @par Specification Reference:\r
ba1a2d11
ED		 13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
14 May 2018, Volume 4: Model-Specific-Registers (MSR)\r
83d4e58c
MK		 15\r
16**/\r
17\r
18#ifndef __PENTIUM_M_MSR_H__\r
19#define __PENTIUM_M_MSR_H__\r
20\r
e057908f 21#include <Register/Intel/ArchitecturalMsr.h>\r
83d4e58c 22\r
f4c982bf
JF		 23/**\r
24 Is Pentium M Processors?\r
25\r
26 @param DisplayFamily Display Family ID\r
27 @param DisplayModel Display Model ID\r
28\r
29 @retval TRUE Yes, it is.\r
30 @retval FALSE No, it isn't.\r
31**/\r
32#define IS_PENTIUM_M_PROCESSOR(DisplayFamily, DisplayModel) \\r
33 (DisplayFamily == 0x06 && \\r
34 ( \\r
35 DisplayModel == 0x0D \\r
36 ) \\r
37 )\r
38\r
83d4e58c 39/**\r
ba1a2d11 40 See Section 2.22, "MSRs in Pentium Processors.".\r
83d4e58c
MK		 41\r
42 @param ECX MSR_PENTIUM_M_P5_MC_ADDR (0x00000000)\r
43 @param EAX Lower 32-bits of MSR value.\r
44 @param EDX Upper 32-bits of MSR value.\r
45\r
46 <b>Example usage</b>\r
47 @code\r
48 UINT64 Msr;\r
49\r
50 Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_ADDR);\r
51 AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_ADDR, Msr);\r
52 @endcode\r
65ee84bd 53 @note MSR_PENTIUM_M_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.\r
83d4e58c 54**/\r
2f88bd3a 55#define MSR_PENTIUM_M_P5_MC_ADDR 0x00000000\r
83d4e58c
MK		 56\r
57/**\r
ba1a2d11 58 See Section 2.22, "MSRs in Pentium Processors.".\r
83d4e58c
MK		 59\r
60 @param ECX MSR_PENTIUM_M_P5_MC_TYPE (0x00000001)\r
61 @param EAX Lower 32-bits of MSR value.\r
62 @param EDX Upper 32-bits of MSR value.\r
63\r
64 <b>Example usage</b>\r
65 @code\r
66 UINT64 Msr;\r
67\r
68 Msr = AsmReadMsr64 (MSR_PENTIUM_M_P5_MC_TYPE);\r
69 AsmWriteMsr64 (MSR_PENTIUM_M_P5_MC_TYPE, Msr);\r
70 @endcode\r
65ee84bd 71 @note MSR_PENTIUM_M_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.\r
83d4e58c 72**/\r
2f88bd3a 73#define MSR_PENTIUM_M_P5_MC_TYPE 0x00000001\r
83d4e58c
MK		 74\r
75/**\r
76 Processor Hard Power-On Configuration (R/W) Enables and disables processor\r
77 features. (R) Indicates current processor configuration.\r
78\r
79 @param ECX MSR_PENTIUM_M_EBL_CR_POWERON (0x0000002A)\r
80 @param EAX Lower 32-bits of MSR value.\r
81 Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.\r
82 @param EDX Upper 32-bits of MSR value.\r
83 Described by the type MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER.\r
84\r
85 <b>Example usage</b>\r
86 @code\r
87 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER Msr;\r
88\r
89 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON);\r
90 AsmWriteMsr64 (MSR_PENTIUM_M_EBL_CR_POWERON, Msr.Uint64);\r
91 @endcode\r
65ee84bd 92 @note MSR_PENTIUM_M_EBL_CR_POWERON is defined as MSR_EBL_CR_POWERON in SDM.\r
83d4e58c 93**/\r
2f88bd3a 94#define MSR_PENTIUM_M_EBL_CR_POWERON 0x0000002A\r
83d4e58c
MK		 95\r
96/**\r
97 MSR information returned for MSR index #MSR_PENTIUM_M_EBL_CR_POWERON\r
98**/\r
99typedef union {\r
100 ///\r
101 /// Individual bit fields\r
102 ///\r
103 struct {\r
2f88bd3a 104 UINT32 Reserved1 : 1;\r
83d4e58c
MK		 105 ///\r
106 /// [Bit 1] Data Error Checking Enable (R) 0 = Disabled Always 0 on the\r
107 /// Pentium M processor.\r
108 ///\r
2f88bd3a 109 UINT32 DataErrorCheckingEnable : 1;\r
83d4e58c
MK		 110 ///\r
111 /// [Bit 2] Response Error Checking Enable (R) 0 = Disabled Always 0 on\r
112 /// the Pentium M processor.\r
113 ///\r
2f88bd3a 114 UINT32 ResponseErrorCheckingEnable : 1;\r
83d4e58c
MK		 115 ///\r
116 /// [Bit 3] MCERR# Drive Enable (R) 0 = Disabled Always 0 on the Pentium\r
117 /// M processor.\r
118 ///\r
2f88bd3a 119 UINT32 MCERR_DriveEnable : 1;\r
83d4e58c
MK		 120 ///\r
121 /// [Bit 4] Address Parity Enable (R) 0 = Disabled Always 0 on the Pentium\r
122 /// M processor.\r
123 ///\r
2f88bd3a
MK		 124 UINT32 AddressParityEnable : 1;\r
125 UINT32 Reserved2 : 2;\r
83d4e58c
MK		 126 ///\r
127 /// [Bit 7] BINIT# Driver Enable (R) 1 = Enabled; 0 = Disabled Always 0 on\r
128 /// the Pentium M processor.\r
129 ///\r
2f88bd3a 130 UINT32 BINIT_DriverEnable : 1;\r
83d4e58c
MK		 131 ///\r
132 /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
133 ///\r
2f88bd3a 134 UINT32 OutputTriStateEnable : 1;\r
83d4e58c
MK		 135 ///\r
136 /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.\r
137 ///\r
2f88bd3a 138 UINT32 ExecuteBIST : 1;\r
83d4e58c
MK		 139 ///\r
140 /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r
141 /// Always 0 on the Pentium M processor.\r
142 ///\r
2f88bd3a
MK		 143 UINT32 MCERR_ObservationEnabled : 1;\r
144 UINT32 Reserved3 : 1;\r
83d4e58c
MK		 145 ///\r
146 /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled\r
147 /// Always 0 on the Pentium M processor.\r
148 ///\r
2f88bd3a
MK		 149 UINT32 BINIT_ObservationEnabled : 1;\r
150 UINT32 Reserved4 : 1;\r
83d4e58c
MK		 151 ///\r
152 /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes\r
153 /// Always 0 on the Pentium M processor.\r
154 ///\r
2f88bd3a
MK		 155 UINT32 ResetVector : 1;\r
156 UINT32 Reserved5 : 1;\r
83d4e58c
MK		 157 ///\r
158 /// [Bits 17:16] APIC Cluster ID (R/O) Always 00B on the Pentium M\r
159 /// processor.\r
160 ///\r
2f88bd3a 161 UINT32 APICClusterID : 2;\r
83d4e58c
MK		 162 ///\r
163 /// [Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved Always\r
164 /// 0 on the Pentium M processor.\r
165 ///\r
2f88bd3a
MK		 166 UINT32 SystemBusFrequency : 1;\r
167 UINT32 Reserved6 : 1;\r
83d4e58c
MK		 168 ///\r
169 /// [Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B on the Pentium\r
170 /// M processor.\r
171 ///\r
2f88bd3a 172 UINT32 SymmetricArbitrationID : 2;\r
83d4e58c
MK		 173 ///\r
174 /// [Bits 26:22] Clock Frequency Ratio (R/O).\r
175 ///\r
2f88bd3a
MK		 176 UINT32 ClockFrequencyRatio : 5;\r
177 UINT32 Reserved7 : 5;\r
178 UINT32 Reserved8 : 32;\r
83d4e58c
MK		 179 } Bits;\r
180 ///\r
181 /// All bit fields as a 32-bit value\r
182 ///\r
2f88bd3a 183 UINT32 Uint32;\r
83d4e58c
MK		 184 ///\r
185 /// All bit fields as a 64-bit value\r
186 ///\r
2f88bd3a 187 UINT64 Uint64;\r
83d4e58c
MK		 188} MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER;\r
189\r
83d4e58c
MK		 190/**\r
191 Last Branch Record n (R/W) One of 8 last branch record registers on the last\r
192 branch record stack: bits 31-0 hold the 'from' address and bits 63-32 hold\r
193 the to address. See also: - Last Branch Record Stack TOS at 1C9H - Section\r
ba1a2d11 194 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M\r
83d4e58c
MK		 195 Processors)".\r
196\r
197 @param ECX MSR_PENTIUM_M_LASTBRANCH_n\r
198 @param EAX Lower 32-bits of MSR value.\r
199 @param EDX Upper 32-bits of MSR value.\r
200\r
201 <b>Example usage</b>\r
202 @code\r
203 UINT64 Msr;\r
204\r
205 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_0);\r
206 AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_0, Msr);\r
207 @endcode\r
65ee84bd
JF		 208 @note MSR_PENTIUM_M_LASTBRANCH_0 is defined as MSR_LASTBRANCH_0 in SDM.\r
209 MSR_PENTIUM_M_LASTBRANCH_1 is defined as MSR_LASTBRANCH_1 in SDM.\r
210 MSR_PENTIUM_M_LASTBRANCH_2 is defined as MSR_LASTBRANCH_2 in SDM.\r
211 MSR_PENTIUM_M_LASTBRANCH_3 is defined as MSR_LASTBRANCH_3 in SDM.\r
212 MSR_PENTIUM_M_LASTBRANCH_4 is defined as MSR_LASTBRANCH_4 in SDM.\r
213 MSR_PENTIUM_M_LASTBRANCH_5 is defined as MSR_LASTBRANCH_5 in SDM.\r
214 MSR_PENTIUM_M_LASTBRANCH_6 is defined as MSR_LASTBRANCH_6 in SDM.\r
215 MSR_PENTIUM_M_LASTBRANCH_7 is defined as MSR_LASTBRANCH_7 in SDM.\r
83d4e58c
MK		 216 @{\r
217**/\r
2f88bd3a
MK		 218#define MSR_PENTIUM_M_LASTBRANCH_0 0x00000040\r
219#define MSR_PENTIUM_M_LASTBRANCH_1 0x00000041\r
220#define MSR_PENTIUM_M_LASTBRANCH_2 0x00000042\r
221#define MSR_PENTIUM_M_LASTBRANCH_3 0x00000043\r
222#define MSR_PENTIUM_M_LASTBRANCH_4 0x00000044\r
223#define MSR_PENTIUM_M_LASTBRANCH_5 0x00000045\r
224#define MSR_PENTIUM_M_LASTBRANCH_6 0x00000046\r
225#define MSR_PENTIUM_M_LASTBRANCH_7 0x00000047\r
83d4e58c
MK		 226/// @}\r
227\r
83d4e58c
MK		 228/**\r
229 Reserved.\r
230\r
231 @param ECX MSR_PENTIUM_M_BBL_CR_CTL (0x00000119)\r
232 @param EAX Lower 32-bits of MSR value.\r
233 @param EDX Upper 32-bits of MSR value.\r
234\r
235 <b>Example usage</b>\r
236 @code\r
237 UINT64 Msr;\r
238\r
239 Msr = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL);\r
240 AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL, Msr);\r
241 @endcode\r
65ee84bd 242 @note MSR_PENTIUM_M_BBL_CR_CTL is defined as MSR_BBL_CR_CTL in SDM.\r
83d4e58c 243**/\r
2f88bd3a 244#define MSR_PENTIUM_M_BBL_CR_CTL 0x00000119\r
83d4e58c
MK		 245\r
246/**\r
247\r
248\r
249 @param ECX MSR_PENTIUM_M_BBL_CR_CTL3 (0x0000011E)\r
250 @param EAX Lower 32-bits of MSR value.\r
251 Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.\r
252 @param EDX Upper 32-bits of MSR value.\r
253 Described by the type MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER.\r
254\r
255 <b>Example usage</b>\r
256 @code\r
257 MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER Msr;\r
258\r
259 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3);\r
260 AsmWriteMsr64 (MSR_PENTIUM_M_BBL_CR_CTL3, Msr.Uint64);\r
261 @endcode\r
65ee84bd 262 @note MSR_PENTIUM_M_BBL_CR_CTL3 is defined as MSR_BBL_CR_CTL3 in SDM.\r
83d4e58c 263**/\r
2f88bd3a 264#define MSR_PENTIUM_M_BBL_CR_CTL3 0x0000011E\r
83d4e58c
MK		 265\r
266/**\r
267 MSR information returned for MSR index #MSR_PENTIUM_M_BBL_CR_CTL3\r
268**/\r
269typedef union {\r
270 ///\r
271 /// Individual bit fields\r
272 ///\r
273 struct {\r
274 ///\r
275 /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r
276 /// Indicates if the L2 is hardware-disabled.\r
277 ///\r
2f88bd3a
MK		 278 UINT32 L2HardwareEnabled : 1;\r
279 UINT32 Reserved1 : 4;\r
83d4e58c
MK		 280 ///\r
281 /// [Bit 5] ECC Check Enable (RO) This bit enables ECC checking on the\r
282 /// cache data bus. ECC is always generated on write cycles. 1. = Disabled\r
283 /// (default) 2. = Enabled For the Pentium M processor, ECC checking on\r
284 /// the cache data bus is always enabled.\r
285 ///\r
2f88bd3a
MK		 286 UINT32 ECCCheckEnable : 1;\r
287 UINT32 Reserved2 : 2;\r
83d4e58c
MK		 288 ///\r
289 /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =\r
290 /// Disabled (default) Until this bit is set the processor will not\r
291 /// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r
292 ///\r
2f88bd3a
MK		 293 UINT32 L2Enabled : 1;\r
294 UINT32 Reserved3 : 14;\r
83d4e58c
MK		 295 ///\r
296 /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.\r
297 ///\r
2f88bd3a
MK		 298 UINT32 L2NotPresent : 1;\r
299 UINT32 Reserved4 : 8;\r
300 UINT32 Reserved5 : 32;\r
83d4e58c
MK		 301 } Bits;\r
302 ///\r
303 /// All bit fields as a 32-bit value\r
304 ///\r
2f88bd3a 305 UINT32 Uint32;\r
83d4e58c
MK		 306 ///\r
307 /// All bit fields as a 64-bit value\r
308 ///\r
2f88bd3a 309 UINT64 Uint64;\r
83d4e58c
MK		 310} MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER;\r
311\r
83d4e58c
MK		 312/**\r
313\r
314\r
315 @param ECX MSR_PENTIUM_M_THERM2_CTL (0x0000019D)\r
316 @param EAX Lower 32-bits of MSR value.\r
317 Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.\r
318 @param EDX Upper 32-bits of MSR value.\r
319 Described by the type MSR_PENTIUM_M_THERM2_CTL_REGISTER.\r
320\r
321 <b>Example usage</b>\r
322 @code\r
323 MSR_PENTIUM_M_THERM2_CTL_REGISTER Msr;\r
324\r
325 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_THERM2_CTL);\r
326 AsmWriteMsr64 (MSR_PENTIUM_M_THERM2_CTL, Msr.Uint64);\r
327 @endcode\r
65ee84bd 328 @note MSR_PENTIUM_M_THERM2_CTL is defined as MSR_THERM2_CTL in SDM.\r
83d4e58c 329**/\r
2f88bd3a 330#define MSR_PENTIUM_M_THERM2_CTL 0x0000019D\r
83d4e58c
MK		 331\r
332/**\r
333 MSR information returned for MSR index #MSR_PENTIUM_M_THERM2_CTL\r
334**/\r
335typedef union {\r
336 ///\r
337 /// Individual bit fields\r
338 ///\r
339 struct {\r
2f88bd3a 340 UINT32 Reserved1 : 16;\r
83d4e58c
MK		 341 ///\r
342 /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =\r
343 /// Thermal Monitor 1 (thermally-initiated on-die modulation of the\r
344 /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated\r
345 /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is\r
346 /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.\r
347 ///\r
2f88bd3a
MK		 348 UINT32 TM_SELECT : 1;\r
349 UINT32 Reserved2 : 15;\r
350 UINT32 Reserved3 : 32;\r
83d4e58c
MK		 351 } Bits;\r
352 ///\r
353 /// All bit fields as a 32-bit value\r
354 ///\r
2f88bd3a 355 UINT32 Uint32;\r
83d4e58c
MK		 356 ///\r
357 /// All bit fields as a 64-bit value\r
358 ///\r
2f88bd3a 359 UINT64 Uint64;\r
83d4e58c
MK		 360} MSR_PENTIUM_M_THERM2_CTL_REGISTER;\r
361\r
83d4e58c
MK		 362/**\r
363 Enable Miscellaneous Processor Features (R/W) Allows a variety of processor\r
364 functions to be enabled and disabled.\r
365\r
366 @param ECX MSR_PENTIUM_M_IA32_MISC_ENABLE (0x000001A0)\r
367 @param EAX Lower 32-bits of MSR value.\r
368 Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.\r
369 @param EDX Upper 32-bits of MSR value.\r
370 Described by the type MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER.\r
371\r
372 <b>Example usage</b>\r
373 @code\r
374 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER Msr;\r
375\r
376 Msr.Uint64 = AsmReadMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE);\r
377 AsmWriteMsr64 (MSR_PENTIUM_M_IA32_MISC_ENABLE, Msr.Uint64);\r
378 @endcode\r
65ee84bd 379 @note MSR_PENTIUM_M_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r
83d4e58c 380**/\r
2f88bd3a 381#define MSR_PENTIUM_M_IA32_MISC_ENABLE 0x000001A0\r
83d4e58c
MK		 382\r
383/**\r
384 MSR information returned for MSR index #MSR_PENTIUM_M_IA32_MISC_ENABLE\r
385**/\r
386typedef union {\r
387 ///\r
388 /// Individual bit fields\r
389 ///\r
390 struct {\r
2f88bd3a 391 UINT32 Reserved1 : 3;\r
83d4e58c
MK		 392 ///\r
393 /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting\r
394 /// this bit enables the thermal control circuit (TCC) portion of the\r
395 /// Intel Thermal Monitor feature. This allows processor clocks to be\r
396 /// automatically modulated based on the processor's thermal sensor\r
397 /// operation. 0 = Disabled (default). The automatic thermal control\r
398 /// circuit enable bit determines if the thermal control circuit (TCC)\r
399 /// will be activated when the processor's internal thermal sensor\r
400 /// determines the processor is about to exceed its maximum operating\r
401 /// temperature. When the TCC is activated and TM1 is enabled, the\r
402 /// processors clocks will be forced to a 50% duty cycle. BIOS must enable\r
403 /// this feature. The bit should not be confused with the on-demand\r
404 /// thermal control circuit enable bit.\r
405 ///\r
2f88bd3a
MK		 406 UINT32 AutomaticThermalControlCircuit : 1;\r
407 UINT32 Reserved2 : 3;\r
83d4e58c
MK		 408 ///\r
409 /// [Bit 7] Performance Monitoring Available (R) 1 = Performance\r
410 /// monitoring enabled 0 = Performance monitoring disabled.\r
411 ///\r
2f88bd3a
MK		 412 UINT32 PerformanceMonitoring : 1;\r
413 UINT32 Reserved3 : 2;\r
83d4e58c
MK		 414 ///\r
415 /// [Bit 10] FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the\r
416 /// processor to indicate a pending break event within the processor 0 =\r
417 /// Indicates compatible FERR# signaling behavior This bit must be set to\r
418 /// 1 to support XAPIC interrupt model usage.\r
419 /// **Branch Trace Storage Unavailable (RO)** 1 = Processor doesn't\r
420 /// support branch trace storage (BTS) 0 = BTS is supported\r
421 ///\r
2f88bd3a 422 UINT32 FERR : 1;\r
83d4e58c
MK		 423 ///\r
424 /// [Bit 11] Branch Trace Storage Unavailable (RO)\r
425 /// 1 = Processor doesn't support branch trace storage (BTS)\r
426 /// 0 = BTS is supported\r
427 ///\r
2f88bd3a 428 UINT32 BTS : 1;\r
83d4e58c 429 ///\r
0f16be6d
HW		 430 /// [Bit 12] Processor Event Based Sampling Unavailable (RO) 1 =\r
431 /// Processor does not support processor event based sampling (PEBS); 0 =\r
432 /// PEBS is supported. The Pentium M processor does not support PEBS.\r
83d4e58c 433 ///\r
2f88bd3a
MK		 434 UINT32 PEBS : 1;\r
435 UINT32 Reserved5 : 3;\r
83d4e58c
MK		 436 ///\r
437 /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 1 =\r
438 /// Enhanced Intel SpeedStep Technology enabled. On the Pentium M\r
439 /// processor, this bit may be configured to be read-only.\r
440 ///\r
2f88bd3a
MK		 441 UINT32 EIST : 1;\r
442 UINT32 Reserved6 : 6;\r
83d4e58c
MK		 443 ///\r
444 /// [Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are\r
445 /// disabled. xTPR messages are optional messages that allow the processor\r
446 /// to inform the chipset of its priority. The default is processor\r
447 /// specific.\r
448 ///\r
2f88bd3a
MK		 449 UINT32 xTPR_Message_Disable : 1;\r
450 UINT32 Reserved7 : 8;\r
451 UINT32 Reserved8 : 32;\r
83d4e58c
MK		 452 } Bits;\r
453 ///\r
454 /// All bit fields as a 32-bit value\r
455 ///\r
2f88bd3a 456 UINT32 Uint32;\r
83d4e58c
MK		 457 ///\r
458 /// All bit fields as a 64-bit value\r
459 ///\r
2f88bd3a 460 UINT64 Uint64;\r
83d4e58c
MK		 461} MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER;\r
462\r
83d4e58c
MK		 463/**\r
464 Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3) that points\r
465 to the MSR containing the most recent branch record. See also: -\r
0f16be6d 466 MSR_LASTBRANCH_0_FROM_IP (at 40H) - Section 17.13, "Last Branch, Interrupt,\r
83d4e58c
MK		 467 and Exception Recording (Pentium M Processors)".\r
468\r
469 @param ECX MSR_PENTIUM_M_LASTBRANCH_TOS (0x000001C9)\r
470 @param EAX Lower 32-bits of MSR value.\r
471 @param EDX Upper 32-bits of MSR value.\r
472\r
473 <b>Example usage</b>\r
474 @code\r
475 UINT64 Msr;\r
476\r
477 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS);\r
478 AsmWriteMsr64 (MSR_PENTIUM_M_LASTBRANCH_TOS, Msr);\r
479 @endcode\r
65ee84bd 480 @note MSR_PENTIUM_M_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r
83d4e58c 481**/\r
2f88bd3a 482#define MSR_PENTIUM_M_LASTBRANCH_TOS 0x000001C9\r
83d4e58c
MK		 483\r
484/**\r
485 Debug Control (R/W) Controls how several debug features are used. Bit\r
ba1a2d11 486 definitions are discussed in the referenced section. See Section 17.15,\r
83d4e58c
MK		 487 "Last Branch, Interrupt, and Exception Recording (Pentium M Processors).".\r
488\r
489 @param ECX MSR_PENTIUM_M_DEBUGCTLB (0x000001D9)\r
490 @param EAX Lower 32-bits of MSR value.\r
491 @param EDX Upper 32-bits of MSR value.\r
492\r
493 <b>Example usage</b>\r
494 @code\r
495 UINT64 Msr;\r
496\r
497 Msr = AsmReadMsr64 (MSR_PENTIUM_M_DEBUGCTLB);\r
498 AsmWriteMsr64 (MSR_PENTIUM_M_DEBUGCTLB, Msr);\r
499 @endcode\r
65ee84bd 500 @note MSR_PENTIUM_M_DEBUGCTLB is defined as MSR_DEBUGCTLB in SDM.\r
83d4e58c 501**/\r
2f88bd3a 502#define MSR_PENTIUM_M_DEBUGCTLB 0x000001D9\r
83d4e58c
MK		 503\r
504/**\r
505 Last Exception Record To Linear IP (R) This area contains a pointer to the\r
506 target of the last branch instruction that the processor executed prior to\r
507 the last exception that was generated or the last interrupt that was\r
ba1a2d11
ED		 508 handled. See Section 17.15, "Last Branch, Interrupt, and Exception Recording\r
509 (Pentium M Processors)" and Section 17.16.2, "Last Branch and Last Exception\r
83d4e58c
MK		 510 MSRs.".\r
511\r
512 @param ECX MSR_PENTIUM_M_LER_TO_LIP (0x000001DD)\r
513 @param EAX Lower 32-bits of MSR value.\r
514 @param EDX Upper 32-bits of MSR value.\r
515\r
516 <b>Example usage</b>\r
517 @code\r
518 UINT64 Msr;\r
519\r
520 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_TO_LIP);\r
521 @endcode\r
65ee84bd 522 @note MSR_PENTIUM_M_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r
83d4e58c 523**/\r
2f88bd3a 524#define MSR_PENTIUM_M_LER_TO_LIP 0x000001DD\r
83d4e58c
MK		 525\r
526/**\r
527 Last Exception Record From Linear IP (R) Contains a pointer to the last\r
528 branch instruction that the processor executed prior to the last exception\r
529 that was generated or the last interrupt that was handled. See Section\r
ba1a2d11
ED		 530 17.15, "Last Branch, Interrupt, and Exception Recording (Pentium M\r
531 Processors)" and Section 17.16.2, "Last Branch and Last Exception MSRs.".\r
83d4e58c
MK		 532\r
533 @param ECX MSR_PENTIUM_M_LER_FROM_LIP (0x000001DE)\r
534 @param EAX Lower 32-bits of MSR value.\r
535 @param EDX Upper 32-bits of MSR value.\r
536\r
537 <b>Example usage</b>\r
538 @code\r
539 UINT64 Msr;\r
540\r
541 Msr = AsmReadMsr64 (MSR_PENTIUM_M_LER_FROM_LIP);\r
542 @endcode\r
65ee84bd 543 @note MSR_PENTIUM_M_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r
83d4e58c 544**/\r
2f88bd3a 545#define MSR_PENTIUM_M_LER_FROM_LIP 0x000001DE\r
83d4e58c
MK		 546\r
547/**\r
548 See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
549\r
550 @param ECX MSR_PENTIUM_M_MC4_CTL (0x0000040C)\r
551 @param EAX Lower 32-bits of MSR value.\r
552 @param EDX Upper 32-bits of MSR value.\r
553\r
554 <b>Example usage</b>\r
555 @code\r
556 UINT64 Msr;\r
557\r
558 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_CTL);\r
559 AsmWriteMsr64 (MSR_PENTIUM_M_MC4_CTL, Msr);\r
560 @endcode\r
65ee84bd 561 @note MSR_PENTIUM_M_MC4_CTL is defined as MSR_MC4_CTL in SDM.\r
83d4e58c 562**/\r
2f88bd3a 563#define MSR_PENTIUM_M_MC4_CTL 0x0000040C\r
83d4e58c
MK		 564\r
565/**\r
566 See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
567\r
568 @param ECX MSR_PENTIUM_M_MC4_STATUS (0x0000040D)\r
569 @param EAX Lower 32-bits of MSR value.\r
570 @param EDX Upper 32-bits of MSR value.\r
571\r
572 <b>Example usage</b>\r
573 @code\r
574 UINT64 Msr;\r
575\r
576 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_STATUS);\r
577 AsmWriteMsr64 (MSR_PENTIUM_M_MC4_STATUS, Msr);\r
578 @endcode\r
65ee84bd 579 @note MSR_PENTIUM_M_MC4_STATUS is defined as MSR_MC4_STATUS in SDM.\r
83d4e58c 580**/\r
2f88bd3a 581#define MSR_PENTIUM_M_MC4_STATUS 0x0000040D\r
83d4e58c
MK		 582\r
583/**\r
584 See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR register is\r
585 either not implemented or contains no address if the ADDRV flag in the\r
586 MSR_MC4_STATUS register is clear. When not implemented in the processor, all\r
587 reads and writes to this MSR will cause a general-protection exception.\r
588\r
589 @param ECX MSR_PENTIUM_M_MC4_ADDR (0x0000040E)\r
590 @param EAX Lower 32-bits of MSR value.\r
591 @param EDX Upper 32-bits of MSR value.\r
592\r
593 <b>Example usage</b>\r
594 @code\r
595 UINT64 Msr;\r
596\r
597 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC4_ADDR);\r
598 AsmWriteMsr64 (MSR_PENTIUM_M_MC4_ADDR, Msr);\r
599 @endcode\r
65ee84bd 600 @note MSR_PENTIUM_M_MC4_ADDR is defined as MSR_MC4_ADDR in SDM.\r
83d4e58c 601**/\r
2f88bd3a 602#define MSR_PENTIUM_M_MC4_ADDR 0x0000040E\r
83d4e58c
MK		 603\r
604/**\r
605 See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
606\r
607 @param ECX MSR_PENTIUM_M_MC3_CTL (0x00000410)\r
608 @param EAX Lower 32-bits of MSR value.\r
609 @param EDX Upper 32-bits of MSR value.\r
610\r
611 <b>Example usage</b>\r
612 @code\r
613 UINT64 Msr;\r
614\r
615 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_CTL);\r
616 AsmWriteMsr64 (MSR_PENTIUM_M_MC3_CTL, Msr);\r
617 @endcode\r
65ee84bd 618 @note MSR_PENTIUM_M_MC3_CTL is defined as MSR_MC3_CTL in SDM.\r
83d4e58c 619**/\r
2f88bd3a 620#define MSR_PENTIUM_M_MC3_CTL 0x00000410\r
83d4e58c
MK		 621\r
622/**\r
623 See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
624\r
625 @param ECX MSR_PENTIUM_M_MC3_STATUS (0x00000411)\r
626 @param EAX Lower 32-bits of MSR value.\r
627 @param EDX Upper 32-bits of MSR value.\r
628\r
629 <b>Example usage</b>\r
630 @code\r
631 UINT64 Msr;\r
632\r
633 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_STATUS);\r
634 AsmWriteMsr64 (MSR_PENTIUM_M_MC3_STATUS, Msr);\r
635 @endcode\r
65ee84bd 636 @note MSR_PENTIUM_M_MC3_STATUS is defined as MSR_MC3_STATUS in SDM.\r
83d4e58c 637**/\r
2f88bd3a 638#define MSR_PENTIUM_M_MC3_STATUS 0x00000411\r
83d4e58c
MK		 639\r
640/**\r
641 See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR register is\r
642 either not implemented or contains no address if the ADDRV flag in the\r
643 MSR_MC3_STATUS register is clear. When not implemented in the processor, all\r
644 reads and writes to this MSR will cause a general-protection exception.\r
645\r
646 @param ECX MSR_PENTIUM_M_MC3_ADDR (0x00000412)\r
647 @param EAX Lower 32-bits of MSR value.\r
648 @param EDX Upper 32-bits of MSR value.\r
649\r
650 <b>Example usage</b>\r
651 @code\r
652 UINT64 Msr;\r
653\r
654 Msr = AsmReadMsr64 (MSR_PENTIUM_M_MC3_ADDR);\r
655 AsmWriteMsr64 (MSR_PENTIUM_M_MC3_ADDR, Msr);\r
656 @endcode\r
65ee84bd 657 @note MSR_PENTIUM_M_MC3_ADDR is defined as MSR_MC3_ADDR in SDM.\r
83d4e58c 658**/\r
2f88bd3a 659#define MSR_PENTIUM_M_MC3_ADDR 0x00000412\r
83d4e58c
MK		 660\r
661#endif\r
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