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1 | /** @file\r |
2 | MSR Definitions for Pentium Processors.\r | |
3 | \r | |
4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
7 | provided for that MSR.\r | |
8 | \r | |
e057908f | 9 | Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r |
0acd8697 | 10 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
a1e8e34d MK |
11 | \r |
12 | @par Specification Reference:\r | |
ba1a2d11 ED |
13 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r |
14 | May 2018, Volume 4: Model-Specific-Registers (MSR)\r | |
a1e8e34d MK |
15 | \r |
16 | **/\r | |
17 | \r | |
18 | #ifndef __PENTIUM_MSR_H__\r | |
19 | #define __PENTIUM_MSR_H__\r | |
20 | \r | |
e057908f | 21 | #include <Register/Intel/ArchitecturalMsr.h>\r |
a1e8e34d | 22 | \r |
f4c982bf JF |
23 | /**\r |
24 | Is Pentium Processors?\r | |
25 | \r | |
26 | @param DisplayFamily Display Family ID\r | |
27 | @param DisplayModel Display Model ID\r | |
28 | \r | |
29 | @retval TRUE Yes, it is.\r | |
30 | @retval FALSE No, it isn't.\r | |
31 | **/\r | |
32 | #define IS_PENTIUM_PROCESSOR(DisplayFamily, DisplayModel) \\r | |
33 | (DisplayFamily == 0x05 && \\r | |
34 | ( \\r | |
35 | DisplayModel == 0x01 || \\r | |
36 | DisplayModel == 0x02 || \\r | |
37 | DisplayModel == 0x04 \\r | |
38 | ) \\r | |
39 | )\r | |
40 | \r | |
a1e8e34d MK |
41 | /**\r |
42 | See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".\r | |
43 | \r | |
44 | @param ECX MSR_PENTIUM_P5_MC_ADDR (0x00000000)\r | |
45 | @param EAX Lower 32-bits of MSR value.\r | |
46 | @param EDX Upper 32-bits of MSR value.\r | |
47 | \r | |
48 | <b>Example usage</b>\r | |
49 | @code\r | |
50 | UINT64 Msr;\r | |
51 | \r | |
52 | Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_ADDR);\r | |
53 | AsmWriteMsr64 (MSR_PENTIUM_P5_MC_ADDR, Msr);\r | |
54 | @endcode\r | |
634429c0 | 55 | @note MSR_PENTIUM_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.\r |
a1e8e34d | 56 | **/\r |
2f88bd3a | 57 | #define MSR_PENTIUM_P5_MC_ADDR 0x00000000\r |
a1e8e34d MK |
58 | \r |
59 | /**\r | |
60 | See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".\r | |
61 | \r | |
62 | @param ECX MSR_PENTIUM_P5_MC_TYPE (0x00000001)\r | |
63 | @param EAX Lower 32-bits of MSR value.\r | |
64 | @param EDX Upper 32-bits of MSR value.\r | |
65 | \r | |
66 | <b>Example usage</b>\r | |
67 | @code\r | |
68 | UINT64 Msr;\r | |
69 | \r | |
70 | Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_TYPE);\r | |
71 | AsmWriteMsr64 (MSR_PENTIUM_P5_MC_TYPE, Msr);\r | |
72 | @endcode\r | |
634429c0 | 73 | @note MSR_PENTIUM_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.\r |
a1e8e34d | 74 | **/\r |
2f88bd3a | 75 | #define MSR_PENTIUM_P5_MC_TYPE 0x00000001\r |
a1e8e34d MK |
76 | \r |
77 | /**\r | |
ba1a2d11 | 78 | See Section 17.17, "Time-Stamp Counter.".\r |
a1e8e34d MK |
79 | \r |
80 | @param ECX MSR_PENTIUM_TSC (0x00000010)\r | |
81 | @param EAX Lower 32-bits of MSR value.\r | |
82 | @param EDX Upper 32-bits of MSR value.\r | |
83 | \r | |
84 | <b>Example usage</b>\r | |
85 | @code\r | |
86 | UINT64 Msr;\r | |
87 | \r | |
88 | Msr = AsmReadMsr64 (MSR_PENTIUM_TSC);\r | |
89 | AsmWriteMsr64 (MSR_PENTIUM_TSC, Msr);\r | |
90 | @endcode\r | |
634429c0 | 91 | @note MSR_PENTIUM_TSC is defined as TSC in SDM.\r |
a1e8e34d | 92 | **/\r |
2f88bd3a | 93 | #define MSR_PENTIUM_TSC 0x00000010\r |
a1e8e34d MK |
94 | \r |
95 | /**\r | |
ba1a2d11 | 96 | See Section 18.6.9.1, "Control and Event Select Register (CESR).".\r |
a1e8e34d MK |
97 | \r |
98 | @param ECX MSR_PENTIUM_CESR (0x00000011)\r | |
99 | @param EAX Lower 32-bits of MSR value.\r | |
100 | @param EDX Upper 32-bits of MSR value.\r | |
101 | \r | |
102 | <b>Example usage</b>\r | |
103 | @code\r | |
104 | UINT64 Msr;\r | |
105 | \r | |
106 | Msr = AsmReadMsr64 (MSR_PENTIUM_CESR);\r | |
107 | AsmWriteMsr64 (MSR_PENTIUM_CESR, Msr);\r | |
108 | @endcode\r | |
634429c0 | 109 | @note MSR_PENTIUM_CESR is defined as CESR in SDM.\r |
a1e8e34d | 110 | **/\r |
2f88bd3a | 111 | #define MSR_PENTIUM_CESR 0x00000011\r |
a1e8e34d MK |
112 | \r |
113 | /**\r | |
ba1a2d11 | 114 | Section 18.6.9.3, "Events Counted.".\r |
a1e8e34d MK |
115 | \r |
116 | @param ECX MSR_PENTIUM_CTRn\r | |
117 | @param EAX Lower 32-bits of MSR value.\r | |
118 | @param EDX Upper 32-bits of MSR value.\r | |
119 | \r | |
120 | <b>Example usage</b>\r | |
121 | @code\r | |
122 | UINT64 Msr;\r | |
123 | \r | |
124 | Msr = AsmReadMsr64 (MSR_PENTIUM_CTR0);\r | |
125 | AsmWriteMsr64 (MSR_PENTIUM_CTR0, Msr);\r | |
126 | @endcode\r | |
634429c0 JF |
127 | @note MSR_PENTIUM_CTR0 is defined as CTR0 in SDM.\r |
128 | MSR_PENTIUM_CTR1 is defined as CTR1 in SDM.\r | |
a1e8e34d MK |
129 | @{\r |
130 | **/\r | |
2f88bd3a MK |
131 | #define MSR_PENTIUM_CTR0 0x00000012\r |
132 | #define MSR_PENTIUM_CTR1 0x00000013\r | |
a1e8e34d MK |
133 | /// @}\r |
134 | \r | |
135 | #endif\r |